]> git.sur5r.net Git - u-boot/commitdiff
85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards
authorKumar Gala <galak@kernel.crashing.org>
Tue, 2 Dec 2008 22:08:40 +0000 (16:08 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Fri, 23 Jan 2009 23:03:13 +0000 (17:03 -0600)
Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
board/freescale/mpc8536ds/tlb.c
board/freescale/mpc8572ds/tlb.c
include/configs/MPC8536DS.h
include/configs/MPC8540ADS.h
include/configs/MPC8541CDS.h
include/configs/MPC8544DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8555CDS.h
include/configs/MPC8560ADS.h
include/configs/MPC8568MDS.h
include/configs/MPC8572DS.h

index ec76d5c7952165dba1e60d55960c7346e3ca4b8f..35a13d449966471d07b953de1e514eb51b70a549 100644 (file)
@@ -63,7 +63,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 2, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_256K, 1),
 
index 594ff0560ecbebf7ec3cc2d489b80d258be358fe..d832f89742fe8cafec4234055e46e8e512ee3c91 100644 (file)
@@ -73,7 +73,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 5, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256K, 1),
 
index d537940f814374debcbe5d27beaf64b0e238d1c6..63a0f7e675c4558c7308c0bc1ef4cae55fc51d53 100644 (file)
@@ -361,6 +361,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_MEM_BUS                0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xffc00000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
@@ -370,6 +371,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0x90000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x08000000      /* 128M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc10000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
@@ -379,6 +381,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0x98000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x08000000      /* 128M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc20000
 #define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
@@ -388,6 +391,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xffc30000
 #define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc30000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
@@ -398,10 +402,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play */
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE3_IO_PHYS
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE3_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -414,7 +418,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 #endif
 
 #undef CONFIG_EEPRO100
index 645736bc3a2cff4161818351dd43df4dd9f175db..0d03b0b85f8595d4b6a1ce324560bba435d31317 100644 (file)
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
index ed628a0c33f69623292e4fe6c0456bd37634f2f6..fa82fbc6fde0497bee67383a7e547ecdf790c330 100644 (file)
@@ -345,6 +345,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
@@ -353,6 +354,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       0xa0000000
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT        0xe2100000
 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x100000        /* 1M */
index 4a43edf1c7c98686dd6043badea5943d6c29465d..59cfde6284b047f6a79d2c7e8238dc7761b0a556 100644 (file)
@@ -272,6 +272,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_MEM_BUS        0xc0000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0xc0000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe1000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
@@ -281,6 +282,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
@@ -290,6 +292,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
@@ -299,6 +302,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x00100000      /* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00100000      /* 1M */
@@ -310,10 +314,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
index 7110c3416b04c675e864d07a5faae7d33027f7a4..95bce9514792aa13081ac9c53c4ce40e4ac61f46 100644 (file)
@@ -372,6 +372,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
@@ -381,6 +382,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       0xa0000000
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT        0xe2800000
 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2800000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
@@ -391,6 +393,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /*   1M */
index 78fd683bf759d3894eefbfd98cb3bc7cdfcfdb46..6bf09613b09db3f8f0367dd360202d206184b97d 100644 (file)
@@ -343,6 +343,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
@@ -351,6 +352,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       0xa0000000
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT        0xe2100000
 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
index 4d18dd824de84940bceef1fd8d91609de352b064..3f78a6e120a098b56449147408eff746e9b2e1f2 100644 (file)
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
index fcaca1a4c8e4034c67618b5253c7a0e7392a617e..58ff52b33fdef8a4241739d975a83f0f3071ec28 100644 (file)
@@ -326,6 +326,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00800000      /* 8M */
@@ -334,6 +335,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe2800000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
index 8c4aa7d5260bbe45c34e1684881555479f366b42..0277a42a243bb4283d7216ea5a5dc2d22493a9cd 100644 (file)
@@ -384,6 +384,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xffc00000
 #define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
@@ -393,6 +394,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
@@ -402,6 +404,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
@@ -409,7 +412,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE1_IO_PHYS
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE1_IO_VIRT
 
 /* video */
 #define CONFIG_VIDEO