]> git.sur5r.net Git - u-boot/commitdiff
fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)
authorRoy Zang <tie-fei.zang@freescale.com>
Fri, 7 Jan 2011 06:24:27 +0000 (00:24 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 14 Jan 2011 07:32:22 +0000 (01:32 -0600)
False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
include/configs/P4080DS.h

index d5c34c867f709a7157a7b93877e2b08b7959741d..4e2cb4a6401554bbf6d3f3d8b3e64a9bea9df8c3 100644 (file)
@@ -55,6 +55,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
        puts("Work-around for Erratum ESDHC135 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
+       puts("Work-around for Erratum ESDHC136 enabled\n");
 #endif
        return 0;
 }
index 1d016c4d04b15b91264d1b2826343145ab9fe05a..354b22231474a7edeb82bacbc57d39c931d03a92 100644 (file)
@@ -394,6 +394,14 @@ int cpu_init_r(void)
        setup_mp();
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+       {
+               void *p;
+               p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+               setbits_be32(p, 1 << (31 - 14));
+       }
+#endif
+
 #ifdef CONFIG_SYS_LBC_LCRR
        /*
         * Modify the CLKDIV field of LCRR register to improve the writing
index a15dd761b8f4e04a258acef024753461918dfa04..4dd7faa1bb176e892a5d41a13eec98652c55826a 100644 (file)
@@ -37,6 +37,7 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8