QE/DeepSleep: add QE deepsleep support for mpc85xx

Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 6561ce644e72e63f2c624256c4f710ab5b26b8db..4dc528bc810974be4f19f2612ebb1a4ae82ff3dd 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -119,10 +119,6 @@
 
 #define DCU_LAYER_MAX_NUM                      16
 
-#define QE_MURAM_SIZE          0x6000UL
-#define MAX_QE_RISC            1
-#define QE_NUM_OF_SNUM         28
-
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA

diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index f924e7f482dc329d0dce0a9ffd5229dfc5ab294a..9e4132c64edc21437f59056b7c2ca4b8ba606071 100644 (file)
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -7,6 +7,9 @@
 #include <common.h>
 #include <asm/immap_85xx.h>
 #include "sleep.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,6 +68,11 @@ static void dp_resume_prepare(void)
        disable_cpc_sram();
 #endif
        enable_cpc();
+
+#ifdef CONFIG_U_QE
+       u_qe_resume();
+#endif
+
 }
 
 int fsl_dp_resume(void)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index d24651b5ba2b786e2a050cb3d98204d130365d6c..84e1433d9ee746e847fd11d2c283652364952f5b 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -196,6 +196,18 @@ void u_qe_init(void)
 }
 #endif
 
+#ifdef CONFIG_U_QE
+void u_qe_resume(void)
+{
+       qe_map_t *qe_immrr;
+       uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */
+       qe_immrr = (qe_map_t *)qe_base;
+
+       u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
+       out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
 void qe_reset(void)
 {
        qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -580,6 +592,76 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
 }
 #endif
 
+#ifdef CONFIG_U_QE
+int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
+{
+       unsigned int i;
+       unsigned int j;
+       const struct qe_header *hdr;
+       const u32 *code;
+#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_PPC
+       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#else
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+#endif
+#endif
+
+       if (!firmware)
+               return -EINVAL;
+
+       hdr = &firmware->header;
+
+       /* Check the magic */
+       if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+           (hdr->magic[2] != 'F')) {
+#ifdef CONFIG_DEEP_SLEEP
+               setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
+               return -EPERM;
+       }
+
+       /*
+        * If the microcode calls for it, split the I-RAM.
+        */
+       if (!firmware->split) {
+               out_be16(&qe_immrr->cp.cercr,
+                        in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
+       }
+
+       /* Loop through each microcode. */
+       for (i = 0; i < firmware->count; i++) {
+               const struct qe_microcode *ucode = &firmware->microcode[i];
+
+               /* Upload a microcode if it's present */
+               if (!ucode->code_offset)
+                       return 0;
+
+               code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
+
+               /* Use auto-increment */
+               out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
+                       QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+
+               for (i = 0; i < be32_to_cpu(ucode->count); i++)
+                       out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
+
+               /* Program the traps for this processor */
+               for (j = 0; j < 16; j++) {
+                       u32 trap = be32_to_cpu(ucode->traps[j]);
+
+                       if (trap)
+                               out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
+               }
+
+               /* Enable traps */
+               out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+       }
+
+       return 0;
+}
+#endif
+
 struct qe_firmware_info *qe_get_firmware_info(void)
 {
        return qe_firmware_uploaded ? &qe_firmware_info : NULL;

diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 33878f897b0177d87578092af1edceb08883e674..77b18e928ff04bc67e19b0f16cfe6cc250017a19 100644 (file)
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -11,6 +11,9 @@
 #define __QE_H__
 
 #include "common.h"
+#ifdef CONFIG_U_QE
+#include <linux/immap_qe.h>
+#endif
 
 #define QE_NUM_OF_BRGS 16
 #define UCC_MAX_NUM    8
@@ -288,6 +291,9 @@ void qe_reset(void);
 #ifdef CONFIG_U_QE
 void u_qe_init(void);
 int u_qe_upload_firmware(const struct qe_firmware *firmware);
+void u_qe_resume(void);
+int u_qe_firmware_resume(const struct qe_firmware *firmware,
+                        qe_map_t *qe_immrr);
 #endif
 
 #endif /* __QE_H__ */

diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
index b317dcb5fe88d9072f5aad93b6e7cfeedd17d0a6..6d1f88ec2e1d5a606c3f95ccc41c6e3879266441 100644 (file)
--- a/include/linux/immap_qe.h
+++ b/include/linux/immap_qe.h
@@ -24,6 +24,18 @@
 #endif
 #endif
 
+#ifdef CONFIG_LS102XA
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+#endif
+
+#ifdef CONFIG_PPC
+#define QE_IMMR_OFFSET         0x00140000
+#else
+#define QE_IMMR_OFFSET         0x01400000
+#endif
+
 /* QE I-RAM */
 typedef struct qe_iram {
        u32 iadd;               /* I-RAM Address Register */