ifdef CONFIG_DM_SERIAL
obj-y += serial-uclass.o
+obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
else
obj-y += serial.o
+obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
endif
obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
-obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
+#include <errno.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
+#include <serial_pl01x.h>
#include <linux/compiler.h>
-#include "serial_pl01x.h"
+#include "serial_pl01x_internal.h"
-/*
- * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
- * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
- * Versatile PB has four UARTs.
- */
-#define CONSOLE_PORT CONFIG_CONS_INDEX
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
+static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
+static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
-static void pl01x_putc (int portnum, char c);
-static int pl01x_getc (int portnum);
-static int pl01x_tstc (int portnum);
-unsigned int baudrate = CONFIG_BAUDRATE;
DECLARE_GLOBAL_DATA_PTR;
-static struct pl01x_regs *pl01x_get_regs(int portnum)
+static int pl01x_putc(struct pl01x_regs *regs, char c)
{
- return (struct pl01x_regs *) port[portnum];
-}
-
-#ifdef CONFIG_PL010_SERIAL
-
-static int pl01x_serial_init(void)
-{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
- unsigned int divisor;
-
- /* First, disable everything */
- writel(0, ®s->pl010_cr);
+ /* Wait until there is space in the FIFO */
+ if (readl(®s->fr) & UART_PL01x_FR_TXFF)
+ return -EAGAIN;
- /* Set baud rate */
- switch (baudrate) {
- case 9600:
- divisor = UART_PL010_BAUD_9600;
- break;
+ /* Send the character */
+ writel(c, ®s->dr);
- case 19200:
- divisor = UART_PL010_BAUD_9600;
- break;
+ return 0;
+}
- case 38400:
- divisor = UART_PL010_BAUD_38400;
- break;
+static int pl01x_getc(struct pl01x_regs *regs)
+{
+ unsigned int data;
- case 57600:
- divisor = UART_PL010_BAUD_57600;
- break;
+ /* Wait until there is data in the FIFO */
+ if (readl(®s->fr) & UART_PL01x_FR_RXFE)
+ return -EAGAIN;
- case 115200:
- divisor = UART_PL010_BAUD_115200;
- break;
+ data = readl(®s->dr);
- default:
- divisor = UART_PL010_BAUD_38400;
+ /* Check for an error flag */
+ if (data & 0xFFFFFF00) {
+ /* Clear the error */
+ writel(0xFFFFFFFF, ®s->ecr);
+ return -1;
}
- writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
- writel(divisor & 0xff, ®s->pl010_lcrl);
-
- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
-
- /* Finally, enable the UART */
- writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
-
- return 0;
+ return (int) data;
}
-#endif /* CONFIG_PL010_SERIAL */
-
-#ifdef CONFIG_PL011_SERIAL
+static int pl01x_tstc(struct pl01x_regs *regs)
+{
+ WATCHDOG_RESET();
+ return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
+}
-static int pl01x_serial_init(void)
+static int pl01x_generic_serial_init(struct pl01x_regs *regs,
+ enum pl01x_type type)
{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
- unsigned int temp;
- unsigned int divider;
- unsigned int remainder;
- unsigned int fraction;
unsigned int lcr;
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- /* Empty RX fifo if necessary */
- if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
- while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
- readl(®s->dr);
+ if (type == TYPE_PL011) {
+ /* Empty RX fifo if necessary */
+ if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
+ while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
+ readl(®s->dr);
+ }
}
#endif
/* First, disable everything */
- writel(0, ®s->pl011_cr);
-
- /*
- * Set baud rate
- *
- * IBRD = UART_CLK / (16 * BAUD_RATE)
- * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
- */
- temp = 16 * baudrate;
- divider = CONFIG_PL011_CLOCK / temp;
- remainder = CONFIG_PL011_CLOCK % temp;
- temp = (8 * remainder) / baudrate;
- fraction = (temp >> 1) + (temp & 1);
-
- writel(divider, ®s->pl011_ibrd);
- writel(fraction, ®s->pl011_fbrd);
+ writel(0, ®s->pl010_cr);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
writel(lcr, ®s->pl011_lcrh);
+ switch (type) {
+ case TYPE_PL010:
+ break;
+ case TYPE_PL011: {
#ifdef CONFIG_PL011_SERIAL_RLCR
- {
int i;
/*
writel(lcr, ®s->pl011_rlcr);
/* lcrh needs to be set again for change to be effective */
writel(lcr, ®s->pl011_lcrh);
- }
#endif
- /* Finally, enable the UART */
- writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
- UART_PL011_CR_RTS, ®s->pl011_cr);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
return 0;
}
-#endif /* CONFIG_PL011_SERIAL */
-
-static void pl01x_serial_putc(const char c)
+static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
+ int clock, int baudrate)
{
- if (c == '\n')
- pl01x_putc (CONSOLE_PORT, '\r');
+ switch (type) {
+ case TYPE_PL010: {
+ unsigned int divisor;
+
+ switch (baudrate) {
+ case 9600:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 19200:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 38400:
+ divisor = UART_PL010_BAUD_38400;
+ break;
+ case 57600:
+ divisor = UART_PL010_BAUD_57600;
+ break;
+ case 115200:
+ divisor = UART_PL010_BAUD_115200;
+ break;
+ default:
+ divisor = UART_PL010_BAUD_38400;
+ }
+
+ writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
+ writel(divisor & 0xff, ®s->pl010_lcrl);
+
+ /* Finally, enable the UART */
+ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
+ break;
+ }
+ case TYPE_PL011: {
+ unsigned int temp;
+ unsigned int divider;
+ unsigned int remainder;
+ unsigned int fraction;
- pl01x_putc (CONSOLE_PORT, c);
-}
+ /*
+ * Set baud rate
+ *
+ * IBRD = UART_CLK / (16 * BAUD_RATE)
+ * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
+ * / (16 * BAUD_RATE))
+ */
+ temp = 16 * baudrate;
+ divider = clock / temp;
+ remainder = clock % temp;
+ temp = (8 * remainder) / baudrate;
+ fraction = (temp >> 1) + (temp & 1);
+
+ writel(divider, ®s->pl011_ibrd);
+ writel(fraction, ®s->pl011_fbrd);
+
+ /* Finally, enable the UART */
+ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
+ UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
-static int pl01x_serial_getc(void)
-{
- return pl01x_getc (CONSOLE_PORT);
+ return 0;
}
-static int pl01x_serial_tstc(void)
+#ifndef CONFIG_DM_SERIAL
+static void pl01x_serial_init_baud(int baudrate)
{
- return pl01x_tstc (CONSOLE_PORT);
+ int clock = 0;
+
+#if defined(CONFIG_PL010_SERIAL)
+ pl01x_type = TYPE_PL010;
+#elif defined(CONFIG_PL011_SERIAL)
+ pl01x_type = TYPE_PL011;
+ clock = CONFIG_PL011_CLOCK;
+#endif
+ base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
+
+ pl01x_generic_serial_init(base_regs, pl01x_type);
+ pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
}
-static void pl01x_serial_setbrg(void)
+/*
+ * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
+ * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
+ * Versatile PB has four UARTs.
+ */
+int pl01x_serial_init(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+ pl01x_serial_init_baud(CONFIG_BAUDRATE);
- baudrate = gd->baudrate;
- /*
- * Flush FIFO and wait for non-busy before changing baudrate to avoid
- * crap in console
- */
- while (!(readl(®s->fr) & UART_PL01x_FR_TXFE))
- WATCHDOG_RESET();
- while (readl(®s->fr) & UART_PL01x_FR_BUSY)
- WATCHDOG_RESET();
- serial_init();
+ return 0;
}
-static void pl01x_putc (int portnum, char c)
+static void pl01x_serial_putc(const char c)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
-
- /* Wait until there is space in the FIFO */
- while (readl(®s->fr) & UART_PL01x_FR_TXFF)
- WATCHDOG_RESET();
+ if (c == '\n')
+ while (pl01x_putc(base_regs, '\r') == -EAGAIN);
- /* Send the character */
- writel(c, ®s->dr);
+ while (pl01x_putc(base_regs, c) == -EAGAIN);
}
-static int pl01x_getc (int portnum)
+static int pl01x_serial_getc(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
- unsigned int data;
+ while (1) {
+ int ch = pl01x_getc(base_regs);
- /* Wait until there is data in the FIFO */
- while (readl(®s->fr) & UART_PL01x_FR_RXFE)
- WATCHDOG_RESET();
+ if (ch == -EAGAIN) {
+ WATCHDOG_RESET();
+ continue;
+ }
- data = readl(®s->dr);
-
- /* Check for an error flag */
- if (data & 0xFFFFFF00) {
- /* Clear the error */
- writel(0xFFFFFFFF, ®s->ecr);
- return -1;
+ return ch;
}
-
- return (int) data;
}
-static int pl01x_tstc (int portnum)
+static int pl01x_serial_tstc(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
+ return pl01x_tstc(base_regs);
+}
- WATCHDOG_RESET();
- return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
+static void pl01x_serial_setbrg(void)
+{
+ /*
+ * Flush FIFO and wait for non-busy before changing baudrate to avoid
+ * crap in console
+ */
+ while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
+ WATCHDOG_RESET();
+ while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
+ WATCHDOG_RESET();
+ pl01x_serial_init_baud(gd->baudrate);
}
static struct serial_device pl01x_serial_drv = {
{
return &pl01x_serial_drv;
}
+
+#endif /* nCONFIG_DM_SERIAL */
+++ /dev/null
-/*
- * (C) Copyright 2003, 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * ARM PrimeCell UART's (PL010 & PL011)
- * ------------------------------------
- *
- * Definitions common to both PL010 & PL011
- *
- */
-
-#ifndef __ASSEMBLY__
-/*
- * We can use a combined structure for PL010 and PL011, because they overlap
- * only in common registers.
- */
-struct pl01x_regs {
- u32 dr; /* 0x00 Data register */
- u32 ecr; /* 0x04 Error clear register (Write) */
- u32 pl010_lcrh; /* 0x08 Line control register, high byte */
- u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
- u32 pl010_lcrl; /* 0x10 Line control register, low byte */
- u32 pl010_cr; /* 0x14 Control register */
- u32 fr; /* 0x18 Flag register (Read only) */
-#ifdef CONFIG_PL011_SERIAL_RLCR
- u32 pl011_rlcr; /* 0x1c Receive line control register */
-#else
- u32 reserved;
-#endif
- u32 ilpr; /* 0x20 IrDA low-power counter register */
- u32 pl011_ibrd; /* 0x24 Integer baud rate register */
- u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
- u32 pl011_lcrh; /* 0x2C Line control register */
- u32 pl011_cr; /* 0x30 Control register */
-};
-#endif
-
-#define UART_PL01x_RSR_OE 0x08
-#define UART_PL01x_RSR_BE 0x04
-#define UART_PL01x_RSR_PE 0x02
-#define UART_PL01x_RSR_FE 0x01
-
-#define UART_PL01x_FR_TXFE 0x80
-#define UART_PL01x_FR_RXFF 0x40
-#define UART_PL01x_FR_TXFF 0x20
-#define UART_PL01x_FR_RXFE 0x10
-#define UART_PL01x_FR_BUSY 0x08
-#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
-
-/*
- * PL010 definitions
- *
- */
-#define UART_PL010_CR_LPE (1 << 7)
-#define UART_PL010_CR_RTIE (1 << 6)
-#define UART_PL010_CR_TIE (1 << 5)
-#define UART_PL010_CR_RIE (1 << 4)
-#define UART_PL010_CR_MSIE (1 << 3)
-#define UART_PL010_CR_IIRLP (1 << 2)
-#define UART_PL010_CR_SIREN (1 << 1)
-#define UART_PL010_CR_UARTEN (1 << 0)
-
-#define UART_PL010_LCRH_WLEN_8 (3 << 5)
-#define UART_PL010_LCRH_WLEN_7 (2 << 5)
-#define UART_PL010_LCRH_WLEN_6 (1 << 5)
-#define UART_PL010_LCRH_WLEN_5 (0 << 5)
-#define UART_PL010_LCRH_FEN (1 << 4)
-#define UART_PL010_LCRH_STP2 (1 << 3)
-#define UART_PL010_LCRH_EPS (1 << 2)
-#define UART_PL010_LCRH_PEN (1 << 1)
-#define UART_PL010_LCRH_BRK (1 << 0)
-
-
-#define UART_PL010_BAUD_460800 1
-#define UART_PL010_BAUD_230400 3
-#define UART_PL010_BAUD_115200 7
-#define UART_PL010_BAUD_57600 15
-#define UART_PL010_BAUD_38400 23
-#define UART_PL010_BAUD_19200 47
-#define UART_PL010_BAUD_14400 63
-#define UART_PL010_BAUD_9600 95
-#define UART_PL010_BAUD_4800 191
-#define UART_PL010_BAUD_2400 383
-#define UART_PL010_BAUD_1200 767
-/*
- * PL011 definitions
- *
- */
-#define UART_PL011_LCRH_SPS (1 << 7)
-#define UART_PL011_LCRH_WLEN_8 (3 << 5)
-#define UART_PL011_LCRH_WLEN_7 (2 << 5)
-#define UART_PL011_LCRH_WLEN_6 (1 << 5)
-#define UART_PL011_LCRH_WLEN_5 (0 << 5)
-#define UART_PL011_LCRH_FEN (1 << 4)
-#define UART_PL011_LCRH_STP2 (1 << 3)
-#define UART_PL011_LCRH_EPS (1 << 2)
-#define UART_PL011_LCRH_PEN (1 << 1)
-#define UART_PL011_LCRH_BRK (1 << 0)
-
-#define UART_PL011_CR_CTSEN (1 << 15)
-#define UART_PL011_CR_RTSEN (1 << 14)
-#define UART_PL011_CR_OUT2 (1 << 13)
-#define UART_PL011_CR_OUT1 (1 << 12)
-#define UART_PL011_CR_RTS (1 << 11)
-#define UART_PL011_CR_DTR (1 << 10)
-#define UART_PL011_CR_RXE (1 << 9)
-#define UART_PL011_CR_TXE (1 << 8)
-#define UART_PL011_CR_LPE (1 << 7)
-#define UART_PL011_CR_IIRLP (1 << 2)
-#define UART_PL011_CR_SIREN (1 << 1)
-#define UART_PL011_CR_UARTEN (1 << 0)
-
-#define UART_PL011_IMSC_OEIM (1 << 10)
-#define UART_PL011_IMSC_BEIM (1 << 9)
-#define UART_PL011_IMSC_PEIM (1 << 8)
-#define UART_PL011_IMSC_FEIM (1 << 7)
-#define UART_PL011_IMSC_RTIM (1 << 6)
-#define UART_PL011_IMSC_TXIM (1 << 5)
-#define UART_PL011_IMSC_RXIM (1 << 4)
-#define UART_PL011_IMSC_DSRMIM (1 << 3)
-#define UART_PL011_IMSC_DCDMIM (1 << 2)
-#define UART_PL011_IMSC_CTSMIM (1 << 1)
-#define UART_PL011_IMSC_RIMIM (1 << 0)
--- /dev/null
+/*
+ * (C) Copyright 2003, 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * ARM PrimeCell UART's (PL010 & PL011)
+ * ------------------------------------
+ *
+ * Definitions common to both PL010 & PL011
+ *
+ */
+
+#ifndef __ASSEMBLY__
+/*
+ * We can use a combined structure for PL010 and PL011, because they overlap
+ * only in common registers.
+ */
+struct pl01x_regs {
+ u32 dr; /* 0x00 Data register */
+ u32 ecr; /* 0x04 Error clear register (Write) */
+ u32 pl010_lcrh; /* 0x08 Line control register, high byte */
+ u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
+ u32 pl010_lcrl; /* 0x10 Line control register, low byte */
+ u32 pl010_cr; /* 0x14 Control register */
+ u32 fr; /* 0x18 Flag register (Read only) */
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ u32 pl011_rlcr; /* 0x1c Receive line control register */
+#else
+ u32 reserved;
+#endif
+ u32 ilpr; /* 0x20 IrDA low-power counter register */
+ u32 pl011_ibrd; /* 0x24 Integer baud rate register */
+ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
+ u32 pl011_lcrh; /* 0x2C Line control register */
+ u32 pl011_cr; /* 0x30 Control register */
+};
+#endif
+
+#define UART_PL01x_RSR_OE 0x08
+#define UART_PL01x_RSR_BE 0x04
+#define UART_PL01x_RSR_PE 0x02
+#define UART_PL01x_RSR_FE 0x01
+
+#define UART_PL01x_FR_TXFE 0x80
+#define UART_PL01x_FR_RXFF 0x40
+#define UART_PL01x_FR_TXFF 0x20
+#define UART_PL01x_FR_RXFE 0x10
+#define UART_PL01x_FR_BUSY 0x08
+#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
+
+/*
+ * PL010 definitions
+ *
+ */
+#define UART_PL010_CR_LPE (1 << 7)
+#define UART_PL010_CR_RTIE (1 << 6)
+#define UART_PL010_CR_TIE (1 << 5)
+#define UART_PL010_CR_RIE (1 << 4)
+#define UART_PL010_CR_MSIE (1 << 3)
+#define UART_PL010_CR_IIRLP (1 << 2)
+#define UART_PL010_CR_SIREN (1 << 1)
+#define UART_PL010_CR_UARTEN (1 << 0)
+
+#define UART_PL010_LCRH_WLEN_8 (3 << 5)
+#define UART_PL010_LCRH_WLEN_7 (2 << 5)
+#define UART_PL010_LCRH_WLEN_6 (1 << 5)
+#define UART_PL010_LCRH_WLEN_5 (0 << 5)
+#define UART_PL010_LCRH_FEN (1 << 4)
+#define UART_PL010_LCRH_STP2 (1 << 3)
+#define UART_PL010_LCRH_EPS (1 << 2)
+#define UART_PL010_LCRH_PEN (1 << 1)
+#define UART_PL010_LCRH_BRK (1 << 0)
+
+
+#define UART_PL010_BAUD_460800 1
+#define UART_PL010_BAUD_230400 3
+#define UART_PL010_BAUD_115200 7
+#define UART_PL010_BAUD_57600 15
+#define UART_PL010_BAUD_38400 23
+#define UART_PL010_BAUD_19200 47
+#define UART_PL010_BAUD_14400 63
+#define UART_PL010_BAUD_9600 95
+#define UART_PL010_BAUD_4800 191
+#define UART_PL010_BAUD_2400 383
+#define UART_PL010_BAUD_1200 767
+/*
+ * PL011 definitions
+ *
+ */
+#define UART_PL011_LCRH_SPS (1 << 7)
+#define UART_PL011_LCRH_WLEN_8 (3 << 5)
+#define UART_PL011_LCRH_WLEN_7 (2 << 5)
+#define UART_PL011_LCRH_WLEN_6 (1 << 5)
+#define UART_PL011_LCRH_WLEN_5 (0 << 5)
+#define UART_PL011_LCRH_FEN (1 << 4)
+#define UART_PL011_LCRH_STP2 (1 << 3)
+#define UART_PL011_LCRH_EPS (1 << 2)
+#define UART_PL011_LCRH_PEN (1 << 1)
+#define UART_PL011_LCRH_BRK (1 << 0)
+
+#define UART_PL011_CR_CTSEN (1 << 15)
+#define UART_PL011_CR_RTSEN (1 << 14)
+#define UART_PL011_CR_OUT2 (1 << 13)
+#define UART_PL011_CR_OUT1 (1 << 12)
+#define UART_PL011_CR_RTS (1 << 11)
+#define UART_PL011_CR_DTR (1 << 10)
+#define UART_PL011_CR_RXE (1 << 9)
+#define UART_PL011_CR_TXE (1 << 8)
+#define UART_PL011_CR_LPE (1 << 7)
+#define UART_PL011_CR_IIRLP (1 << 2)
+#define UART_PL011_CR_SIREN (1 << 1)
+#define UART_PL011_CR_UARTEN (1 << 0)
+
+#define UART_PL011_IMSC_OEIM (1 << 10)
+#define UART_PL011_IMSC_BEIM (1 << 9)
+#define UART_PL011_IMSC_PEIM (1 << 8)
+#define UART_PL011_IMSC_FEIM (1 << 7)
+#define UART_PL011_IMSC_RTIM (1 << 6)
+#define UART_PL011_IMSC_TXIM (1 << 5)
+#define UART_PL011_IMSC_RXIM (1 << 4)
+#define UART_PL011_IMSC_DSRMIM (1 << 3)
+#define UART_PL011_IMSC_DCDMIM (1 << 2)
+#define UART_PL011_IMSC_CTSMIM (1 << 1)
+#define UART_PL011_IMSC_RIMIM (1 << 0)
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __serial_pl01x_h
+#define __serial_pl01x_h
+
+enum pl01x_type {
+ TYPE_PL010,
+ TYPE_PL011,
+};
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ * @type: Port type
+ * @clock: Input clock rate, used for calculating the baud rate divisor
+ */
+struct pl01x_serial_platdata {
+ unsigned long base;
+ enum pl01x_type type;
+ unsigned int clock;
+};
+
+#endif
projects / u-boot / commitdiff