#include <common.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#include <common.h>
#include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/clocks_omap3.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_CLOCKS_H_
+#define _OMAP24XX_CLOCKS_H_
+
+#define COMMIT_DIVIDERS 0x1
+
+#define MODE_BYPASS_FAST 0x2
+#define APLL_LOCK 0xc
+#ifdef CONFIG_APTIX
+#define DPLL_LOCK 0x1 /* stay in bypass mode */
+#else
+#define DPLL_LOCK 0x3 /* DPLL lock */
+#endif
+
+/****************************************************************************;
+; PRCM Scheme II
+;
+; Enable clocks and DPLL for:
+; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
+; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
+; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
+; DSPI=100 6 CM_CLKSEL_DSP[6:5]
+; DSP_S bypass CM_CLKSEL_DSP[7]
+; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
+; IVAF=100 auto
+; IVAI auto
+; IVA_MPU auto
+; IVA_S bypass CM_CLKSEL_DSP[13]
+; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
+; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
+; SSI_SSTF=100 auto
+; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
+; L4=100Mhz 6
+; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define II_DPLL_OUT_X2 0x2 /* x2 core out */
+#define II_MPU_DIV 0x2 /* mpu = core/2 */
+#define II_DSP_DIV 0x343 /* dsp & iva divider */
+#define II_GFX_DIV 0x2
+#define II_BUS_DIV 0x04601026
+#define II_DPLL_300 0x01832100
+
+/****************************************************************************;
+; PRCM Scheme III
+;
+; Enable clocks and DPLL for:
+; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
+; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
+; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
+; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
+; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
+; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
+; IVAF=88.67 auto
+; IVAI auto
+; IVA_MPU auto
+; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
+; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
+; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
+; SSI_SSTF=88.67 auto
+; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
+; L4=66.5Mhz /8
+; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define III_DPLL_OUT_X2 0x2 /* x2 core out */
+#define III_MPU_DIV 0x2 /* mpu = core/2 */
+#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
+#define III_GFX_DIV 0x2
+#define III_BUS_DIV 0x08301044
+#define III_DPLL_266 0x01885500
+
+/* set defaults for boot up */
+#ifdef PRCM_CONFIG_II
+# define DPLL_OUT II_DPLL_OUT_X2
+# define MPU_DIV II_MPU_DIV
+# define DSP_DIV II_DSP_DIV
+# define GFX_DIV II_GFX_DIV
+# define BUS_DIV II_BUS_DIV
+# define DPLL_VAL II_DPLL_300
+#elif PRCM_CONFIG_III
+# define DPLL_OUT III_DPLL_OUT_X2
+# define MPU_DIV III_MPU_DIV
+# define DSP_DIV III_DSP_DIV
+# define GFX_DIV III_GFX_DIV
+# define BUS_DIV III_BUS_DIV
+# define DPLL_VAL III_DPLL_266
+#endif
+
+/* lock delay time out */
+#define LDELAY 12000000
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS 0x1
-
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK 0xc
-#ifdef CONFIG_APTIX
-#define DPLL_LOCK 0x1 /* stay in bypass mode */
-#else
-#define DPLL_LOCK 0x3 /* DPLL lock */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II
-;
-; Enable clocks and DPLL for:
-; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
-; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
-; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
-; DSPI=100 6 CM_CLKSEL_DSP[6:5]
-; DSP_S bypass CM_CLKSEL_DSP[7]
-; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
-; IVAF=100 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S bypass CM_CLKSEL_DSP[13]
-; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
-; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=100 auto
-; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
-; L4=100Mhz 6
-; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2 0x2 /* x2 core out */
-#define II_MPU_DIV 0x2 /* mpu = core/2 */
-#define II_DSP_DIV 0x343 /* dsp & iva divider */
-#define II_GFX_DIV 0x2
-#define II_BUS_DIV 0x04601026
-#define II_DPLL_300 0x01832100
-
-/****************************************************************************;
-; PRCM Scheme III
-;
-; Enable clocks and DPLL for:
-; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
-; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
-; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
-; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
-; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
-; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
-; IVAF=88.67 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
-; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
-; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=88.67 auto
-; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
-; L4=66.5Mhz /8
-; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2 0x2 /* x2 core out */
-#define III_MPU_DIV 0x2 /* mpu = core/2 */
-#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV 0x2
-#define III_BUS_DIV 0x08301044
-#define III_DPLL_266 0x01885500
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_II
-# define DPLL_OUT II_DPLL_OUT_X2
-# define MPU_DIV II_MPU_DIV
-# define DSP_DIV II_DSP_DIV
-# define GFX_DIV II_GFX_DIV
-# define BUS_DIV II_BUS_DIV
-# define DPLL_VAL II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT III_DPLL_OUT_X2
-# define MPU_DIV III_MPU_DIV
-# define DSP_DIV III_DSP_DIV
-# define GFX_DIV III_GFX_DIV
-# define BUS_DIV III_BUS_DIV
-# define DPLL_VAL III_DPLL_266
-#endif
-
-/* lock delay time out */
-#define LDELAY 12000000
-
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY 12000000
+
+#define S12M 12000000
+#define S13M 13000000
+#define S19_2M 19200000
+#define S24M 24000000
+#define S26M 26000000
+#define S38_4M 38400000
+
+#define FCK_IVA2_ON 0x00000001
+#define FCK_CORE1_ON 0x03fffe29
+#define ICK_CORE1_ON 0x3ffffffb
+#define ICK_CORE2_ON 0x0000001f
+#define FCK_WKUP_ON 0x000000e9
+#define ICK_WKUP_ON 0x0000003f
+#define FCK_DSS_ON 0x00000005
+#define ICK_DSS_ON 0x00000001
+#define FCK_CAM_ON 0x00000001
+#define ICK_CAM_ON 0x00000001
+#define FCK_PER_ON 0x0003ffff
+#define ICK_PER_ON 0x0003ffff
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+} dpll_param;
+
+struct dpll_per_36x_param {
+ unsigned int sys_clk;
+ unsigned int m;
+ unsigned int n;
+ unsigned int m2;
+ unsigned int m3;
+ unsigned int m4;
+ unsigned int m5;
+ unsigned int m6;
+ unsigned int m2div;
+};
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
+
+extern dpll_param *get_36x_mpu_dpll_param(void);
+extern dpll_param *get_36x_iva_dpll_param(void);
+extern dpll_param *get_36x_core_dpll_param(void);
+extern dpll_param *get_36x_per_dpll_param(void);
+
+extern void *_end_vect, *_start;
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _CLOCKS_H_
-#define _CLOCKS_H_
-
-#define LDELAY 12000000
-
-#define S12M 12000000
-#define S13M 13000000
-#define S19_2M 19200000
-#define S24M 24000000
-#define S26M 26000000
-#define S38_4M 38400000
-
-#define FCK_IVA2_ON 0x00000001
-#define FCK_CORE1_ON 0x03fffe29
-#define ICK_CORE1_ON 0x3ffffffb
-#define ICK_CORE2_ON 0x0000001f
-#define FCK_WKUP_ON 0x000000e9
-#define ICK_WKUP_ON 0x0000003f
-#define FCK_DSS_ON 0x00000005
-#define ICK_DSS_ON 0x00000001
-#define FCK_CAM_ON 0x00000001
-#define ICK_CAM_ON 0x00000001
-#define FCK_PER_ON 0x0003ffff
-#define ICK_PER_ON 0x0003ffff
-
-/* Used to index into DPLL parameter tables */
-typedef struct {
- unsigned int m;
- unsigned int n;
- unsigned int fsel;
- unsigned int m2;
-} dpll_param;
-
-struct dpll_per_36x_param {
- unsigned int sys_clk;
- unsigned int m;
- unsigned int n;
- unsigned int m2;
- unsigned int m3;
- unsigned int m4;
- unsigned int m5;
- unsigned int m6;
- unsigned int m2div;
-};
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param *get_mpu_dpll_param(void);
-extern dpll_param *get_iva_dpll_param(void);
-extern dpll_param *get_core_dpll_param(void);
-extern dpll_param *get_per_dpll_param(void);
-extern dpll_param *get_per2_dpll_param(void);
-
-extern dpll_param *get_36x_mpu_dpll_param(void);
-extern dpll_param *get_36x_iva_dpll_param(void);
-extern dpll_param *get_36x_core_dpll_param(void);
-extern dpll_param *get_36x_per_dpll_param(void);
-
-extern void *_end_vect, *_start;
-
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY 1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
+#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE 0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR 0x12
+#define SMPS_REG_ADDR_VCORE1 0x55
+#define SMPS_REG_ADDR_VCORE2 0x5B
+#define SMPS_REG_ADDR_VCORE3 0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR 0x60
+#define TPS62361_REG_ADDR_SET0 0x0
+#define TPS62361_REG_ADDR_SET1 0x1
+#define TPS62361_REG_ADDR_SET2 0x2
+#define TPS62361_REG_ADDR_SET3 0x3
+#define TPS62361_REG_ADDR_CTRL 0x4
+#define TPS62361_REG_ADDR_TEMP 0x5
+#define TPS62361_REG_ADDR_RMP_CTRL 0x6
+#define TPS62361_REG_ADDR_CHIP_ID 0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
+
+#define TPS62361_BASE_VOLT_MV 500
+#define TPS62361_VSEL0_GPIO 7
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT 1
+#define AUXCLK_SRCSELECT_MASK (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT 16
+#define AUXCLK_CLKDIV_MASK (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK 0
+#define AUXCLK_SRCSELECT_CORE_DPLL 1
+#define AUXCLK_SRCSELECT_PER_DPLL 2
+#define AUXCLK_SRCSELECT_ALTERNATE 3
+
+#define AUXCLK_CLKDIV_2 1
+#define AUXCLK_CLKDIV_16 0xF
+
+/* ALTCLKSRC */
+#define ALTCLKSRC_MODE_MASK 3
+#define ALTCLKSRC_ENABLE_INT_MASK 4
+#define ALTCLKSRC_ENABLE_EXT_MASK 8
+
+#define ALTCLKSRC_MODE_ACTIVE 1
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+struct omap4_scrm_regs {
+ u32 revision; /* 0x0000 */
+ u32 pad00[63];
+ u32 clksetuptime; /* 0x0100 */
+ u32 pmicsetuptime; /* 0x0104 */
+ u32 pad01[2];
+ u32 altclksrc; /* 0x0110 */
+ u32 pad02[2];
+ u32 c2cclkm; /* 0x011c */
+ u32 pad03[56];
+ u32 extclkreq; /* 0x0200 */
+ u32 accclkreq; /* 0x0204 */
+ u32 pwrreq; /* 0x0208 */
+ u32 pad04[1];
+ u32 auxclkreq0; /* 0x0210 */
+ u32 auxclkreq1; /* 0x0214 */
+ u32 auxclkreq2; /* 0x0218 */
+ u32 auxclkreq3; /* 0x021c */
+ u32 auxclkreq4; /* 0x0220 */
+ u32 auxclkreq5; /* 0x0224 */
+ u32 pad05[3];
+ u32 c2cclkreq; /* 0x0234 */
+ u32 pad06[54];
+ u32 auxclk0; /* 0x0310 */
+ u32 auxclk1; /* 0x0314 */
+ u32 auxclk2; /* 0x0318 */
+ u32 auxclk3; /* 0x031c */
+ u32 auxclk4; /* 0x0320 */
+ u32 auxclk5; /* 0x0324 */
+ u32 pad07[54];
+ u32 rsttime_reg; /* 0x0400 */
+ u32 pad08[6];
+ u32 c2crstctrl; /* 0x041c */
+ u32 extpwronrstctrl; /* 0x0420 */
+ u32 pad09[59];
+ u32 extwarmrstst_reg; /* 0x0510 */
+ u32 apewarmrstst_reg; /* 0x0514 */
+ u32 pad10[1];
+ u32 c2cwarmrstst_reg; /* 0x051C */
+};
+#endif /* _CLOCKS_OMAP4_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _CLOCKS_OMAP4_H_
-#define _CLOCKS_OMAP4_H_
-#include <common.h>
-#include <asm/omap_common.h>
-
-/*
- * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
- * loop, allow for a minimum of 2 ms wait (in reality the wait will be
- * much more than that)
- */
-#define LDELAY 1000000
-
-/* CM_DLL_CTRL */
-#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
-#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
-#define CM_DLL_CTRL_NO_OVERRIDE 0
-
-/* CM_CLKMODE_DPLL */
-#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
-#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
-#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
-#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
-#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
-#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
-#define CM_CLKMODE_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
-
-#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
-
-#define DPLL_EN_STOP 1
-#define DPLL_EN_MN_BYPASS 4
-#define DPLL_EN_LOW_POWER_BYPASS 5
-#define DPLL_EN_FAST_RELOCK_BYPASS 6
-#define DPLL_EN_LOCK 7
-
-/* CM_IDLEST_DPLL fields */
-#define ST_DPLL_CLK_MASK 1
-
-/* CM_CLKSEL_DPLL */
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
-#define CM_CLKSEL_DPLL_M_SHIFT 8
-#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
-#define CM_CLKSEL_DPLL_N_SHIFT 0
-#define CM_CLKSEL_DPLL_N_MASK 0x7F
-#define CM_CLKSEL_DCC_EN_SHIFT 22
-#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-
-/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
-
-/* CM_CLKSEL_CORE */
-#define CLKSEL_CORE_SHIFT 0
-#define CLKSEL_L3_SHIFT 4
-#define CLKSEL_L4_SHIFT 8
-
-#define CLKSEL_CORE_X2_DIV_1 0
-#define CLKSEL_L3_CORE_DIV_2 1
-#define CLKSEL_L4_L3_DIV_2 1
-
-/* CM_ABE_PLL_REF_CLKSEL */
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
-
-/* CM_BYPCLK_DPLL_IVA */
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
-
-#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
-
-/* CM_SHADOW_FREQ_CONFIG1 */
-#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
-#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
-#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
-
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
-
-#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
-#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
-
-/*CM_<clock_domain>__CLKCTRL */
-#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
-#define CD_CLKCTRL_CLKTRCTRL_MASK 3
-
-#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
-#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
-#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
-#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
-
-
-/* CM_<clock_domain>_<module>_CLKCTRL */
-#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
-#define MODULE_CLKCTRL_MODULEMODE_MASK 3
-#define MODULE_CLKCTRL_IDLEST_SHIFT 16
-#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
-
-#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
-#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
-#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
-
-#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
-#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
-#define MODULE_CLKCTRL_IDLEST_IDLE 2
-#define MODULE_CLKCTRL_IDLEST_DISABLED 3
-
-/* CM_L4PER_GPIO4_CLKCTRL */
-#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_L3INIT_HSMMCn_CLKCTRL */
-#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
-
-/* CM_WKUP_GPTIMER1_CLKCTRL */
-#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
-
-/* CM_CAM_ISS_CLKCTRL */
-#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_DSS_DSS_CLKCTRL */
-#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
-
-/* CM_L3INIT_USBPHY_CLKCTRL */
-#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
-
-/* CM_MPU_MPU_CLKCTRL */
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
-
-/* Clock frequencies */
-#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-
-/* PRM_VC_VAL_BYPASS */
-#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
-
-/* SMPS */
-#define SMPS_I2C_SLAVE_ADDR 0x12
-#define SMPS_REG_ADDR_VCORE1 0x55
-#define SMPS_REG_ADDR_VCORE2 0x5B
-#define SMPS_REG_ADDR_VCORE3 0x61
-
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
-
-/* TPS */
-#define TPS62361_I2C_SLAVE_ADDR 0x60
-#define TPS62361_REG_ADDR_SET0 0x0
-#define TPS62361_REG_ADDR_SET1 0x1
-#define TPS62361_REG_ADDR_SET2 0x2
-#define TPS62361_REG_ADDR_SET3 0x3
-#define TPS62361_REG_ADDR_CTRL 0x4
-#define TPS62361_REG_ADDR_TEMP 0x5
-#define TPS62361_REG_ADDR_RMP_CTRL 0x6
-#define TPS62361_REG_ADDR_CHIP_ID 0x8
-#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
-
-#define TPS62361_BASE_VOLT_MV 500
-#define TPS62361_VSEL0_GPIO 7
-
-/* AUXCLKx reg fields */
-#define AUXCLK_ENABLE_MASK (1 << 8)
-#define AUXCLK_SRCSELECT_SHIFT 1
-#define AUXCLK_SRCSELECT_MASK (3 << 1)
-#define AUXCLK_CLKDIV_SHIFT 16
-#define AUXCLK_CLKDIV_MASK (0xF << 16)
-
-#define AUXCLK_SRCSELECT_SYS_CLK 0
-#define AUXCLK_SRCSELECT_CORE_DPLL 1
-#define AUXCLK_SRCSELECT_PER_DPLL 2
-#define AUXCLK_SRCSELECT_ALTERNATE 3
-
-#define AUXCLK_CLKDIV_2 1
-#define AUXCLK_CLKDIV_16 0xF
-
-/* ALTCLKSRC */
-#define ALTCLKSRC_MODE_MASK 3
-#define ALTCLKSRC_ENABLE_INT_MASK 4
-#define ALTCLKSRC_ENABLE_EXT_MASK 8
-
-#define ALTCLKSRC_MODE_ACTIVE 1
-
-#define DPLL_NO_LOCK 0
-#define DPLL_LOCK 1
-
-struct omap4_scrm_regs {
- u32 revision; /* 0x0000 */
- u32 pad00[63];
- u32 clksetuptime; /* 0x0100 */
- u32 pmicsetuptime; /* 0x0104 */
- u32 pad01[2];
- u32 altclksrc; /* 0x0110 */
- u32 pad02[2];
- u32 c2cclkm; /* 0x011c */
- u32 pad03[56];
- u32 extclkreq; /* 0x0200 */
- u32 accclkreq; /* 0x0204 */
- u32 pwrreq; /* 0x0208 */
- u32 pad04[1];
- u32 auxclkreq0; /* 0x0210 */
- u32 auxclkreq1; /* 0x0214 */
- u32 auxclkreq2; /* 0x0218 */
- u32 auxclkreq3; /* 0x021c */
- u32 auxclkreq4; /* 0x0220 */
- u32 auxclkreq5; /* 0x0224 */
- u32 pad05[3];
- u32 c2cclkreq; /* 0x0234 */
- u32 pad06[54];
- u32 auxclk0; /* 0x0310 */
- u32 auxclk1; /* 0x0314 */
- u32 auxclk2; /* 0x0318 */
- u32 auxclk3; /* 0x031c */
- u32 auxclk4; /* 0x0320 */
- u32 auxclk5; /* 0x0324 */
- u32 pad07[54];
- u32 rsttime_reg; /* 0x0400 */
- u32 pad08[6];
- u32 c2crstctrl; /* 0x041c */
- u32 extpwronrstctrl; /* 0x0420 */
- u32 pad09[59];
- u32 extwarmrstst_reg; /* 0x0510 */
- u32 apewarmrstst_reg; /* 0x0514 */
- u32 pad10[1];
- u32 c2cwarmrstst_reg; /* 0x051C */
-};
-#endif /* _CLOCKS_OMAP4_H_ */
#define _SYS_PROTO_H_
#include <asm/arch/omap.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include <asm/arch/mux_omap4.h>
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY 1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
+#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE 0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* SGX */
+#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
+#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
+
+/* CM_WKUPAON_SCRM_CLKCTRL */
+#define OPTFCLKEN_SCRM_PER_SHIFT 9
+#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
+#define OPTFCLKEN_SCRM_CORE_SHIFT 8
+#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT 0
+#define RSTTIME1_MASK (0x3ff << 0)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR 0x12
+#define SMPS_REG_ADDR_12_MPU 0x23
+#define SMPS_REG_ADDR_45_IVA 0x2B
+#define SMPS_REG_ADDR_8_CORE 0x37
+
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+/* ES1.0 settings */
+#define VDD_MPU 1040
+#define VDD_MM 1040
+#define VDD_CORE 1040
+
+#define VDD_MPU_LOW 890
+#define VDD_MM_LOW 890
+#define VDD_CORE_LOW 890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2 1060
+#define VDD_MM_ES2 1025
+#define VDD_CORE_ES2 1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD 1120
+
+#define VDD_MPU_ES2_LOW 880
+#define VDD_MM_ES2_LOW 880
+
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR 0x60
+#define TPS62361_REG_ADDR_SET0 0x0
+#define TPS62361_REG_ADDR_SET1 0x1
+#define TPS62361_REG_ADDR_SET2 0x2
+#define TPS62361_REG_ADDR_SET3 0x3
+#define TPS62361_REG_ADDR_CTRL 0x4
+#define TPS62361_REG_ADDR_TEMP 0x5
+#define TPS62361_REG_ADDR_RMP_CTRL 0x6
+#define TPS62361_REG_ADDR_CHIP_ID 0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
+
+#define TPS62361_BASE_VOLT_MV 500
+#define TPS62361_VSEL0_GPIO 7
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
+#endif /* _CLOCKS_OMAP5_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _CLOCKS_OMAP5_H_
-#define _CLOCKS_OMAP5_H_
-#include <common.h>
-#include <asm/omap_common.h>
-
-/*
- * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
- * loop, allow for a minimum of 2 ms wait (in reality the wait will be
- * much more than that)
- */
-#define LDELAY 1000000
-
-/* CM_DLL_CTRL */
-#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
-#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
-#define CM_DLL_CTRL_NO_OVERRIDE 0
-
-/* CM_CLKMODE_DPLL */
-#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
-#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
-#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
-#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
-#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
-#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
-#define CM_CLKMODE_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
-
-#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
-
-#define DPLL_EN_STOP 1
-#define DPLL_EN_MN_BYPASS 4
-#define DPLL_EN_LOW_POWER_BYPASS 5
-#define DPLL_EN_FAST_RELOCK_BYPASS 6
-#define DPLL_EN_LOCK 7
-
-/* CM_IDLEST_DPLL fields */
-#define ST_DPLL_CLK_MASK 1
-
-/* SGX */
-#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
-#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
-
-/* CM_CLKSEL_DPLL */
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
-#define CM_CLKSEL_DPLL_M_SHIFT 8
-#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
-#define CM_CLKSEL_DPLL_N_SHIFT 0
-#define CM_CLKSEL_DPLL_N_MASK 0x7F
-#define CM_CLKSEL_DCC_EN_SHIFT 22
-#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-
-/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
-
-/* CM_CLKSEL_CORE */
-#define CLKSEL_CORE_SHIFT 0
-#define CLKSEL_L3_SHIFT 4
-#define CLKSEL_L4_SHIFT 8
-
-#define CLKSEL_CORE_X2_DIV_1 0
-#define CLKSEL_L3_CORE_DIV_2 1
-#define CLKSEL_L4_L3_DIV_2 1
-
-/* CM_ABE_PLL_REF_CLKSEL */
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
-
-/* CM_BYPCLK_DPLL_IVA */
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
-
-#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
-
-/* CM_SHADOW_FREQ_CONFIG1 */
-#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
-#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
-#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
-
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
-
-#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
-#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
-
-/*CM_<clock_domain>__CLKCTRL */
-#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
-#define CD_CLKCTRL_CLKTRCTRL_MASK 3
-
-#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
-#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
-#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
-#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
-
-
-/* CM_<clock_domain>_<module>_CLKCTRL */
-#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
-#define MODULE_CLKCTRL_MODULEMODE_MASK 3
-#define MODULE_CLKCTRL_IDLEST_SHIFT 16
-#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
-
-#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
-#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
-#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
-
-#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
-#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
-#define MODULE_CLKCTRL_IDLEST_IDLE 2
-#define MODULE_CLKCTRL_IDLEST_DISABLED 3
-
-/* CM_L4PER_GPIO4_CLKCTRL */
-#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_L3INIT_HSMMCn_CLKCTRL */
-#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
-
-/* CM_WKUP_GPTIMER1_CLKCTRL */
-#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
-
-/* CM_CAM_ISS_CLKCTRL */
-#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_DSS_DSS_CLKCTRL */
-#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
-
-/* CM_L3INIT_USBPHY_CLKCTRL */
-#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
-
-/* CM_MPU_MPU_CLKCTRL */
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
-
-/* CM_WKUPAON_SCRM_CLKCTRL */
-#define OPTFCLKEN_SCRM_PER_SHIFT 9
-#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
-#define OPTFCLKEN_SCRM_CORE_SHIFT 8
-#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
-
-/* CM_COREAON_IO_SRCOMP_CLKCTRL */
-#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
-#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
-
-/* PRM_RSTTIME */
-#define RSTTIME1_SHIFT 0
-#define RSTTIME1_MASK (0x3ff << 0)
-
-/* Clock frequencies */
-#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-
-/* PRM_VC_VAL_BYPASS */
-#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
-
-/* SMPS */
-#define SMPS_I2C_SLAVE_ADDR 0x12
-#define SMPS_REG_ADDR_12_MPU 0x23
-#define SMPS_REG_ADDR_45_IVA 0x2B
-#define SMPS_REG_ADDR_8_CORE 0x37
-
-/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
-/* ES1.0 settings */
-#define VDD_MPU 1040
-#define VDD_MM 1040
-#define VDD_CORE 1040
-
-#define VDD_MPU_LOW 890
-#define VDD_MM_LOW 890
-#define VDD_CORE_LOW 890
-
-/* ES2.0 settings */
-#define VDD_MPU_ES2 1060
-#define VDD_MM_ES2 1025
-#define VDD_CORE_ES2 1040
-
-#define VDD_MPU_ES2_HIGH 1250
-#define VDD_MM_ES2_OD 1120
-
-#define VDD_MPU_ES2_LOW 880
-#define VDD_MM_ES2_LOW 880
-
-/* Standard offset is 0.5v expressed in uv */
-#define PALMAS_SMPS_BASE_VOLT_UV 500000
-
-/* TPS */
-#define TPS62361_I2C_SLAVE_ADDR 0x60
-#define TPS62361_REG_ADDR_SET0 0x0
-#define TPS62361_REG_ADDR_SET1 0x1
-#define TPS62361_REG_ADDR_SET2 0x2
-#define TPS62361_REG_ADDR_SET3 0x3
-#define TPS62361_REG_ADDR_CTRL 0x4
-#define TPS62361_REG_ADDR_TEMP 0x5
-#define TPS62361_REG_ADDR_RMP_CTRL 0x6
-#define TPS62361_REG_ADDR_CHIP_ID 0x8
-#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
-
-#define TPS62361_BASE_VOLT_MV 500
-#define TPS62361_VSEL0_GPIO 7
-
-#define DPLL_NO_LOCK 0
-#define DPLL_LOCK 1
-
-/*
- * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
- * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
- * into microsec and passing the value.
- */
-#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#endif /* _CLOCKS_OMAP5_H_ */
#include <asm/arch/omap.h>
#include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include "errno.h"
#include <i2c.h>
#ifdef CONFIG_USB_EHCI
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
#include <version.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
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