S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/mach-at91/
-F: arch/arm/include/asm/arch-at91/
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_COMMON_H
-#define AT91_COMMON_H
-
-void at91_can_hw_init(void);
-void at91_gmac_hw_init(void);
-void at91_macb_hw_init(void);
-void at91_mci_hw_init(void);
-void at91_serial0_hw_init(void);
-void at91_serial1_hw_init(void);
-void at91_serial2_hw_init(void);
-void at91_seriald_hw_init(void);
-void at91_spi0_hw_init(unsigned long cs_mask);
-void at91_spi1_hw_init(unsigned long cs_mask);
-void at91_udp_hw_init(void);
-void at91_uhp_hw_init(void);
-void at91_lcd_hw_init(void);
-void at91_plla_init(u32 pllar);
-void at91_pllb_init(u32 pllar);
-void at91_mck_init(u32 mckr);
-void at91_pmc_init(void);
-void mem_init(void);
-void at91_phy_reset(void);
-void at91_sdram_hw_init(void);
-void at91_mck_init(u32 mckr);
-void at91_spl_board_init(void);
-void at91_disable_wdt(void);
-void matrix_init(void);
-void redirect_int_from_saic_to_aic(void);
-
-#endif /* AT91_COMMON_H */
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Debug Unit
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_DBU_H
-#define AT91_DBU_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_dbu {
- u32 cr; /* Control Register WO */
- u32 mr; /* Mode Register RW */
- u32 ier; /* Interrupt Enable Register WO */
- u32 idr; /* Interrupt Disable Register WO */
- u32 imr; /* Interrupt Mask Register RO */
- u32 sr; /* Status Register RO */
- u32 rhr; /* Receive Holding Register RO */
- u32 thr; /* Transmit Holding Register WO */
- u32 brgr; /* Baud Rate Generator Register RW */
- u32 res1[7];/* 0x0024 - 0x003C Reserved */
- u32 cidr; /* Chip ID Register RO */
- u32 exid; /* Chip ID Extension Register RO */
- u32 fnr; /* Force NTRST Register RW */
-} at91_dbu_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_DBU_CID_ARCH_MASK 0x0ff00000
-#define AT91_DBU_CID_ARCH_9xx 0x01900000
-#define AT91_DBU_CID_ARCH_9XExx 0x02900000
-
-#define AT91_DBU_CIDR_MASK 0x1f
-#define AT91_DBU_CIDR 0x40
-#define AT91_DBU_EXID 0x44
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Enhanced Embedded Flash Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_EEFC_H
-#define AT91_EEFC_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_eefc {
- u32 fmr; /* Flash Mode Register RW */
- u32 fcr; /* Flash Command Register WO */
- u32 fsr; /* Flash Status Register RO */
- u32 frr; /* Flash Result Register RO */
-} at91_eefc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_EEFC_FMR_FWS_MASK 0x00000f00
-#define AT91_EEFC_FMR_FRDY_BIT 0x00000001
-
-#define AT91_EEFC_FCR_KEY 0x5a000000
-#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00
-#define AT91_EEFC_FCR_FARG_SHIFT 8
-#define AT91_EEFC_FCR_FCMD_GETD 0x0
-#define AT91_EEFC_FCR_FCMD_WP 0x1
-#define AT91_EEFC_FCR_FCMD_WPL 0x2
-#define AT91_EEFC_FCR_FCMD_EWP 0x3
-#define AT91_EEFC_FCR_FCMD_EWPL 0x4
-#define AT91_EEFC_FCR_FCMD_EA 0x5
-#define AT91_EEFC_FCR_FCMD_SLB 0x8
-#define AT91_EEFC_FCR_FCMD_CLB 0x9
-#define AT91_EEFC_FCR_FCMD_GLB 0xA
-#define AT91_EEFC_FCR_FCMD_SGPB 0xB
-#define AT91_EEFC_FCR_FCMD_CGPB 0xC
-#define AT91_EEFC_FCR_FCMD_GGPB 0xD
-
-#define AT91_EEFC_FSR_FRDY 1
-#define AT91_EEFC_FSR_FCMDE 2
-#define AT91_EEFC_FSR_FLOCKE 4
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_H
-#define AT91_H
-
-typedef struct at91_emac {
- u32 ctl;
- u32 cfg;
- u32 sr;
- u32 tar;
- u32 tcr;
- u32 tsr;
- u32 rbqp;
- u32 reserved0;
- u32 rsr;
- u32 isr;
- u32 ier;
- u32 idr;
- u32 imr;
- u32 man;
- u32 reserved1[2];
- u32 fra;
- u32 scol;
- u32 mocl;
- u32 ok;
- u32 seqe;
- u32 ale;
- u32 dte;
- u32 lcol;
- u32 ecol;
- u32 cse;
- u32 tue;
- u32 cde;
- u32 elr;
- u32 rjb;
- u32 usf;
- u32 sqee;
- u32 drfc;
- u32 reserved2[3];
- u32 hsh;
- u32 hsl;
- u32 sa1l;
- u32 sa1h;
- u32 sa2l;
- u32 sa2h;
- u32 sa3l;
- u32 sa3h;
- u32 sa4l;
- u32 sa4h;
-} at91_emac_t;
-
-#define AT91_EMAC_CTL_LB 0x0001
-#define AT91_EMAC_CTL_LBL 0x0002
-#define AT91_EMAC_CTL_RE 0x0004
-#define AT91_EMAC_CTL_TE 0x0008
-#define AT91_EMAC_CTL_MPE 0x0010
-#define AT91_EMAC_CTL_CSR 0x0020
-#define AT91_EMAC_CTL_ISR 0x0040
-#define AT91_EMAC_CTL_WES 0x0080
-#define AT91_EMAC_CTL_BP 0x1000
-
-#define AT91_EMAC_CFG_SPD 0x0001
-#define AT91_EMAC_CFG_FD 0x0002
-#define AT91_EMAC_CFG_BR 0x0004
-#define AT91_EMAC_CFG_CAF 0x0010
-#define AT91_EMAC_CFG_NBC 0x0020
-#define AT91_EMAC_CFG_MTI 0x0040
-#define AT91_EMAC_CFG_UNI 0x0080
-#define AT91_EMAC_CFG_BIG 0x0100
-#define AT91_EMAC_CFG_EAE 0x0200
-#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF
-#define AT91_EMAC_CFG_MCLK_8 0x0000
-#define AT91_EMAC_CFG_MCLK_16 0x0400
-#define AT91_EMAC_CFG_MCLK_32 0x0800
-#define AT91_EMAC_CFG_MCLK_64 0x0C00
-#define AT91_EMAC_CFG_RTY 0x1000
-#define AT91_EMAC_CFG_RMII 0x2000
-
-#define AT91_EMAC_SR_LINK 0x0001
-#define AT91_EMAC_SR_MDIO 0x0002
-#define AT91_EMAC_SR_IDLE 0x0004
-
-#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF)
-#define AT91_EMAC_TCR_NCRC 0x8000
-
-#define AT91_EMAC_TSR_OVR 0x0001
-#define AT91_EMAC_TSR_COL 0x0002
-#define AT91_EMAC_TSR_RLE 0x0004
-#define AT91_EMAC_TSR_TXIDLE 0x0008
-#define AT91_EMAC_TSR_BNQ 0x0010
-#define AT91_EMAC_TSR_COMP 0x0020
-#define AT91_EMAC_TSR_UND 0x0040
-
-#define AT91_EMAC_RSR_BNA 0x0001
-#define AT91_EMAC_RSR_REC 0x0002
-#define AT91_EMAC_RSR_OVR 0x0004
-
-/* ISR, IER, IDR, IMR use the same bits */
-#define AT91_EMAC_IxR_DONE 0x0001
-#define AT91_EMAC_IxR_RCOM 0x0002
-#define AT91_EMAC_IxR_RBNA 0x0004
-#define AT91_EMAC_IxR_TOVR 0x0008
-#define AT91_EMAC_IxR_TUND 0x0010
-#define AT91_EMAC_IxR_RTRY 0x0020
-#define AT91_EMAC_IxR_TBRE 0x0040
-#define AT91_EMAC_IxR_TCOM 0x0080
-#define AT91_EMAC_IxR_TIDLE 0x0100
-#define AT91_EMAC_IxR_LINK 0x0200
-#define AT91_EMAC_IxR_ROVR 0x0400
-#define AT91_EMAC_IxR_HRESP 0x0800
-
-#define AT91_EMAC_MAN_DATA_MASK 0xFFFF
-#define AT91_EMAC_MAN_CODE_802_3 0x00020000
-#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18)
-#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23)
-#define AT91_EMAC_MAN_RW_R 0x20000000
-#define AT91_EMAC_MAN_RW_W 0x10000000
-#define AT91_EMAC_MAN_HIGH 0x40000000
-#define AT91_EMAC_MAN_LOW 0x80000000
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * General Purpose Backup Registers
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_GPBR_H
-#define AT91_GPBR_H
-
-/*
- * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
- * 32 Bit registers (buffered by the Vbu power).
- *
- * Please consider carefully before using this resource for tasks
- * that do not really need nonvolatile registers. Maybe you can
- * store information in EEPROM or FLASH instead.
- *
- * However, if you use a GPBR please document its use here and
- * reference the define in your code!
- *
- * known typical uses of the GPBRs:
- * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
- * GPBR[1]: unused
- * GPBR[2]: unused
- * GPBR[3]: bootcount (u-boot)
- */
-#define AT91_GPBR_INDEX_TIMEOFF 0
-#define AT91_GPBR_INDEX_BOOTCOUNT 3
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_gpbr {
- u32 reg[4];
-} at91_gpbr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_MATRIX_H
-#define AT91_MATRIX_H
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
-#else
-#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
-#endif
-
-#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
-
-#else
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_MATRIX_MASTERS 6
-#define AT91_MATRIX_SLAVES 5
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_MATRIX_MASTERS 1
-#define AT91_MATRIX_SLAVES 5
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_MASTERS 9
-#define AT91_MATRIX_SLAVES 7
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MASTERS 11
-#define AT91_MATRIX_SLAVES 8
-#else
-#error CPU not supported. Please update at91_matrix.h
-#endif
-
-typedef struct at91_priority {
- u32 a;
- u32 b;
-} at91_priority_t;
-
-typedef struct at91_matrix {
- u32 mcfg[AT91_MATRIX_MASTERS];
-#if defined(CONFIG_AT91SAM9261)
- u32 scfg[AT91_MATRIX_SLAVES];
- u32 res61_1[3];
- u32 tcr;
- u32 res61_2[2];
- u32 csa;
- u32 pucr;
- u32 res61_3[114];
-#else
- u32 reserve1[16 - AT91_MATRIX_MASTERS];
- u32 scfg[AT91_MATRIX_SLAVES];
- u32 reserve2[16 - AT91_MATRIX_SLAVES];
- at91_priority_t pr[AT91_MATRIX_SLAVES];
- u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
- u32 mrcr; /* 0x100 Master Remap Control */
- u32 reserve4[3];
-#if defined(CONFIG_AT91SAM9G45)
- u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
- u32 womr; /* 0x1E4 Write Protect Mode */
- u32 wpsr; /* 0x1E8 Write Protect Status */
- u32 resg45_1[10];
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
- u32 res60_1[3];
- u32 csa;
- u32 res60_2[56];
-#elif defined(CONFIG_AT91SAM9263)
- u32 res63_1;
- u32 tcmr;
- u32 res63_2[2];
- u32 csa[2];
- u32 res63_3[54];
-#else
- u32 reserve5[60];
-#endif
-#endif
-} at91_matrix_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_CSA_DBPUC 0x00000100
-#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
-#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
-
-#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
-#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
-#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
-#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
-
-#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
-
-#if defined CONFIG_AT91SAM9261
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_MCFG_RCB0 (1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_MCFG_RCB1 (1 << 1)
-#endif
-
-/* Undefined Length Burst Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
- defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
-#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
-#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
-#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
-#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
-#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
-#define AT91_MATRIX_MCFG_ULBT_128 0x00000007
-#endif
-
-/* Default Master Type */
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
-
-/* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
-#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
-#endif
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
- defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
-#endif
-
-/* Arbitration Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
-#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
-#endif
-
-/* Master Remap Control Register */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
- defined(CONFIG_AT91SAM9G45)
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_MRCR_RCB0 (1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_MRCR_RCB1 (1 << 1)
-#endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MRCR_RCB2 0x00000004
-#define AT91_MATRIX_MRCR_RCB3 0x00000008
-#define AT91_MATRIX_MRCR_RCB4 0x00000010
-#define AT91_MATRIX_MRCR_RCB5 0x00000020
-#define AT91_MATRIX_MRCR_RCB6 0x00000040
-#define AT91_MATRIX_MRCR_RCB7 0x00000080
-#define AT91_MATRIX_MRCR_RCB8 0x00000100
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MRCR_RCB9 0x00000200
-#define AT91_MATRIX_MRCR_RCB10 0x00000400
-#define AT91_MATRIX_MRCR_RCB11 0x00000800
-#endif
-
-/* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
-/* Size of ITCM enabled memory block */
-#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
-#define AT91_MATRIX_TCMR_ITCM_32 0x00000040
-/* Size of DTCM enabled memory block */
-#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
-#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
-#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
-/* Wait state TCM register */
-#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
-#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
-#endif
-#if defined(CONFIG_AT91SAM9263)
-/* Size of ITCM enabled memory block */
-#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
-#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
-#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
-/* Size of DTCM enabled memory block */
-#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
-#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
-#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
-#endif
-#if defined(CONFIG_AT91SAM9261)
-/* Size of ITCM enabled memory block */
-#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
-#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
-#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
-#define AT91_MATRIX_TCMR_ITCM_64 0x00000007
-/* Size of DTCM enabled memory block */
-#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
-#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
-#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
-#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
-#endif
-
-#if defined(CONFIG_AT91SAM9G45)
-/* Video Mode Configuration Register */
-#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
-#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
-/* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
-#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
-#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
-/* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_NO_WPV 0x00000000
-#define AT91_MATRIX_WPSR_WPV 0x00000001
-#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
-#endif
-
-/* USB Pad Pull-Up Control Register */
-#if defined(CONFIG_AT91SAM9261)
-#define AT91_MATRIX_USBPUCR_PUON 0x40000000
-#endif
-
-#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
-#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_MC_H
-#define AT91_MC_H
-
-#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60)
-#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64)
-#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_ebi {
- u32 csa; /* 0x00 Chip Select Assignment Register */
- u32 cfgr; /* 0x04 Configuration Register */
- u32 reserved[2];
-} at91_ebi_t;
-
-#define AT91_EBI_CSA_CS0A 0x0001
-#define AT91_EBI_CSA_CS1A 0x0002
-
-#define AT91_EBI_CSA_CS3A 0x0008
-#define AT91_EBI_CSA_CS4A 0x0010
-
-typedef struct at91_sdramc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
- u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
- u32 cr; /* 0x08 SDRAMC Configuration Register */
- u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
- u32 lpr; /* 0x10 SDRAMC Low Power Register */
- u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
- u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
- u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
- u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
- u32 reserved[3];
-} at91_sdramc_t;
-
-typedef struct at91_smc {
- u32 csr[8]; /* 0x00 SDRAMC Mode Register */
-} at91_smc_t;
-
-#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
-#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
-#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
-#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
-#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
-#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
-#define AT91_SMC_CSR_DRP 0x00008000
-#define AT91_SMC_CSR_DBW_8 0x00004000
-#define AT91_SMC_CSR_DBW_16 0x00002000
-#define AT91_SMC_CSR_BAT_8 0x00000000
-#define AT91_SMC_CSR_BAT_16 0x00001000
-#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
-#define AT91_SMC_CSR_WSEN 0x00000080
-#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
-
-typedef struct at91_bfc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
-} at91_bfc_t;
-
-typedef struct at91_mc {
- u32 rcr; /* 0x00 MC Remap Control Register */
- u32 asr; /* 0x04 MC Abort Status Register */
- u32 aasr; /* 0x08 MC Abort Address Status Reg */
- u32 mpr; /* 0x0C MC Master Priority Register */
- u32 reserved1[20]; /* 0x10-0x5C */
- at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
- at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
- at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
- at91_bfc_t bfc; /* 0xC0 BFC User Interface */
- u32 reserved2[15];
-} at91_mc_t;
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_PDC_H
-#define AT91_PDC_H
-
-typedef struct at91_pdc {
- u32 rpr; /* 0x100 Receive Pointer Register */
- u32 rcr; /* 0x104 Receive Counter Register */
- u32 tpr; /* 0x108 Transmit Pointer Register */
- u32 tcr; /* 0x10C Transmit Counter Register */
- u32 pnpr; /* 0x110 Receive Next Pointer Register */
- u32 pncr; /* 0x114 Receive Next Counter Register */
- u32 tnpr; /* 0x118 Transmit Next Pointer Register */
- u32 tncr; /* 0x11C Transmit Next Counter Register */
- u32 ptcr; /* 0x120 Transfer Control Register */
- u32 ptsr; /* 0x124 Transfer Status Register */
-} at91_pdc_t;
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-
-#define AT91_ASM_PIO_RANGE 0x200
-#define AT91_ASM_PIOC_ASR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
-#define AT91_ASM_PIOC_BSR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
-#define AT91_ASM_PIOC_PDR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOC_PUDR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
-
-#define AT91_ASM_PIOD_PDR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOD_PUDR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
-#define AT91_ASM_PIOD_ASR \
- (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_port {
- u32 per; /* 0x00 PIO Enable Register */
- u32 pdr; /* 0x04 PIO Disable Register */
- u32 psr; /* 0x08 PIO Status Register */
- u32 reserved0;
- u32 oer; /* 0x10 Output Enable Register */
- u32 odr; /* 0x14 Output Disable Registerr */
- u32 osr; /* 0x18 Output Status Register */
- u32 reserved1;
- u32 ifer; /* 0x20 Input Filter Enable Register */
- u32 ifdr; /* 0x24 Input Filter Disable Register */
- u32 ifsr; /* 0x28 Input Filter Status Register */
- u32 reserved2;
- u32 sodr; /* 0x30 Set Output Data Register */
- u32 codr; /* 0x34 Clear Output Data Register */
- u32 odsr; /* 0x38 Output Data Status Register */
- u32 pdsr; /* 0x3C Pin Data Status Register */
- u32 ier; /* 0x40 Interrupt Enable Register */
- u32 idr; /* 0x44 Interrupt Disable Register */
- u32 imr; /* 0x48 Interrupt Mask Register */
- u32 isr; /* 0x4C Interrupt Status Register */
- u32 mder; /* 0x50 Multi-driver Enable Register */
- u32 mddr; /* 0x54 Multi-driver Disable Register */
- u32 mdsr; /* 0x58 Multi-driver Status Register */
- u32 reserved3;
- u32 pudr; /* 0x60 Pull-up Disable Register */
- u32 puer; /* 0x64 Pull-up Enable Register */
- u32 pusr; /* 0x68 Pad Pull-up Status Register */
- u32 reserved4;
-#if defined(CPU_HAS_PIO3)
- u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
- u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
- u32 reserved5[2];
- u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
- u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
- u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
- u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
- u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
- u32 ppder; /* 0x94 Pad Pull-down Enable Register */
- u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
- u32 reserved6; /* */
-#else
- u32 asr; /* 0x70 Select A Register */
- u32 bsr; /* 0x74 Select B Register */
- u32 absr; /* 0x78 AB Select Status Register */
- u32 reserved5[9]; /* */
-#endif
- u32 ower; /* 0xA0 Output Write Enable Register */
- u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 Output Write Status Register */
-#if defined(CPU_HAS_PIO3)
- u32 reserved7; /* */
- u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
- u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
- u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
- u32 reserved8; /* */
- u32 esr; /* 0xC0 Edge Select Register */
- u32 lsr; /* 0xC4 Level Select Register */
- u32 elsr; /* 0xC8 Edge/Level Status Register */
- u32 reserved9; /* 0xCC */
- u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
- u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
- u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
- u32 reserved10; /* */
- u32 locksr; /* 0xE0 Lock Status */
- u32 wpmr; /* 0xE4 Write Protect Mode Register */
- u32 wpsr; /* 0xE8 Write Protect Status Register */
- u32 reserved11[5]; /* */
- u32 schmitt; /* 0x100 Schmitt Trigger Register */
- u32 reserved12[63];
-#else
- u32 reserved6[85];
-#endif
-} at91_port_t;
-
-typedef union at91_pio {
- struct {
- at91_port_t pioa;
- at91_port_t piob;
- at91_port_t pioc;
- at91_port_t piod; /* not present in all hardware */
- at91_port_t pioe;/* not present in all hardware */
- };
- at91_port_t port[5];
-} at91_pio_t;
-
-#ifdef CONFIG_AT91_GPIO
-int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
-#if defined(CPU_HAS_PIO3)
-int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
-int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
-#endif
-int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_output(unsigned port, unsigned pin, int value);
-int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_value(unsigned port, unsigned pin, int value);
-int at91_get_pio_value(unsigned port, unsigned pin);
-#endif
-#endif
-
-#define AT91_PIO_PORTA 0x0
-#define AT91_PIO_PORTB 0x1
-#define AT91_PIO_PORTC 0x2
-#define AT91_PIO_PORTD 0x3
-#define AT91_PIO_PORTE 0x4
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-
-typedef struct at91_pit {
- u32 mr; /* 0x00 Mode Register */
- u32 sr; /* 0x04 Status Register */
- u32 pivr; /* 0x08 Periodic Interval Value Register */
- u32 piir; /* 0x0C Periodic Interval Image Register */
-} at91_pit_t;
-
-#define AT91_PIT_MR_IEN 0x02000000
-#define AT91_PIT_MR_EN 0x01000000
-#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
-#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#ifdef __ASSEMBLY__
-
-#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
-#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
-#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
-#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
-#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
-
-#else
-
-#include <asm/types.h>
-
-typedef struct at91_pmc {
- u32 scer; /* 0x00 System Clock Enable Register */
- u32 scdr; /* 0x04 System Clock Disable Register */
- u32 scsr; /* 0x08 System Clock Status Register */
- u32 reserved0;
- u32 pcer; /* 0x10 Peripheral Clock Enable Register */
- u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
- u32 pcsr; /* 0x18 Peripheral Clock Status Register */
- u32 uckr; /* 0x1C UTMI Clock Register */
- u32 mor; /* 0x20 Main Oscilator Register */
- u32 mcfr; /* 0x24 Main Clock Frequency Register */
- u32 pllar; /* 0x28 PLL A Register */
- u32 pllbr; /* 0x2C PLL B Register */
- u32 mckr; /* 0x30 Master Clock Register */
- u32 reserved1;
- u32 usb; /* 0x38 USB Clock Register */
- u32 reserved2;
- u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
- u32 reserved3[4];
- u32 ier; /* 0x60 Interrupt Enable Register */
- u32 idr; /* 0x64 Interrupt Disable Register */
- u32 sr; /* 0x68 Status Register */
- u32 imr; /* 0x6C Interrupt Mask Register */
- u32 reserved4[4];
- u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
- u32 reserved5[21];
- u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
- u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CPU_HAS_PCR
- u32 reserved6[8];
- u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
- u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
- u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
- u32 pcr; /* 0x10c Periperial Control Register */
- u32 ocr; /* 0x110 Oscillator Calibration Register */
-#else
- u32 reserved8[5];
-#endif
-} at91_pmc_t;
-
-#endif /* end not assembly */
-
-#define AT91_PMC_MOR_MOSCEN 0x01
-#define AT91_PMC_MOR_OSCBYPASS 0x02
-#define AT91_PMC_MOR_MOSCRCEN 0x08
-#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8)
-#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16)
-#define AT91_PMC_MOR_MOSCSEL (1 << 24)
-
-#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
-#else
-#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
-#endif
-#define AT91_PMC_PLLAR_29 0x20000000
-#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
-#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
-#define AT91_PMC_PLLBR_USBDIV_4 0x20000000
-
-#define AT91_PMC_MCFR_MAINRDY 0x00010000
-#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
-
-#define AT91_PMC_MCKR_CSS_SLOW 0x00000000
-#define AT91_PMC_MCKR_CSS_MAIN 0x00000001
-#define AT91_PMC_MCKR_CSS_PLLA 0x00000002
-#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
-#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_MCKR_PRES_1 0x00000000
-#define AT91_PMC_MCKR_PRES_2 0x00000010
-#define AT91_PMC_MCKR_PRES_4 0x00000020
-#define AT91_PMC_MCKR_PRES_8 0x00000030
-#define AT91_PMC_MCKR_PRES_16 0x00000040
-#define AT91_PMC_MCKR_PRES_32 0x00000050
-#define AT91_PMC_MCKR_PRES_64 0x00000060
-#define AT91_PMC_MCKR_PRES_MASK 0x00000070
-#else
-#define AT91_PMC_MCKR_PRES_1 0x00000000
-#define AT91_PMC_MCKR_PRES_2 0x00000004
-#define AT91_PMC_MCKR_PRES_4 0x00000008
-#define AT91_PMC_MCKR_PRES_8 0x0000000C
-#define AT91_PMC_MCKR_PRES_16 0x00000010
-#define AT91_PMC_MCKR_PRES_32 0x00000014
-#define AT91_PMC_MCKR_PRES_64 0x00000018
-#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
-#endif
-
-#ifdef CONFIG_AT91RM9200
-#define AT91_PMC_MCKR_MDIV_1 0x00000000
-#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#define AT91_PMC_MCKR_MDIV_3 0x00000200
-#define AT91_PMC_MCKR_MDIV_4 0x00000300
-#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
-#else
-#define AT91_PMC_MCKR_MDIV_1 0x00000000
-#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_MCKR_MDIV_3 0x00000300
-#endif
-#define AT91_PMC_MCKR_MDIV_4 0x00000200
-#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
-#endif
-
-#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000
-#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
-#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
-
-#define AT91_PMC_MCKR_H32MXDIV 0x01000000
-
-#define AT91_PMC_IXR_MOSCS 0x00000001
-#define AT91_PMC_IXR_LOCKA 0x00000002
-#define AT91_PMC_IXR_LOCKB 0x00000004
-#define AT91_PMC_IXR_MCKRDY 0x00000008
-#define AT91_PMC_IXR_LOCKU 0x00000040
-#define AT91_PMC_IXR_PCKRDY0 0x00000100
-#define AT91_PMC_IXR_PCKRDY1 0x00000200
-#define AT91_PMC_IXR_PCKRDY2 0x00000400
-#define AT91_PMC_IXR_PCKRDY3 0x00000800
-#define AT91_PMC_IXR_MOSCSELS 0x00010000
-
-#define AT91_PMC_PCR_PID_MASK (0x3f)
-#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
-#define AT91_PMC_PCR_EN (0x1 << 28)
-
-#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
-#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
-#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
-#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
-#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
-#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
-#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
-#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
-#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
-#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
-#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
-#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
-#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
-#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
-
-#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
-#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
-#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
-
-#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
-#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
-
-#define AT91_PMC_DIV (0xff << 0) /* Divider */
-#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
-#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
-#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
-#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
-#define AT91_PMC_USBDIV_1 (0 << 28)
-#define AT91_PMC_USBDIV_2 (1 << 28)
-#define AT91_PMC_USBDIV_4 (2 << 28)
-#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
-#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
-
-#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
-#define AT91_PMC_CSS_SLOW (0 << 0)
-#define AT91_PMC_CSS_MAIN (1 << 0)
-#define AT91_PMC_CSS_PLLA (2 << 0)
-#define AT91_PMC_CSS_PLLB (3 << 0)
-#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
-#define AT91_PMC_PRES_1 (0 << 2)
-#define AT91_PMC_PRES_2 (1 << 2)
-#define AT91_PMC_PRES_4 (2 << 2)
-#define AT91_PMC_PRES_8 (3 << 2)
-#define AT91_PMC_PRES_16 (4 << 2)
-#define AT91_PMC_PRES_32 (5 << 2)
-#define AT91_PMC_PRES_64 (6 << 2)
-#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
-#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
-#define AT91RM9200_PMC_MDIV_2 (1 << 8)
-#define AT91RM9200_PMC_MDIV_3 (2 << 8)
-#define AT91RM9200_PMC_MDIV_4 (3 << 8)
-#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
-#define AT91SAM9_PMC_MDIV_2 (1 << 8)
-#define AT91SAM9_PMC_MDIV_4 (2 << 8)
-#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
-#define AT91SAM9_PMC_MDIV_6 (3 << 8)
-#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
-#define AT91_PMC_PDIV_1 (0 << 12)
-#define AT91_PMC_PDIV_2 (1 << 12)
-
-#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
-#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
-#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
-#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
-#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
-#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
-
-#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
-#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
-#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
-#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
-#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
-#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
-#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
-#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
-#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
-
-#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-/* Reset Controller Status Register */
-#define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04)
-#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rstc {
- u32 cr; /* Reset Controller Control Register */
- u32 sr; /* Reset Controller Status Register */
- u32 mr; /* Reset Controller Mode Register */
-} at91_rstc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RSTC_KEY 0xA5000000
-
-#define AT91_RSTC_CR_PROCRST 0x00000001
-#define AT91_RSTC_CR_PERRST 0x00000004
-#define AT91_RSTC_CR_EXTRST 0x00000008
-
-#define AT91_RSTC_MR_URSTEN 0x00000001
-#define AT91_RSTC_MR_URSTIEN 0x00000010
-#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8)
-#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00
-
-#define AT91_RSTC_SR_NRSTL 0x00010000
-
-#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
-#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
-#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
-#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
-#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
-#define AT91_RSTC_RSTTYP_USER (4 << 8)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Real-time Timer
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rtt {
- u32 mr; /* Mode Register RW 0x00008000 */
- u32 ar; /* Alarm Register RW 0xFFFFFFFF */
- u32 vr; /* Value Register RO 0x00000000 */
- u32 sr; /* Status Register RO 0x00000000 */
-} at91_rtt_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RTT_MR_RTPRES 0x0000ffff
-#define AT91_RTT_MR_ALMIEN 0x00010000
-#define AT91_RTT_RTTINCIEN 0x00020000
-#define AT91_RTT_RTTRST 0x00040000
-
-#define AT91_RTT_SR_ALMS 0x00000001
-#define AT91_RTT_SR_RTTINC 0x00000002
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#include <asm/arch/at91_pdc.h>
-
-typedef struct at91_spi {
- u32 cr; /* 0x00 Control Register */
- u32 mr; /* 0x04 Mode Register */
- u32 rdr; /* 0x08 Receive Data Register */
- u32 tdr; /* 0x0C Transmit Data Register */
- u32 sr; /* 0x10 Status Register */
- u32 ier; /* 0x14 Interrupt Enable Register */
- u32 idr; /* 0x18 Interrupt Disable Register */
- u32 imr; /* 0x1C Interrupt Mask Register */
- u32 reserve1[4];
- u32 csr[4]; /* 0x30 Chip Select Register 0-3 */
- u32 reserve2[48];
- at91_pdc_t pdc;
-} at91_spi_t;
-
-#ifdef CONFIG_ATMEL_LEGACY
-
-#define AT91_SPI_CR 0x00 /* Control Register */
-#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
-#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
-#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR 0x04 /* Mode Register */
-#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
-#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
-#define AT91_SPI_PS_FIXED (0 << 1)
-#define AT91_SPI_PS_VARIABLE (1 << 1)
-#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
-#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
-#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
-#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
-#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR 0x08 /* Receive Data Register */
-#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
-
-#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
-#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR 0x10 /* Status Register */
-#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
-#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
-#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
-#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
-#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
-#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
-#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
-#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
-#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
-#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
-#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
-
-#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
-#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
-#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
-#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
-#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
-#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
-#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
-#define AT91_SPI_BITS_8 (0 << 4)
-#define AT91_SPI_BITS_9 (1 << 4)
-#define AT91_SPI_BITS_10 (2 << 4)
-#define AT91_SPI_BITS_11 (3 << 4)
-#define AT91_SPI_BITS_12 (4 << 4)
-#define AT91_SPI_BITS_13 (5 << 4)
-#define AT91_SPI_BITS_14 (6 << 4)
-#define AT91_SPI_BITS_15 (7 << 4)
-#define AT91_SPI_BITS_16 (8 << 4)
-#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
-#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
-#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
-
-#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
-
-#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
-
-#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
-
-#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
-
-#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
-
-#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
-
-#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
-
-#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
-
-#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
-#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
-#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
-#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
-#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
-
-#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
-
-#endif /* CONFIG_ATMEL_LEGACY */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-typedef struct at91_st {
-
- u32 cr;
- u32 pimr;
- u32 wdmr;
- u32 rtmr;
- u32 sr;
- u32 ier;
- u32 idr;
- u32 imr;
- u32 rtar;
- u32 crtr;
-} at91_st_t ;
-
-#define AT91_ST_CR_WDRST 1
-
-#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
-#define AT91_ST_WDMR_RSTEN 0x00010000
-#define AT91_ST_WDMR_EXTEN 0x00020000
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-typedef struct at91_tcc {
- u32 ccr; /* 0x00 Channel Control Register */
- u32 cmr; /* 0x04 Channel Mode Register */
- u32 reserved1[2];
- u32 cv; /* 0x10 Counter Value */
- u32 ra; /* 0x14 Register A */
- u32 rb; /* 0x18 Register B */
- u32 rc; /* 0x1C Register C */
- u32 sr; /* 0x20 Status Register */
- u32 ier; /* 0x24 Interrupt Enable Register */
- u32 idr; /* 0x28 Interrupt Disable Register */
- u32 imr; /* 0x2C Interrupt Mask Register */
- u32 reserved3[4];
-} at91_tcc_t;
-
-#define AT91_TC_CCR_CLKEN 0x00000001
-#define AT91_TC_CCR_CLKDIS 0x00000002
-#define AT91_TC_CCR_SWTRG 0x00000004
-
-#define AT91_TC_CMR_CPCTRG 0x00004000
-
-#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
-#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
-#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
-#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
-#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
-#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
-#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
-#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
-
-typedef struct at91_tc {
- at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
- u32 bcr; /* 0xC0 TC Block Control Register */
- u32 bmr; /* 0xC4 TC Block Mode Register */
-} at91_tc_t;
-
-#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
-#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
-#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
-#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
-
-#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
-#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
-#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
-#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
-
-#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
-#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
-#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
-#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#ifdef __ASSEMBLY__
-
-#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
-
-#else
-
-typedef struct at91_wdt {
- u32 cr;
- u32 mr;
- u32 sr;
-} at91_wdt_t;
-
-#endif
-
-#define AT91_WDT_CR_WDRSTT 1
-#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
-
-#define AT91_WDT_MR_WDV(x) (x & 0xfff)
-#define AT91_WDT_MR_WDFIEN 0x00001000
-#define AT91_WDT_MR_WDRSTEN 0x00002000
-#define AT91_WDT_MR_WDRPROC 0x00004000
-#define AT91_WDT_MR_WDDIS 0x00008000
-#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16)
-#define AT91_WDT_MR_WDDBGHLT 0x10000000
-#define AT91_WDT_MR_WDIDLEHLT 0x20000000
-
-#endif
+++ /dev/null
-/*
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __AT91RM9200_H__
-#define __AT91RM9200_H__
-
-#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
-#define CONFIG_AT91_GPIO /* and require always gpio features */
-
-/* Periperial Identifiers */
-
-#define ATMEL_ID_SYS 1 /* System Peripheral */
-#define ATMEL_ID_PIOA 2 /* PIO port A */
-#define ATMEL_ID_PIOB 3 /* PIO port B */
-#define ATMEL_ID_PIOC 4 /* PIO port C */
-#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */
-#define ATMEL_ID_USART0 6 /* USART 0 */
-#define ATMEL_ID_USART1 7 /* USART 1 */
-#define ATMEL_ID_USART2 8 /* USART 2 */
-#define ATMEL_ID_USART3 9 /* USART 3 */
-#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
-#define ATMEL_ID_UDP 11 /* USB Device Port */
-#define ATMEL_ID_TWI 12 /* Two Wire Interface */
-#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
-#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
-#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */
-#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */
-#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
-#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
-#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
-#define ATMEL_ID_TC3 20 /* Timer Counter 3 */
-#define ATMEL_ID_TC4 21 /* Timer Counter 4 */
-#define ATMEL_ID_TC5 22 /* Timer Counter 5 */
-#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */
-#define ATMEL_ID_EMAC 24 /* Ethernet MAC */
-#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */
-
-#define ATMEL_USB_HOST_BASE 0x00300000
-
-#define ATMEL_BASE_TC 0xFFFA0000
-#define ATMEL_BASE_UDP 0xFFFB0000
-#define ATMEL_BASE_MCI 0xFFFB4000
-#define ATMEL_BASE_TWI 0xFFFB8000
-#define ATMEL_BASE_EMAC 0xFFFBC000
-#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
-#define ATMEL_BASE_USART0 ATMEL_BASE_USART
-#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000)
-#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000)
-#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000)
-
-#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */
-#define ATMEL_BASE_SPI 0xFFFE0000
-
-#define ATMEL_BASE_AIC 0xFFFFF000
-#define ATMEL_BASE_DBGU 0xFFFFF200
-#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */
-#define ATMEL_BASE_PIOA 0xFFFFF400
-#define ATMEL_BASE_PIOB 0xFFFFF600
-#define ATMEL_BASE_PIOC 0xFFFFF800
-#define ATMEL_BASE_PIOD 0xFFFFFA00
-#define ATMEL_BASE_PMC 0xFFFFFC00
-#define ATMEL_BASE_ST 0xFFFFFD00
-#define ATMEL_BASE_RTC 0xFFFFFE00
-#define ATMEL_BASE_MC 0xFFFFFF00
-
-#define AT91_PIO_BASE ATMEL_BASE_PIO
-
-/* AT91RM9200 Periperial Multiplexing A */
-/* Port A */
-#define ATMEL_PMX_AA_EREFCK 0x00000080
-#define ATMEL_PMX_AA_ETXCK 0x00000080
-#define ATMEL_PMX_AA_ETXEN 0x00000100
-#define ATMEL_PMX_AA_ETX0 0x00000200
-#define ATMEL_PMX_AA_ETX1 0x00000400
-#define ATMEL_PMX_AA_ECRS 0x00000800
-#define ATMEL_PMX_AA_ECRSDV 0x00000800
-#define ATMEL_PMX_AA_ERX0 0x00001000
-#define ATMEL_PMX_AA_ERX1 0x00002000
-#define ATMEL_PMX_AA_ERXER 0x00004000
-#define ATMEL_PMX_AA_EMDC 0x00008000
-#define ATMEL_PMX_AA_EMDIO 0x00010000
-
-#define ATMEL_PMX_AA_TXD2 0x00800000
-
-#define ATMEL_PMX_AA_TWD 0x02000000
-#define ATMEL_PMX_AA_TWCK 0x04000000
-
-/* Port B */
-#define ATMEL_PMX_BA_ERXCK 0x00080000
-#define ATMEL_PMX_BA_ECOL 0x00040000
-#define ATMEL_PMX_BA_ERXDV 0x00020000
-#define ATMEL_PMX_BA_ERX3 0x00010000
-#define ATMEL_PMX_BA_ERX2 0x00008000
-#define ATMEL_PMX_BA_ETXER 0x00004000
-#define ATMEL_PMX_BA_ETX3 0x00002000
-#define ATMEL_PMX_BA_ETX2 0x00001000
-
-/* Port B */
-
-#define ATMEL_PMX_CA_BFCK 0x00000001
-#define ATMEL_PMX_CA_BFRDY 0x00000002
-#define ATMEL_PMX_CA_SMOE 0x00000002
-#define ATMEL_PMX_CA_BFAVD 0x00000004
-#define ATMEL_PMX_CA_BFBAA 0x00000008
-#define ATMEL_PMX_CA_SMWE 0x00000008
-#define ATMEL_PMX_CA_BFOE 0x00000010
-#define ATMEL_PMX_CA_BFWE 0x00000020
-#define ATMEL_PMX_CA_NWAIT 0x00000040
-#define ATMEL_PMX_CA_A23 0x00000080
-#define ATMEL_PMX_CA_A24 0x00000100
-#define ATMEL_PMX_CA_A25 0x00000200
-#define ATMEL_PMX_CA_CFRNW 0x00000200
-#define ATMEL_PMX_CA_NCS4 0x00000400
-#define ATMEL_PMX_CA_CFCS 0x00000400
-#define ATMEL_PMX_CA_NCS5 0x00000800
-#define ATMEL_PMX_CA_CFCE1 0x00001000
-#define ATMEL_PMX_CA_NCS6 0x00001000
-#define ATMEL_PMX_CA_CFCE2 0x00002000
-#define ATMEL_PMX_CA_NCS7 0x00002000
-#define ATMEL_PMX_CA_D16_31 0xFFFF0000
-
-#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
-#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
-
-#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
- *
- * (C) 2006 Andrew Victor
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoCs:
- * AT91SAM9260, AT91SAM9G20, AT91SAM9XE
- *
- * Note that those SoCs are mostly software and pin compatible,
- * therefore this file applies to all of them. Differences between
- * those SoCs are concentrated at the end of this file.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Peripherals */
-#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
-#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
-#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
-#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */
-#define ATMEL_ID_USART0 6 /* USART 0 */
-#define ATMEL_ID_USART1 7 /* USART 1 */
-#define ATMEL_ID_USART2 8 /* USART 2 */
-#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
-#define ATMEL_ID_UDP 10 /* USB Device Port */
-#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
-#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-/* Reserved: 15 */
-/* Reserved: 16 */
-#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
-#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
-#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
-#define ATMEL_ID_UHP 20 /* USB Host port */
-#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
-#define ATMEL_ID_ISI 22 /* Image Sensor Interface */
-#define ATMEL_ID_USART3 23 /* USART 3 */
-#define ATMEL_ID_USART4 24 /* USART 4 */
-/* USART5 or TWI1: 25 */
-#define ATMEL_ID_TC3 26 /* Timer Counter 3 */
-#define ATMEL_ID_TC4 27 /* Timer Counter 4 */
-#define ATMEL_ID_TC5 28 /* Timer Counter 5 */
-#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
-#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_TCB0 0xfffa0000
-#define ATMEL_BASE_TC0 0xfffa0000
-#define ATMEL_BASE_TC1 0xfffa0040
-#define ATMEL_BASE_TC2 0xfffa0080
-#define ATMEL_BASE_UDP0 0xfffa4000
-#define ATMEL_BASE_MCI 0xfffa8000
-#define ATMEL_BASE_TWI0 0xfffac000
-#define ATMEL_BASE_USART0 0xfffb0000
-#define ATMEL_BASE_USART1 0xfffb4000
-#define ATMEL_BASE_USART2 0xfffb8000
-#define ATMEL_BASE_SSC0 0xfffbc000
-#define ATMEL_BASE_ISI0 0xfffc0000
-#define ATMEL_BASE_EMAC0 0xfffc4000
-#define ATMEL_BASE_SPI0 0xfffc8000
-#define ATMEL_BASE_SPI1 0xfffcc000
-#define ATMEL_BASE_USART3 0xfffd0000
-#define ATMEL_BASE_USART4 0xfffd4000
-/* USART5 or TWI1: 0xfffd8000 */
-#define ATMEL_BASE_TCB1 0xfffdc000
-#define ATMEL_BASE_TC3 0xfffdc000
-#define ATMEL_BASE_TC4 0xfffdc040
-#define ATMEL_BASE_TC5 0xfffdc080
-#define ATMEL_BASE_ADC 0xfffe0000
-/* Reserved: 0xfffe4000 - 0xffffe7ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS 0xffffe800
-#define ATMEL_BASE_SDRAMC 0xffffea00
-#define ATMEL_BASE_SMC 0xffffec00
-#define ATMEL_BASE_MATRIX 0xffffee00
-#define ATMEL_BASE_CCFG 0xffffef14
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_DBGU 0xfffff200
-#define ATMEL_BASE_PIOA 0xfffff400
-#define ATMEL_BASE_PIOB 0xfffff600
-#define ATMEL_BASE_PIOC 0xfffff800
-/* EEFC: 0xfffffa00 */
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffd00
-#define ATMEL_BASE_SHDWN 0xfffffd10
-#define ATMEL_BASE_RTT 0xfffffd20
-#define ATMEL_BASE_PIT 0xfffffd30
-#define ATMEL_BASE_WDT 0xfffffd40
-/* GPBR(non-XE SoCs): 0xfffffd50 */
-/* GPBR(XE SoCs): 0xfffffd60 */
-/* Reserved: 0xfffffd70 - 0xffffffff */
-
-/*
- * Internal Memory common on all these SoCs
- */
-#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */
-#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
-/* SRAM or FLASH: 0x00200000 */
-/* SRAM: 0x00300000 */
-/* Reserved: 0x00400000 */
-#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
-#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
-#define ATMEL_BASE_CS2 0x30000000
-#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
-#define ATMEL_BASE_CS4 0x50000000
-#define ATMEL_BASE_CS5 0x60000000
-#define ATMEL_BASE_CS6 0x70000000
-#define ATMEL_BASE_CS7 0x80000000
-
-/*
- * Other misc defines
- */
-#ifndef CONFIG_DM_GPIO
-#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */
-#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
-#endif
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-/*
- * SoC specific defines
- */
-#if defined(CONFIG_AT91SAM9XE)
-# define ATMEL_CPU_NAME "AT91SAM9XE"
-# define ATMEL_ID_TWI1 25 /* TWI 1 */
-# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */
-# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */
-# define ATMEL_BASE_TWI1 0xfffd8000
-# define ATMEL_BASE_EEFC 0xfffffa00
-# define ATMEL_BASE_GPBR 0xfffffd60
-#elif defined(CONFIG_AT91SAM9260)
-# define ATMEL_CPU_NAME "AT91SAM9260"
-# define ATMEL_ID_USART5 25 /* USART 5 */
-# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
-# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
-# define ATMEL_BASE_USART5 0xfffd8000
-# define ATMEL_BASE_GPBR 0xfffffd50
-#elif defined(CONFIG_AT91SAM9G20)
-# define ATMEL_CPU_NAME "AT91SAM9G20"
-# define ATMEL_ID_USART5 25 /* USART 5 */
-# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
-# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
-# define ATMEL_BASE_USART5 0xfffd8000
-# define ATMEL_BASE_GPBR 0xfffffd50
-#endif
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * This struct defines access to the matrix' maximum of
- * 16 masters and 16 slaves.
- * However, on the AT91SAM9260/9G20/9XE there exist only
- * 6 Masters and 5 Slaves!
- */
-struct at91_matrix {
- u32 mcfg[16]; /* Master Configuration Registers */
- u32 scfg[16]; /* Slave Configuration Registers */
- u32 pras[16][2]; /* Priority Assignment Slave Registers */
- u32 mrcr; /* Master Remap Control Register */
- u32 filler[0x06];
- u32 ebicsa; /* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17)
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0)
-#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0)
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
- *
- * Copyright (C) SAN People
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoCs:
- * AT91SAM9261, AT91SAM9G10
- *
- * Note that those SoCs are mostly software and pin compatible,
- * therefore this file applies to all of them. Differences between
- * those SoCs are concentrated at the end of this file.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Peripherals */
-#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
-#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
-#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
-/* Reserved: 5 */
-#define ATMEL_ID_USART0 6 /* USART 0 */
-#define ATMEL_ID_USART1 7 /* USART 1 */
-#define ATMEL_ID_USART2 8 /* USART 2 */
-#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
-#define ATMEL_ID_UDP 10 /* USB Device Port */
-#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
-#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
-#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */
-#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
-#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
-#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
-#define ATMEL_ID_UHP 20 /* USB Host port */
-#define ATMEL_ID_LCDC 21 /* LDC Controller */
-/* Reserved: 22-28 */
-#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
-#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_TCB0 0xfffa0000
-#define ATMEL_BASE_TC0 0xfffa0000
-#define ATMEL_BASE_TC1 0xfffa0040
-#define ATMEL_BASE_TC2 0xfffa0080
-#define ATMEL_BASE_UDP0 0xfffa4000
-#define ATMEL_BASE_MCI 0xfffa8000
-#define ATMEL_BASE_TWI0 0xfffac000
-#define ATMEL_BASE_USART0 0xfffb0000
-#define ATMEL_BASE_USART1 0xfffb4000
-#define ATMEL_BASE_USART2 0xfffb8000
-#define ATMEL_BASE_SSC0 0xfffbc000
-#define ATMEL_BASE_SSC1 0xfffc0000
-#define ATMEL_BASE_SSC2 0xfffc4000
-#define ATMEL_BASE_SPI0 0xfffc8000
-#define ATMEL_BASE_SPI1 0xfffcc000
-/* Reserved: 0xfffc4000 - 0xffffe9ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS 0xffffea00
-#define ATMEL_BASE_SDRAMC 0xffffea00
-#define ATMEL_BASE_SMC 0xffffec00
-#define ATMEL_BASE_MATRIX 0xffffee00
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_DBGU 0xfffff200
-#define ATMEL_BASE_PIOA 0xfffff400
-#define ATMEL_BASE_PIOB 0xfffff600
-#define ATMEL_BASE_PIOC 0xfffff800
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffd00
-#define ATMEL_BASE_SHDWN 0xfffffd10
-#define ATMEL_BASE_RTT 0xfffffd20
-#define ATMEL_BASE_PIT 0xfffffd30
-#define ATMEL_BASE_WDT 0xfffffd40
-#define ATMEL_BASE_GPBR 0xfffffd50
-
-/*
- * Internal Memory common on all these SoCs
- */
-#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
-#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */
-
-#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
-#define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */
-
-#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */
-#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
-#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
-#define ATMEL_BASE_CS2 0x30000000
-#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
-#define ATMEL_BASE_CS4 0x50000000
-#define ATMEL_BASE_CS5 0x60000000
-#define ATMEL_BASE_CS6 0x70000000
-#define ATMEL_BASE_CS7 0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
-
-/*
- * SoC specific defines
- */
-#if defined(CONFIG_AT91SAM9261)
-# define ATMEL_CPU_NAME "AT91SAM9261"
-#elif defined(CONFIG_AT91SAM9G10)
-# define ATMEL_CPU_NAME "AT91SAM9G10"
-#endif
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
- u32 mcfg; /* Master Configuration Registers */
- u32 scfg[5]; /* Slave Configuration Registers */
- u32 filler[6];
- u32 ebicsa; /* EBI Chip Select Assignment Register */
-};
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
- *
- * (C) 2007 Atmel Corporation.
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoC:
- * AT91SAM9263
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Peripherals */
-#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
-#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
-#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
-/* Reserved: 5 */
-/* Reserved: 6 */
-#define ATMEL_ID_USART0 7 /* USART 0 */
-#define ATMEL_ID_USART1 8 /* USART 1 */
-#define ATMEL_ID_USART2 9 /* USART 2 */
-#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */
-#define ATMEL_ID_CAN 12 /* CAN */
-#define ATMEL_ID_TWI 13 /* Two-Wire Interface */
-#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */
-#define ATMEL_ID_AC97C 18 /* AC97 Controller */
-#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
-#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_EMAC 21 /* Ethernet */
-/* Reserved: 22 */
-#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */
-#define ATMEL_ID_UDP 24 /* USB Device Port */
-#define ATMEL_ID_ISI 25 /* Image Sensor Interface */
-#define ATMEL_ID_LCDC 26 /* LCD Controller */
-#define ATMEL_ID_DMA 27 /* DMA Controller */
-/* Reserved: 28 */
-#define ATMEL_ID_UHP 29 /* USB Host port */
-#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_UDP 0xfff78000
-#define ATMEL_BASE_TCB0 0xfff7c000
-#define ATMEL_BASE_TC0 0xfff7c000
-#define ATMEL_BASE_TC1 0xfff7c040
-#define ATMEL_BASE_TC2 0xfff7c080
-#define ATMEL_BASE_MCI0 0xfff80000
-#define ATMEL_BASE_MCI1 0xfff84000
-#define ATMEL_BASE_TWI 0xfff88000
-#define ATMEL_BASE_USART0 0xfff8c000
-#define ATMEL_BASE_USART1 0xfff90000
-#define ATMEL_BASE_USART2 0xfff94000
-#define ATMEL_BASE_SSC0 0xfff98000
-#define ATMEL_BASE_SSC1 0xfff9c000
-#define ATMEL_BASE_AC97C 0xfffa0000
-#define ATMEL_BASE_SPI0 0xfffa4000
-#define ATMEL_BASE_SPI1 0xfffa8000
-#define ATMEL_BASE_CAN 0xfffac000
-#define ATMEL_BASE_PWMC 0xfffb8000
-#define ATMEL_BASE_EMAC 0xfffbc000
-#define ATMEL_BASE_ISI 0xfffc4000
-#define ATMEL_BASE_2DGE 0xfffc8000
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_ECC0 0xffffe000
-#define ATMEL_BASE_SDRAMC0 0xffffe200
-#define ATMEL_BASE_SMC0 0xffffe400
-#define ATMEL_BASE_ECC1 0xffffe600
-#define ATMEL_BASE_SDRAMC1 0xffffe800
-#define ATMEL_BASE_SMC1 0xffffea00
-#define ATMEL_BASE_MATRIX 0xffffec00
-#define ATMEL_BASE_CCFG 0xffffed10
-#define ATMEL_BASE_DBGU 0xffffee00
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_PIOA 0xfffff200
-#define ATMEL_BASE_PIOB 0xfffff400
-#define ATMEL_BASE_PIOC 0xfffff600
-#define ATMEL_BASE_PIOD 0xfffff800
-#define ATMEL_BASE_PIOE 0xfffffa00
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffd00
-#define ATMEL_BASE_SHDWC 0xfffffd10
-#define ATMEL_BASE_RTT0 0xfffffd20
-#define ATMEL_BASE_PIT 0xfffffd30
-#define ATMEL_BASE_WDT 0xfffffd40
-#define ATMEL_BASE_RTT1 0xfffffd50
-#define ATMEL_BASE_GPBR 0xfffffd60
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */
-
-#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */
-
-#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */
-
-#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */
-#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */
-#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
-#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
-#define ATMEL_BASE_CS2 0x30000000
-#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
-#define ATMEL_BASE_CS4 0x50000000
-#define ATMEL_BASE_CS5 0x60000000
-#define ATMEL_BASE_CS6 0x70000000
-#define ATMEL_BASE_CS7 0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
-#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME "AT91SAM9263"
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
- *
- * Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * This struct defines access to the matrix' maximum of
- * 16 masters and 16 slaves.
- * Note: not all masters/slaves are available
- */
-struct at91_matrix {
- u32 mcfg[16]; /* Master Configuration Registers */
- u32 scfg[16]; /* Slave Configuration Registers */
- u32 pras[16][2]; /* Priority Assignment Slave Registers */
- u32 mrcr; /* Master Remap Control Register */
- u32 filler[0x06];
- u32 ebicsa; /* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
-#define __ASM_ARCH_AT91SAM9_MATRIX_H
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#include <asm/arch/at91sam9260_matrix.h>
-#elif defined(CONFIG_AT91SAM9261)
-#include <asm/arch/at91sam9261_matrix.h>
-#elif defined(CONFIG_AT91SAM9263)
-#include <asm/arch/at91sam9263_matrix.h>
-#elif defined(CONFIG_AT91SAM9RL)
-#include <asm/arch/at91sam9rl_matrix.h>
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-#include <asm/arch/at91sam9g45_matrix.h>
-#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
-#include <asm/arch/at91sam9x5_matrix.h>
-#else
-#error "Unsupported AT91SAM9/CAP9 processor"
-#endif
-
-#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
+++ /dev/null
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef ATMEL_BASE_SDRAMC
-#define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0
-#endif
-
-#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
-#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
-#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
-#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
-
-#else
-struct sdramc_reg {
- u32 mr;
- u32 tr;
- u32 cr;
- u32 lpr;
- u32 ier;
- u32 idr;
- u32 imr;
- u32 isr;
- u32 mdr;
-};
-
-int sdramc_initialize(unsigned int sdram_address,
- const struct sdramc_reg *p);
-#endif
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
-#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91_SDRAMC_MODE_NORMAL 0
-#define AT91_SDRAMC_MODE_NOP 1
-#define AT91_SDRAMC_MODE_PRECHARGE 2
-#define AT91_SDRAMC_MODE_LMR 3
-#define AT91_SDRAMC_MODE_REFRESH 4
-#define AT91_SDRAMC_MODE_EXT_LMR 5
-#define AT91_SDRAMC_MODE_DEEP 6
-
-#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
-#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
-#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_SDRAMC_NC_8 (0 << 0)
-#define AT91_SDRAMC_NC_9 (1 << 0)
-#define AT91_SDRAMC_NC_10 (2 << 0)
-#define AT91_SDRAMC_NC_11 (3 << 0)
-#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_SDRAMC_NR_11 (0 << 2)
-#define AT91_SDRAMC_NR_12 (1 << 2)
-#define AT91_SDRAMC_NR_13 (2 << 2)
-#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91_SDRAMC_NB_2 (0 << 4)
-#define AT91_SDRAMC_NB_4 (1 << 4)
-#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91_SDRAMC_CAS_1 (1 << 5)
-#define AT91_SDRAMC_CAS_2 (2 << 5)
-#define AT91_SDRAMC_CAS_3 (3 << 5)
-#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
-#define AT91_SDRAMC_DBW_32 (0 << 7)
-#define AT91_SDRAMC_DBW_16 (1 << 7)
-#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
-#define AT91_SDRAMC_TWR_VAL(x) (x << 8)
-#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
-#define AT91_SDRAMC_TRC_VAL(x) (x << 12)
-#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
-#define AT91_SDRAMC_TRP_VAL(x) (x << 16)
-#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
-#define AT91_SDRAMC_TRCD_VAL(x) (x << 20)
-#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
-#define AT91_SDRAMC_TRAS_VAL(x) (x << 24)
-#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
-#define AT91_SDRAMC_TXSR_VAL(x) (x << 28)
-
-#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
-#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
-#define AT91_SDRAMC_LPCB_DISABLE 0
-#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
-#define AT91_SDRAMC_LPCB_POWER_DOWN 2
-#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
-#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
-#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
-#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
-#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
-#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
-#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
-#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
-
-#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
-#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
-#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
-#define AT91_SDRAMC_MD_SDRAM 0
-#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef ATMEL_BASE_SMC
-#define ATMEL_BASE_SMC ATMEL_BASE_SMC0
-#endif
-
-#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
-#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
-#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
-#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
-
-#else
-
-typedef struct at91_cs {
- u32 setup; /* 0x00 SMC Setup Register */
- u32 pulse; /* 0x04 SMC Pulse Register */
- u32 cycle; /* 0x08 SMC Cycle Register */
- u32 mode; /* 0x0C SMC Mode Register */
-} at91_cs_t;
-
-typedef struct at91_smc {
- at91_cs_t cs[8];
-} at91_smc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
-#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
-#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
-#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
-
-#define AT91_SMC_PULSE_NWE(x) (x & 0x7f)
-#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8)
-#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16)
-#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24)
-
-#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
-#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
-
-#define AT91_SMC_MODE_RM_NCS 0x00000000
-#define AT91_SMC_MODE_RM_NRD 0x00000001
-#define AT91_SMC_MODE_WM_NCS 0x00000000
-#define AT91_SMC_MODE_WM_NWE 0x00000002
-
-#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
-#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
-#define AT91_SMC_MODE_EXNW_READY 0x00000030
-
-#define AT91_SMC_MODE_BAT 0x00000100
-#define AT91_SMC_MODE_DBW_8 0x00000000
-#define AT91_SMC_MODE_DBW_16 0x00001000
-#define AT91_SMC_MODE_DBW_32 0x00002000
-#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
-#define AT91_SMC_MODE_TDF 0x00100000
-#define AT91_SMC_MODE_PMEN 0x01000000
-#define AT91_SMC_MODE_PS_4 0x00000000
-#define AT91_SMC_MODE_PS_8 0x10000000
-#define AT91_SMC_MODE_PS_16 0x20000000
-#define AT91_SMC_MODE_PS_32 0x30000000
-
-#endif
+++ /dev/null
-/*
- * Chip-specific header file for the AT91SAM9M1x family
- *
- * (C) 2008 Atmel Corporation.
- *
- * Definitions for the SoC:
- * AT91SAM9G45
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
-#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
-#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */
-#define ATMEL_ID_TRNG 6 /* True Random Number Generator */
-#define ATMEL_ID_USART0 7 /* USART 0 */
-#define ATMEL_ID_USART1 8 /* USART 1 */
-#define ATMEL_ID_USART2 9 /* USART 2 */
-#define ATMEL_ID_USART3 10 /* USART 3 */
-#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */
-#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */
-#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */
-#define ATMEL_ID_DMA 21 /* DMA Controller */
-#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
-#define ATMEL_ID_LCDC 23 /* LCD Controller */
-#define ATMEL_ID_AC97C 24 /* AC97 Controller */
-#define ATMEL_ID_EMAC 25 /* Ethernet MAC */
-#define ATMEL_ID_ISI 26 /* Image Sensor Interface */
-#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */
-#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
-#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_VDEC 30 /* Video Decoder */
-#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_UDPHS 0xfff78000
-#define ATMEL_BASE_TC0 0xfff7c000
-#define ATMEL_BASE_TC1 0xfff7c040
-#define ATMEL_BASE_TC2 0xfff7c080
-#define ATMEL_BASE_MCI0 0xfff80000
-#define ATMEL_BASE_TWI0 0xfff84000
-#define ATMEL_BASE_TWI1 0xfff88000
-#define ATMEL_BASE_USART0 0xfff8c000
-#define ATMEL_BASE_USART1 0xfff90000
-#define ATMEL_BASE_USART2 0xfff94000
-#define ATMEL_BASE_USART3 0xfff98000
-#define ATMEL_BASE_SSC0 0xfff9c000
-#define ATMEL_BASE_SSC1 0xfffa0000
-#define ATMEL_BASE_SPI0 0xfffa4000
-#define ATMEL_BASE_SPI1 0xfffa8000
-#define ATMEL_BASE_AC97C 0xfffac000
-#define ATMEL_BASE_TSC 0xfffb0000
-#define ATMEL_BASE_ISI 0xfffb4000
-#define ATMEL_BASE_PWMC 0xfffb8000
-#define ATMEL_BASE_EMAC 0xfffbc000
-#define ATMEL_BASE_AES 0xfffc0000
-#define ATMEL_BASE_TDES 0xfffc4000
-#define ATMEL_BASE_SHA 0xfffc8000
-#define ATMEL_BASE_TRNG 0xfffcc000
-#define ATMEL_BASE_MCI1 0xfffd0000
-#define ATMEL_BASE_TC3 0xfffd4000
-#define ATMEL_BASE_TC4 0xfffd4040
-#define ATMEL_BASE_TC5 0xfffd4080
-/* Reserved: 0xfffd8000 - 0xffffe1ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS 0xffffe200
-#define ATMEL_BASE_ECC 0xffffe200
-#define ATMEL_BASE_DDRSDRC1 0xffffe400
-#define ATMEL_BASE_DDRSDRC0 0xffffe600
-#define ATMEL_BASE_SMC 0xffffe800
-#define ATMEL_BASE_MATRIX 0xffffea00
-#define ATMEL_BASE_DMA 0xffffec00
-#define ATMEL_BASE_DBGU 0xffffee00
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_PIOA 0xfffff200
-#define ATMEL_BASE_PIOB 0xfffff400
-#define ATMEL_BASE_PIOC 0xfffff600
-#define ATMEL_BASE_PIOD 0xfffff800
-#define ATMEL_BASE_PIOE 0xfffffa00
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffd00
-#define ATMEL_BASE_SHDWN 0xfffffd10
-#define ATMEL_BASE_RTT 0xfffffd20
-#define ATMEL_BASE_PIT 0xfffffd30
-#define ATMEL_BASE_WDT 0xfffffd40
-#define ATMEL_BASE_GPBR 0xfffffd60
-#define ATMEL_BASE_RTC 0xfffffdb0
-/* Reserved: 0xfffffdc0 - 0xffffffff */
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
-#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
-#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
-#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
-#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
-#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000
-#define ATMEL_BASE_CS1 0x20000000
-#define ATMEL_BASE_CS2 0x30000000
-#define ATMEL_BASE_CS3 0x40000000
-#define ATMEL_BASE_CS4 0x50000000
-#define ATMEL_BASE_CS5 0x60000000
-#define ATMEL_BASE_CS6 0x70000000
-#define ATMEL_BASE_CS7 0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
-#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME "AT91SAM9G45"
-
-#endif
+++ /dev/null
-/*
- * Matrix-centric header file for the AT91SAM9M1x family
- *
- * Copyright (C) 2008 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91SAM9G45_MATRIX_H
-#define AT91SAM9G45_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
- u32 mcfg[16];
- u32 scfg[16];
- u32 pras[16][2];
- u32 mrcr; /* 0x100 Master Remap Control */
- u32 filler[3];
- u32 tcmr;
- u32 filler2;
- u32 ddrmpr;
- u32 filler3[3];
- u32 ebicsa;
- u32 filler4[47];
- u32 wpmr;
- u32 wpsr;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-#define AT91_MATRIX_M6PR_SHIFT 24
-#define AT91_MATRIX_M7PR_SHIFT 28
-
-#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
-#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
-#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
-#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
- *
- * Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Peripherals */
-#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
-#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
-#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
-#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */
-#define ATMEL_ID_USART0 6 /* USART 0 */
-#define ATMEL_ID_USART1 7 /* USART 1 */
-#define ATMEL_ID_USART2 8 /* USART 2 */
-#define ATMEL_ID_USART3 9 /* USART 3 */
-#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
-#define ATMEL_ID_TWI0 11 /* TWI 0 */
-#define ATMEL_ID_TWI1 12 /* TWI 1 */
-#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
-#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
-#define ATMEL_ID_TC0 16 /* Timer Counter 0 */
-#define ATMEL_ID_TC1 17 /* Timer Counter 1 */
-#define ATMEL_ID_TC2 18 /* Timer Counter 2 */
-#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC 20 /* Touch Screen Controller */
-#define ATMEL_ID_DMA 21 /* DMA Controller */
-#define ATMEL_ID_UDPHS 22 /* USB Device HS */
-#define ATMEL_ID_LCDC 23 /* LCD Controller */
-#define ATMEL_ID_AC97C 24 /* AC97 Controller */
-#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define ATMEL_BASE_TCB0 0xfffa0000
-#define ATMEL_BASE_TC0 0xfffa0000
-#define ATMEL_BASE_TC1 0xfffa0040
-#define ATMEL_BASE_TC2 0xfffa0080
-#define ATMEL_BASE_MCI 0xfffa4000
-#define ATMEL_BASE_TWI0 0xfffa8000
-#define ATMEL_BASE_TWI1 0xfffac000
-#define ATMEL_BASE_USART0 0xfffb0000
-#define ATMEL_BASE_USART1 0xfffb4000
-#define ATMEL_BASE_USART2 0xfffb8000
-#define ATMEL_BASE_USART3 0xfffbc000
-#define ATMEL_BASE_SSC0 0xfffc0000
-#define ATMEL_BASE_SSC1 0xfffc4000
-#define ATMEL_BASE_PWMC 0xfffc8000
-#define ATMEL_BASE_SPI0 0xfffcc000
-#define ATMEL_BASE_TSC 0xfffd0000
-#define ATMEL_BASE_UDPHS 0xfffd4000
-#define ATMEL_BASE_AC97C 0xfffd8000
-#define ATMEL_BASE_SYS 0xffffc000
-
-/*
- * System Peripherals
- */
-#define ATMEL_BASE_DMA 0xffffe600
-#define ATMEL_BASE_ECC 0xffffe800
-#define ATMEL_BASE_SDRAMC 0xffffea00
-#define ATMEL_BASE_SMC 0xffffec00
-#define ATMEL_BASE_MATRIX 0xffffee00
-#define ATMEL_BASE_CCFG 0xffffef10
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_DBGU 0xfffff200
-#define ATMEL_BASE_PIOA 0xfffff400
-#define ATMEL_BASE_PIOB 0xfffff600
-#define ATMEL_BASE_PIOC 0xfffff800
-#define ATMEL_BASE_PIOD 0xfffffa00
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffd00
-#define ATMEL_BASE_SHDWC 0xfffffd10
-#define ATMEL_BASE_RTT 0xfffffd20
-#define ATMEL_BASE_PIT 0xfffffd30
-#define ATMEL_BASE_WDT 0xfffffd40
-#define ATMEL_BASE_SCKCR 0xfffffd50
-#define ATMEL_BASE_GPBR 0xfffffd60
-#define ATMEL_BASE_RTC 0xfffffe00
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
-#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
-
-#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
-#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000
-#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
-#define ATMEL_BASE_CS2 0x30000000
-#define ATMEL_BASE_CS3 0x40000000 /* NAND */
-#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */
-#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */
-#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
-
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME "AT91SAM9RL"
-
-#endif
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_MATRIX_H
-#define AT91SAM9RL_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
- u32 mcfg[16]; /* Master Configuration Registers */
- u32 scfg[16]; /* Slave Configuration Registers */
- u32 pras[16][2]; /* Priority Assignment Slave Registers */
- u32 mrcr; /* Master Remap Control Register */
- u32 filler[7];
- u32 ebicsa; /* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
-
-#endif
+++ /dev/null
-/*
- * Chip-specific header file for the AT91SAM9x5 family
- *
- * Copyright (C) 2012-2013 Atmel Corporation.
- *
- * Definitions for the SoC:
- * AT91SAM9x5 & AT91SAM9N12
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __AT91SAM9X5_H__
-#define __AT91SAM9X5_H__
-
-#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
-#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
-#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
-#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */
-#define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */
-#define ATMEL_ID_USART0 5 /* USART 0 */
-#define ATMEL_ID_USART1 6 /* USART 1 */
-#define ATMEL_ID_USART2 7 /* USART 2 */
-#define ATMEL_ID_USART3 8 /* USART 3 */
-#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
-#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_UART0 15 /* UART 0 */
-#define ATMEL_ID_UART1 16 /* UART 1 */
-#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_ADC 19 /* ADC Controller */
-#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
-#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
-#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
-#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
-#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
-#define ATMEL_ID_LCDC 25 /* LCD Controller */
-#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
-#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
-#define ATMEL_ID_TRNG 30 /* True Random Number Generator */
-#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define ATMEL_BASE_SPI0 0xf0000000
-#define ATMEL_BASE_SPI1 0xf0004000
-#define ATMEL_BASE_HSMCI0 0xf0008000
-#define ATMEL_BASE_HSMCI1 0xf000c000
-#define ATMEL_BASE_SSC 0xf0010000
-#define ATMEL_BASE_CAN0 0xf8000000
-#define ATMEL_BASE_CAN1 0xf8004000
-#define ATMEL_BASE_TC0 0xf8008000
-#define ATMEL_BASE_TC1 0xf8008040
-#define ATMEL_BASE_TC2 0xf8008080
-#define ATMEL_BASE_TC3 0xf800c000
-#define ATMEL_BASE_TC4 0xf800c040
-#define ATMEL_BASE_TC5 0xf800c080
-#define ATMEL_BASE_TWI0 0xf8010000
-#define ATMEL_BASE_TWI1 0xf8014000
-#define ATMEL_BASE_TWI2 0xf8018000
-#define ATMEL_BASE_USART0 0xf801c000
-#define ATMEL_BASE_USART1 0xf8020000
-#define ATMEL_BASE_USART2 0xf8024000
-#define ATMEL_BASE_USART3 0xf8028000
-#define ATMEL_BASE_EMAC0 0xf802c000
-#define ATMEL_BASE_EMAC1 0xf8030000
-#define ATMEL_BASE_PWM 0xf8034000
-#define ATMEL_BASE_LCDC 0xf8038000
-#define ATMEL_BASE_UDPHS 0xf803c000
-#define ATMEL_BASE_UART0 0xf8040000
-#define ATMEL_BASE_UART1 0xf8044000
-#define ATMEL_BASE_ISI 0xf8048000
-#define ATMEL_BASE_ADC 0xf804c000
-#define ATMEL_BASE_SYS 0xffffc000
-
-/*
- * System Peripherals
- */
-#define ATMEL_BASE_FUSE 0xffffdc00
-#define ATMEL_BASE_MATRIX 0xffffde00
-#define ATMEL_BASE_PMECC 0xffffe000
-#define ATMEL_BASE_PMERRLOC 0xffffe600
-#define ATMEL_BASE_DDRSDRC 0xffffe800
-#define ATMEL_BASE_SMC 0xffffea00
-#define ATMEL_BASE_DMAC0 0xffffec00
-#define ATMEL_BASE_DMAC1 0xffffee00
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_DBGU 0xfffff200
-#define ATMEL_BASE_PIOA 0xfffff400
-#define ATMEL_BASE_PIOB 0xfffff600
-#define ATMEL_BASE_PIOC 0xfffff800
-#define ATMEL_BASE_PIOD 0xfffffa00
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffe00
-#define ATMEL_BASE_SHDWC 0xfffffe10
-#define ATMEL_BASE_PIT 0xfffffe30
-#define ATMEL_BASE_WDT 0xfffffe40
-#define ATMEL_BASE_GPBR 0xfffffe60
-#define ATMEL_BASE_RTC 0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
-#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
-
-#ifdef CONFIG_AT91SAM9N12
-#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */
-#else /* AT91SAM9X5 */
-#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
-#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
-#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
-#endif
-
-/* 9x5 series chip id definitions */
-#define ARCH_ID_AT91SAM9X5 0x819a05a0
-#define ARCH_ID_VERSION_MASK 0x1f
-#define ARCH_EXID_AT91SAM9G15 0x00000000
-#define ARCH_EXID_AT91SAM9G35 0x00000001
-#define ARCH_EXID_AT91SAM9X35 0x00000002
-#define ARCH_EXID_AT91SAM9G25 0x00000003
-#define ARCH_EXID_AT91SAM9X25 0x00000004
-
-#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
-#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
- (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
-#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
- (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
-#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
- (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
-#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
- (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
-#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
- (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
-
-/*
- * Cpu Name
- */
-#ifdef CONFIG_AT91SAM9N12
-#define ATMEL_CPU_NAME "AT91SAM9N12"
-#else /* AT91SAM9X5 */
-#define ATMEL_CPU_NAME get_cpu_name()
-#endif
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 4
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-
-/*
- * PMECC table in ROM
- */
-#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
-#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
-
-/*
- * at91sam9x5 specific prototypes
- */
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_emac1(void);
-unsigned int has_emac0(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
+++ /dev/null
-/*
- * Matrix-centric header file for the AT91SAM9X5 family
- *
- * Copyright (C) 2012-2013 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __AT91SAM9X5_MATRIX_H__
-#define __AT91SAM9X5_MATRIX_H__
-
-#ifndef __ASSEMBLY__
-
-/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
-struct at91_matrix {
- u32 mcfg[16];
- u32 scfg[16];
- u32 pras[16][2];
- u32 mrcr; /* 0x100 Master Remap Control */
- u32 filler[5];
-#ifdef CONFIG_AT91SAM9X5
- u32 filler1[2];
-#endif
- /* EBI Chip Select Assignment Register
- * 0x118: AT91SAM9N12
- * 0x120: AT91SAM9X5
- */
- u32 ebicsa;
- u32 filler4[47];
-#ifdef CONFIG_AT91SAM9N12
- u32 filler5[2];
-#endif
- u32 wpmr;
- u32 wpsr;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-
-#define AT91_MATRIX_M0PR_SHIFT 0
-#define AT91_MATRIX_M1PR_SHIFT 4
-#define AT91_MATRIX_M2PR_SHIFT 8
-#define AT91_MATRIX_M3PR_SHIFT 12
-#define AT91_MATRIX_M4PR_SHIFT 16
-#define AT91_MATRIX_M5PR_SHIFT 20
-#define AT91_MATRIX_M6PR_SHIFT 24
-#define AT91_MATRIX_M7PR_SHIFT 28
-
-#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
-#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
-#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
-#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
-
-#define AT91_MATRIX_RCB0 (1 << 0)
-#define AT91_MATRIX_RCB1 (1 << 1)
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
-#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
-#define AT91_MATRIX_MP_OFF (0 << 25)
-#define AT91_MATRIX_MP_ON (1 << 25)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ATMEL_MPDDRC_H__
-#define __ATMEL_MPDDRC_H__
-
-/*
- * Only define the needed register in mpddr
- * If other register needed, will add them later
- */
-struct atmel_mpddr {
- u32 mr;
- u32 rtr;
- u32 cr;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 reserved[2];
- u32 md;
-};
-
-int ddr2_init(const unsigned int ram_address,
- const struct atmel_mpddr *mpddr);
-
-/* Bit field in mode register */
-#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
-#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
-#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2
-#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3
-#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4
-#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
-#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
-#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
-
-/* Bit field in configuration register */
-#define ATMEL_MPDDRC_CR_NC_MASK 0x3
-#define ATMEL_MPDDRC_CR_NC_COL_9 0x0
-#define ATMEL_MPDDRC_CR_NC_COL_10 0x1
-#define ATMEL_MPDDRC_CR_NC_COL_11 0x2
-#define ATMEL_MPDDRC_CR_NC_COL_12 0x3
-#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2)
-#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4)
-#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
-#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
-#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
-#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
-#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16)
-#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
-#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20)
-#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21)
-#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22)
-#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23)
-
-/* Bit field in timing parameter 0 register */
-#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0
-#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4
-#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8
-#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12
-#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16
-#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20
-#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
-#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24
-#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7
-#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27
-#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1
-#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28
-#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
-
-/* Bit field in timing parameter 1 register */
-#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0
-#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f
-#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8
-#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff
-#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16
-#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff
-#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24
-#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
-
-/* Bit field in timing parameter 2 register */
-#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0
-#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
-#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4
-#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
-#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8
-#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf
-#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12
-#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7
-#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16
-#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
-
-/* Bit field in Memory Device Register */
-#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
-#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
-#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
-#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
-#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ATMEL_SERIAL_H
-#define _ATMEL_SERIAL_H
-
-/* Information about a serial port */
-struct atmel_serial_platdata {
- uint32_t base_addr;
-};
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2005-2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ATMEL_USBA_UDC_H__
-#define __ATMEL_USBA_UDC_H__
-
-#include <linux/usb/atmel_usba_udc.h>
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
- [idx] = { \
- .name = nam, \
- .index = idx, \
- .fifo_size = maxpkt, \
- .nr_banks = maxbk, \
- .can_dma = dma, \
- .can_isoc = isoc, \
- }
-
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9X5)
-static struct usba_ep_data usba_udc_ep[] = {
- EP("ep0", 0, 64, 1, 0, 0),
- EP("ep1", 1, 1024, 2, 1, 1),
- EP("ep2", 2, 1024, 2, 1, 1),
- EP("ep3", 3, 1024, 3, 1, 0),
- EP("ep4", 4, 1024, 3, 1, 0),
- EP("ep5", 5, 1024, 3, 1, 1),
- EP("ep6", 6, 1024, 3, 1, 1),
-};
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-static struct usba_ep_data usba_udc_ep[] = {
- EP("ep0", 0, 64, 1, 0, 0),
- EP("ep1", 1, 1024, 3, 1, 0),
- EP("ep2", 2, 1024, 3, 1, 0),
- EP("ep3", 3, 1024, 2, 1, 0),
- EP("ep4", 4, 1024, 2, 1, 0),
- EP("ep5", 5, 1024, 2, 1, 0),
- EP("ep6", 6, 1024, 2, 1, 0),
- EP("ep7", 7, 1024, 2, 1, 0),
- EP("ep8", 8, 1024, 2, 0, 0),
- EP("ep9", 9, 1024, 2, 0, 0),
- EP("ep10", 10, 1024, 2, 0, 0),
- EP("ep11", 11, 1024, 2, 0, 0),
- EP("ep12", 12, 1024, 2, 0, 0),
- EP("ep13", 13, 1024, 2, 0, 0),
- EP("ep14", 14, 1024, 2, 0, 0),
- EP("ep15", 15, 1024, 2, 0, 0),
-};
-#else
-# error "NO usba_udc_ep defined"
-#endif
-
-#undef EP
-
-struct usba_platform_data pdata = {
- .num_ep = ARRAY_SIZE(usba_udc_ep),
- .ep = usba_udc_ep,
-};
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARM_ARCH_CLK_H__
-#define __ASM_ARM_ARCH_CLK_H__
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/global_data.h>
-
-static inline unsigned long get_cpu_clk_rate(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.cpu_clk_rate_hz;
-}
-
-static inline unsigned long get_main_clk_rate(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.main_clk_rate_hz;
-}
-
-static inline unsigned long get_mck_clk_rate(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.mck_rate_hz;
-}
-
-static inline unsigned long get_plla_clk_rate(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.plla_rate_hz;
-}
-
-static inline unsigned long get_pllb_clk_rate(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.pllb_rate_hz;
-}
-
-static inline u32 get_pllb_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- return gd->arch.at91_pllb_usb_init;
-}
-
-#ifdef CPU_HAS_H32MXDIV
-static inline unsigned int get_h32mxdiv(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
-}
-#else
-static inline unsigned int get_h32mxdiv(void)
-{
- return 0;
-}
-#endif
-
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
-{
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_mci_clk_rate(void)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-static inline unsigned long get_pit_clk_rate(void)
-{
- if (get_h32mxdiv())
- return get_mck_clk_rate() / 2;
- else
- return get_mck_clk_rate();
-}
-
-int at91_clock_init(unsigned long main_clock);
-void at91_periph_clk_enable(int id);
-void at91_periph_clk_disable(int id);
-#endif /* __ASM_ARM_ARCH_CLK_H__ */
+++ /dev/null
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
- *
- * Copyright (C) 2005 HP Labs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_AT91_GPIO_H
-#define __ASM_ARCH_AT91_GPIO_H
-
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_ATMEL_LEGACY
-
-#define PIN_BASE 0
-
-#define MAX_GPIO_BANKS 5
-
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-
-#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
-#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
-#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
-#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
-#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
-#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
-#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
-#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
-#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
-#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
-#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
-#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
-#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
-#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
-#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
-#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
-#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
-#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
-#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
-#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
-#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
-#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
-#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
-#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
-#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
-#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
-#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
-#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
-#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
-#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
-#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
-#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
-
-#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
-#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
-#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
-#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
-#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
-#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
-#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
-#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
-#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
-#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
-#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
-#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
-#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
-#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
-#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
-#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
-#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
-#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
-#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
-#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
-#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
-#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
-#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
-#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
-#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
-#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
-#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
-#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
-#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
-#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
-#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
-#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
-
-#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
-#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
-#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
-#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
-#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
-#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
-#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
-#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
-#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
-#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
-#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
-#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
-#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
-#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
-#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
-#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
-#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
-#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
-#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
-#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
-#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
-#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
-#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
-#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
-#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
-#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
-#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
-#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
-#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
-#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
-#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
-#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
-
-#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
-#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
-#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
-#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
-#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
-#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
-#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
-#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
-#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
-#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
-#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
-#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
-#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
-#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
-#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
-#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
-#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
-#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
-#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
-#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
-#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
-#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
-#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
-#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
-#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
-#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
-#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
-#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
-#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
-#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
-#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
-#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
-
-#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
-#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
-#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
-#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
-#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
-#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
-#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
-#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
-#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
-#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
-#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
-#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
-#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
-#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
-#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
-#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
-#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
-#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
-#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
-#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
-#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
-#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
-#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
-#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
-#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
-#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
-#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
-#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
-#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
-#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
-#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
-#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
-
-static unsigned long at91_pios[] = {
- ATMEL_BASE_PIOA,
- ATMEL_BASE_PIOB,
- ATMEL_BASE_PIOC,
-#ifdef ATMEL_BASE_PIOD
- ATMEL_BASE_PIOD,
-#ifdef ATMEL_BASE_PIOE
- ATMEL_BASE_PIOE
-#endif
-#endif
-};
-
-static inline void *pin_to_controller(unsigned pin)
-{
- pin -= PIN_BASE;
- pin /= 32;
- return (void *)(at91_pios[pin]);
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
- pin -= PIN_BASE;
- return 1 << (pin % 32);
-}
-
-/* The following macros are need for backward compatibility */
-#define at91_set_GPIO_periph(x, y) \
- at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_A_periph(x, y) \
- at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_B_periph(x, y) \
- at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_output(x, y) \
- at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_input(x, y) \
- at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_value(x, y) \
- at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_get_gpio_value(x) \
- at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
-#else
-#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
-#define at91_get_gpio_value(x) at91_get_pio_value(x)
-#endif
-
-#define GPIO_PIOA_BASE (0)
-#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
-#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
-#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
-#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
-#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
-#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
-#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
-#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
-
-static inline unsigned at91_gpio_to_port(unsigned gpio)
-{
- return gpio / 32;
-}
-
-static inline unsigned at91_gpio_to_pin(unsigned gpio)
-{
- return gpio % 32;
-}
-
-/* Platform data for each GPIO port */
-struct at91_port_platdata {
- uint32_t base_addr;
- const char *bank_name;
-};
-
-#endif /* __ASM_ARCH_AT91_GPIO_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARM_ARCH_HARDWARE_H__
-#define __ASM_ARM_ARCH_HARDWARE_H__
-
-#if defined(CONFIG_AT91RM9200)
-# include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9XE)
-# include <asm/arch/at91sam9260.h>
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
-# include <asm/arch/at91sam9261.h>
-#elif defined(CONFIG_AT91SAM9263)
-# include <asm/arch/at91sam9263.h>
-#elif defined(CONFIG_AT91SAM9RL)
-# include <asm/arch/at91sam9rl.h>
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-# include <asm/arch/at91sam9g45.h>
-#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
-# include <asm/arch/at91sam9x5.h>
-#elif defined(CONFIG_SAMA5D3)
-# include <asm/arch/sama5d3.h>
-#elif defined(CONFIG_SAMA5D4)
-# include <asm/arch/sama5d4.h>
-#else
-# error "Unsupported AT91 processor"
-#endif
-
-#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */
+++ /dev/null
-/*
- * Bus Matrix header file for the SAMA5 family
- *
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SAMA5_MATRIX_H
-#define __SAMA5_MATRIX_H
-
-struct atmel_matrix {
- u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
- u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
- u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
- u32 res1[20]; /* 0x100 ~ 0x14c */
- u32 meier; /* 0x150: Master Error Interrupt Enable Register */
- u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
- u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
- u32 mesr; /* 0x15c: Master Error Status Register */
- u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
- u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
- u32 wpmr; /* 0x1E4: Write Protection Mode Register */
- u32 wpsr; /* 0x1E8: Write Protection Status Register */
- u32 res3[5]; /* 0x1EC ~ 0x1FC */
- u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */
- u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */
- u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */
- u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
-};
-
-/* Bit field in WPMR */
-#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
-#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
-
-#endif
+++ /dev/null
-/*
- * Special Function Register (SFR)
- *
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
-
-struct atmel_sfr {
- u32 reserved1; /* 0x00 */
- u32 ddrcfg; /* 0x04: DDR Configuration Register */
- u32 reserved2; /* 0x08 */
- u32 reserved3; /* 0x0c */
- u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
- u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
- u32 reserved4[4]; /* 0x18 ~ 0x24 */
- u32 secure; /* 0x28: Security Configuration Register */
- u32 reserved5[5]; /* 0x2c ~ 0x3c */
- u32 ebicfg; /* 0x40: EBI Configuration Register */
- u32 reserved6[2]; /* 0x44 ~ 0x48 */
- u32 sn0; /* 0x4c */
- u32 sn1; /* 0x50 */
- u32 aicredir; /* 0x54 */
-};
-
-/* Bit field in DDRCFG */
-#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
-#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
-
-/* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
-#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
-
-#endif
+++ /dev/null
-/*
- * Chip-specific header file for the SAMA5D3 family
- *
- * (C) 2012 - 2013 Atmel Corporation.
- * Bo Shen <voice.shen@atmel.com>
- *
- * Definitions for the SoC:
- * SAMA5D3
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef SAMA5D3_H
-#define SAMA5D3_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
-#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */
-#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
-#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */
-#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
-#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */
-#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */
-#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */
-#define ATMEL_ID_SMD 11 /* SMD Soft Modem */
-#define ATMEL_ID_USART0 12 /* USART 0 */
-#define ATMEL_ID_USART1 13 /* USART 1 */
-#define ATMEL_ID_USART2 14 /* USART 2 */
-#define ATMEL_ID_USART3 15 /* USART 3 */
-#define ATMEL_ID_UART0 16
-#define ATMEL_ID_UART1 17
-#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
-#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1 22 /* */
-#define ATMEL_ID_MCI2 23 /* */
-#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_TC0 26 /* */
-#define ATMEL_ID_TC1 27 /* */
-#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */
-#define ATMEL_ID_DMA0 30 /* DMA Controller */
-#define ATMEL_ID_DMA1 31 /* DMA Controller */
-#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */
-#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */
-#define ATMEL_ID_GMAC 34
-#define ATMEL_ID_EMAC 35 /* Ethernet MAC */
-#define ATMEL_ID_LCDC 36 /* LCD Controller */
-#define ATMEL_ID_ISI 37 /* Image Sensor Interface */
-#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */
-#define ATMEL_ID_CAN0 40
-#define ATMEL_ID_CAN1 41
-#define ATMEL_ID_SHA 42
-#define ATMEL_ID_AES 43
-#define ATMEL_ID_TDES 44
-#define ATMEL_ID_TRNG 45
-#define ATMEL_ID_ARM 46
-#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */
-#define ATMEL_ID_FUSE 48
-#define ATMEL_ID_MPDDRC 49
-
-/* sama5d3 series chip id definitions */
-#define ARCH_ID_SAMA5D3 0x8a5c07c0
-#define ARCH_EXID_SAMA5D31 0x00444300
-#define ARCH_EXID_SAMA5D33 0x00414300
-#define ARCH_EXID_SAMA5D34 0x00414301
-#define ARCH_EXID_SAMA5D35 0x00584300
-#define ARCH_EXID_SAMA5D36 0x00004301
-
-#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
-#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D31))
-#define cpu_is_sama5d33() (cpu_is_sama5d3() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D33))
-#define cpu_is_sama5d34() (cpu_is_sama5d3() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D34))
-#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D35))
-#define cpu_is_sama5d36() (cpu_is_sama5d3() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D36))
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_MCI0 0xf0000000
-#define ATMEL_BASE_SPI0 0xf0004000
-#define ATMEL_BASE_SSC0 0xf000C000
-#define ATMEL_BASE_TC2 0xf0010000
-#define ATMEL_BASE_TWI0 0xf0014000
-#define ATMEL_BASE_TWI1 0xf0018000
-#define ATMEL_BASE_USART0 0xf001c000
-#define ATMEL_BASE_USART1 0xf0020000
-#define ATMEL_BASE_UART0 0xf0024000
-#define ATMEL_BASE_GMAC 0xf0028000
-#define ATMEL_BASE_PWMC 0xf002c000
-#define ATMEL_BASE_LCDC 0xf0030000
-#define ATMEL_BASE_ISI 0xf0034000
-#define ATMEL_BASE_SFR 0xf0038000
-/* Reserved: 0xf003c000 - 0xf8000000 */
-#define ATMEL_BASE_MCI1 0xf8000000
-#define ATMEL_BASE_MCI2 0xf8004000
-#define ATMEL_BASE_SPI1 0xf8008000
-#define ATMEL_BASE_SSC1 0xf800c000
-#define ATMEL_BASE_CAN1 0xf8010000
-#define ATMEL_BASE_TC3 0xf8014000
-#define ATMEL_BASE_TSADC 0xf8018000
-#define ATMEL_BASE_TWI2 0xf801c000
-#define ATMEL_BASE_USART2 0xf8020000
-#define ATMEL_BASE_USART3 0xf8024000
-#define ATMEL_BASE_UART1 0xf8028000
-#define ATMEL_BASE_EMAC 0xf802c000
-#define ATMEL_BASE_UDPHS 0xf8030000
-#define ATMEL_BASE_SHA 0xf8034000
-#define ATMEL_BASE_AES 0xf8038000
-#define ATMEL_BASE_TDES 0xf803c000
-#define ATMEL_BASE_TRNG 0xf8040000
-/* Reserved: 0xf804400 - 0xffffc00 */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS 0xffffc000
-#define ATMEL_BASE_SMC 0xffffc000
-#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
-#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
-#define ATMEL_BASE_FUSE 0xffffe400
-#define ATMEL_BASE_DMAC0 0xffffe600
-#define ATMEL_BASE_DMAC1 0xffffe800
-#define ATMEL_BASE_MPDDRC 0xffffea00
-#define ATMEL_BASE_MATRIX 0xffffec00
-#define ATMEL_BASE_DBGU 0xffffee00
-#define ATMEL_BASE_AIC 0xfffff000
-#define ATMEL_BASE_PIOA 0xfffff200
-#define ATMEL_BASE_PIOB 0xfffff400
-#define ATMEL_BASE_PIOC 0xfffff600
-#define ATMEL_BASE_PIOD 0xfffff800
-#define ATMEL_BASE_PIOE 0xfffffa00
-#define ATMEL_BASE_PMC 0xfffffc00
-#define ATMEL_BASE_RSTC 0xfffffe00
-#define ATMEL_BASE_SHDWN 0xfffffe10
-#define ATMEL_BASE_PIT 0xfffffe30
-#define ATMEL_BASE_WDT 0xfffffe40
-#define ATMEL_BASE_SCKCR 0xfffffe50
-#define ATMEL_BASE_GPBR 0xfffffe60
-#define ATMEL_BASE_RTC 0xfffffeb0
-/* Reserved: 0xfffffee0 - 0xffffffff */
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
-#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
-#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
-#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
-#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
-#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
-#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
-#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
-#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000
-#define ATMEL_BASE_DDRCS 0x20000000
-#define ATMEL_BASE_CS1 0x40000000
-#define ATMEL_BASE_CS2 0x50000000
-#define ATMEL_BASE_CS3 0x60000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV 0x3fff
-#define CPU_HAS_PCR
-
-/*
- * PMECC table in ROM
- */
-#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
-#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
-
-/*
- * SAMA5D3 specific prototypes
- */
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_emac(void);
-unsigned int has_gmac(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on SAMA5D3 datasheet.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef SAMA5D3_SMC_H
-#define SAMA5D3_SMC_H
-
-#ifdef __ASSEMBLY__
-#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
-#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
-#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
-#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
-#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
-#else
-struct at91_cs {
- u32 setup; /* 0x600 SMC Setup Register */
- u32 pulse; /* 0x604 SMC Pulse Register */
- u32 cycle; /* 0x608 SMC Cycle Register */
- u32 timings; /* 0x60C SMC Cycle Register */
- u32 mode; /* 0x610 SMC Mode Register */
-};
-
-struct at91_smc {
- u32 reserved[384];
- struct at91_cs cs[4];
-};
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
-#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
-#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
-#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
-
-#define AT91_SMC_PULSE_NWE(x) (x & 0x3f)
-#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8)
-#define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16)
-#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24)
-
-#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
-#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
-
-#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
-#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
-#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
-#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12)
-#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
-#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
-#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
-#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31)
-
-#define AT91_SMC_MODE_RM_NCS 0x00000000
-#define AT91_SMC_MODE_RM_NRD 0x00000001
-#define AT91_SMC_MODE_WM_NCS 0x00000000
-#define AT91_SMC_MODE_WM_NWE 0x00000002
-
-#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
-#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
-#define AT91_SMC_MODE_EXNW_READY 0x00000030
-
-#define AT91_SMC_MODE_BAT 0x00000100
-#define AT91_SMC_MODE_DBW_8 0x00000000
-#define AT91_SMC_MODE_DBW_16 0x00001000
-#define AT91_SMC_MODE_DBW_32 0x00002000
-#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
-#define AT91_SMC_MODE_TDF 0x00100000
-#define AT91_SMC_MODE_PMEN 0x01000000
-#define AT91_SMC_MODE_PS_4 0x00000000
-#define AT91_SMC_MODE_PS_8 0x10000000
-#define AT91_SMC_MODE_PS_16 0x20000000
-#define AT91_SMC_MODE_PS_32 0x30000000
-
-#endif
+++ /dev/null
-/*
- * Chip-specific header file for the SAMA5D4 SoC
- *
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SAMA5D4_H
-#define __SAMA5D4_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* It's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
-#define ATMEL_ID_SYS 1 /* System Controller */
-#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
-#define ATMEL_ID_PIT 3 /* Periodic Interval Timer */
-#define ATMEL_ID_WDT 4 /* Watchdog timer */
-#define ATMEL_ID_PIOD 5 /* Parallel I/O Controller D */
-#define ATMEL_ID_USART0 6 /* USART 0 */
-#define ATMEL_ID_USART1 7 /* USART 1 */
-#define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
-#define ATMEL_ID_ICM 9 /* Integrity Check Monitor */
-#define ATMEL_ID_PKCC 10 /* Public Key Crypto Controller */
-#define ATMEL_ID_AES 12 /* Advanced Encryption Standard */
-#define ATMEL_ID_AESB 13 /* AES Bridge*/
-#define ATMEL_ID_TDES 14 /* Triple Data Encryption Standard */
-#define ATMEL_ID_SHA 15 /* SHA Signature */
-#define ATMEL_ID_MPDDRC 16 /* MPDDR controller */
-#define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */
-#define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */
-#define ATMEL_ID_VDEC 19 /* Video Decoder */
-#define ATMEL_ID_SBM 20 /* Secure Box Module */
-#define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */
-#define ATMEL_ID_PIOA 23 /* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB 24 /* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC 25 /* Parallel I/O Controller C */
-#define ATMEL_ID_PIOE 26 /* Parallel I/O Controller E */
-#define ATMEL_ID_UART0 27 /* UART 0 */
-#define ATMEL_ID_UART1 28 /* UART 1 */
-#define ATMEL_ID_USART2 29 /* USART 2 */
-#define ATMEL_ID_USART3 30 /* USART 3 */
-#define ATMEL_ID_USART4 31 /* USART 4 */
-#define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */
-#define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1 36 /* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1 38 /* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SPI2 39 /* Serial Peripheral Interface 2 */
-#define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
-#define ATMEL_ID_TC1 41 /* Timer Counter 1 (ch. 3, 4, 5) */
-#define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */
-#define ATMEL_ID_PWMC 43 /* Pulse Width Modulation Controller */
-#define ATMEL_ID_ADC 44 /* Touch Screen ADC Controller */
-#define ATMEL_ID_DBGU 45 /* Debug Unit Interrupt */
-#define ATMEL_ID_UHPHS 46 /* USB Host High Speed */
-#define ATMEL_ID_UDPHS 47 /* USB Device High Speed */
-#define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1 49 /* Synchronous Serial Controller 1 */
-#define ATMEL_ID_XDMAC1 50 /* DMA Controller 1 */
-#define ATMEL_ID_LCDC 51 /* LCD Controller */
-#define ATMEL_ID_ISI 52 /* Image Sensor Interface */
-#define ATMEL_ID_TRNG 53 /* True Random Number Generator */
-#define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
-#define ATMEL_ID_GMAC1 55 /* Ethernet MAC 1 */
-#define ATMEL_ID_IRQ 56 /* IRQ Interrupt ID */
-#define ATMEL_ID_SFC 57 /* Fuse Controller */
-#define ATMEL_ID_SECURAM 59 /* Secured RAM */
-#define ATMEL_ID_SMD 61 /* SMD Soft Modem */
-#define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */
-#define ATMEL_ID_CATB 63 /* Capacitive Touch Controller */
-#define ATMEL_ID_SFR 64 /* Special Funcion Register */
-#define ATMEL_ID_AIC 65 /* Advanced Interrupt Controller */
-#define ATMEL_ID_SAIC 66 /* Secured Advanced Interrupt Controller */
-#define ATMEL_ID_L2CC 67 /* L2 Cache Controller */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_LCDC 0xf0000000
-#define ATMEL_BASE_DMAC1 0xf0004000
-#define ATMEL_BASE_ISI 0xf0008000
-#define ATMEL_BASE_PKCC 0xf000C000
-#define ATMEL_BASE_MPDDRC 0xf0010000
-#define ATMEL_BASE_DMAC0 0xf0014000
-#define ATMEL_BASE_PMC 0xf0018000
-#define ATMEL_BASE_MATRIX0 0xf001c000
-#define ATMEL_BASE_AESB 0xf0020000
-/* Reserved: 0xf0024000 - 0xf8000000 */
-#define ATMEL_BASE_MCI0 0xf8000000
-#define ATMEL_BASE_UART0 0xf8004000
-#define ATMEL_BASE_SSC0 0xf8008000
-#define ATMEL_BASE_PWMC 0xf800c000
-#define ATMEL_BASE_SPI0 0xf8010000
-#define ATMEL_BASE_TWI0 0xf8014000
-#define ATMEL_BASE_TWI1 0xf8018000
-#define ATMEL_BASE_TC0 0xf801c000
-#define ATMEL_BASE_GMAC0 0xf8020000
-#define ATMEL_BASE_TWI2 0xf8024000
-#define ATMEL_BASE_SFR 0xf8028000
-#define ATMEL_BASE_USART0 0xf802c000
-#define ATMEL_BASE_USART1 0xf8030000
-/* Reserved: 0xf8034000 - 0xfc000000 */
-#define ATMEL_BASE_MCI1 0xfc000000
-#define ATMEL_BASE_UART1 0xfc004000
-#define ATMEL_BASE_USART2 0xfc008000
-#define ATMEL_BASE_USART3 0xfc00c000
-#define ATMEL_BASE_USART4 0xfc010000
-#define ATMEL_BASE_SSC1 0xfc014000
-#define ATMEL_BASE_SPI1 0xfc018000
-#define ATMEL_BASE_SPI2 0xfc01c000
-#define ATMEL_BASE_TC1 0xfc020000
-#define ATMEL_BASE_TC2 0xfc024000
-#define ATMEL_BASE_GMAC1 0xfc028000
-#define ATMEL_BASE_UDPHS 0xfc02c000
-#define ATMEL_BASE_TRNG 0xfc030000
-#define ATMEL_BASE_ADC 0xfc034000
-#define ATMEL_BASE_TWI3 0xfc038000
-
-#define ATMEL_BASE_MATRIX1 0xfc054000
-
-#define ATMEL_BASE_SMC 0xfc05c000
-#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
-#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
-
-#define ATMEL_BASE_PIOD 0xfc068000
-#define ATMEL_BASE_RSTC 0xfc068600
-#define ATMEL_BASE_PIT 0xfc068630
-#define ATMEL_BASE_WDT 0xfc068640
-
-#define ATMEL_BASE_DBGU 0xfc069000
-#define ATMEL_BASE_PIOA 0xfc06a000
-#define ATMEL_BASE_PIOB 0xfc06b000
-#define ATMEL_BASE_PIOC 0xfc06c000
-#define ATMEL_BASE_PIOE 0xfc06d000
-#define ATMEL_BASE_AIC 0xfc06e000
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */
-#define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */
-#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
-#define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */
-#define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */
-#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */
-#define ATMEL_BASE_AXI 0x00700000
-#define ATMEL_BASE_DAP 0x00800000
-#define ATMEL_BASE_SMD 0x00900000
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0 0x10000000
-#define ATMEL_BASE_DDRCS 0x20000000
-#define ATMEL_BASE_CS1 0x60000000
-#define ATMEL_BASE_CS2 0x70000000
-#define ATMEL_BASE_CS3 0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS 5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV 0x3fff
-#define CPU_HAS_PCR
-#define CPU_HAS_H32MXDIV
-
-/* sama5d4 series chip id definitions */
-#define ARCH_ID_SAMA5D4 0x8a5c07c0
-#define ARCH_EXID_SAMA5D41 0x00000001
-#define ARCH_EXID_SAMA5D42 0x00000002
-#define ARCH_EXID_SAMA5D43 0x00000003
-#define ARCH_EXID_SAMA5D44 0x00000004
-
-#define cpu_is_sama5d4() (get_chip_id() == ARCH_ID_SAMA5D4)
-#define cpu_is_sama5d41() (cpu_is_sama5d4() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D41))
-#define cpu_is_sama5d42() (cpu_is_sama5d4() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D42))
-#define cpu_is_sama5d43() (cpu_is_sama5d4() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D43))
-#define cpu_is_sama5d44() (cpu_is_sama5d4() && \
- (get_extension_chip_id() == ARCH_EXID_SAMA5D44))
-
-/*
- * No PMECC Galois table in ROM
- */
-#define NO_GALOIS_TABLE_IN_ROM
-
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_COMMON_H
+#define AT91_COMMON_H
+
+void at91_can_hw_init(void);
+void at91_gmac_hw_init(void);
+void at91_macb_hw_init(void);
+void at91_mci_hw_init(void);
+void at91_serial0_hw_init(void);
+void at91_serial1_hw_init(void);
+void at91_serial2_hw_init(void);
+void at91_seriald_hw_init(void);
+void at91_spi0_hw_init(unsigned long cs_mask);
+void at91_spi1_hw_init(unsigned long cs_mask);
+void at91_udp_hw_init(void);
+void at91_uhp_hw_init(void);
+void at91_lcd_hw_init(void);
+void at91_plla_init(u32 pllar);
+void at91_pllb_init(u32 pllar);
+void at91_mck_init(u32 mckr);
+void at91_pmc_init(void);
+void mem_init(void);
+void at91_phy_reset(void);
+void at91_sdram_hw_init(void);
+void at91_mck_init(u32 mckr);
+void at91_spl_board_init(void);
+void at91_disable_wdt(void);
+void matrix_init(void);
+void redirect_int_from_saic_to_aic(void);
+
+#endif /* AT91_COMMON_H */
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Debug Unit
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_DBU_H
+#define AT91_DBU_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_dbu {
+ u32 cr; /* Control Register WO */
+ u32 mr; /* Mode Register RW */
+ u32 ier; /* Interrupt Enable Register WO */
+ u32 idr; /* Interrupt Disable Register WO */
+ u32 imr; /* Interrupt Mask Register RO */
+ u32 sr; /* Status Register RO */
+ u32 rhr; /* Receive Holding Register RO */
+ u32 thr; /* Transmit Holding Register WO */
+ u32 brgr; /* Baud Rate Generator Register RW */
+ u32 res1[7];/* 0x0024 - 0x003C Reserved */
+ u32 cidr; /* Chip ID Register RO */
+ u32 exid; /* Chip ID Extension Register RO */
+ u32 fnr; /* Force NTRST Register RW */
+} at91_dbu_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_DBU_CID_ARCH_MASK 0x0ff00000
+#define AT91_DBU_CID_ARCH_9xx 0x01900000
+#define AT91_DBU_CID_ARCH_9XExx 0x02900000
+
+#define AT91_DBU_CIDR_MASK 0x1f
+#define AT91_DBU_CIDR 0x40
+#define AT91_DBU_EXID 0x44
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Enhanced Embedded Flash Controller
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_EEFC_H
+#define AT91_EEFC_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_eefc {
+ u32 fmr; /* Flash Mode Register RW */
+ u32 fcr; /* Flash Command Register WO */
+ u32 fsr; /* Flash Status Register RO */
+ u32 frr; /* Flash Result Register RO */
+} at91_eefc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_EEFC_FMR_FWS_MASK 0x00000f00
+#define AT91_EEFC_FMR_FRDY_BIT 0x00000001
+
+#define AT91_EEFC_FCR_KEY 0x5a000000
+#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00
+#define AT91_EEFC_FCR_FARG_SHIFT 8
+#define AT91_EEFC_FCR_FCMD_GETD 0x0
+#define AT91_EEFC_FCR_FCMD_WP 0x1
+#define AT91_EEFC_FCR_FCMD_WPL 0x2
+#define AT91_EEFC_FCR_FCMD_EWP 0x3
+#define AT91_EEFC_FCR_FCMD_EWPL 0x4
+#define AT91_EEFC_FCR_FCMD_EA 0x5
+#define AT91_EEFC_FCR_FCMD_SLB 0x8
+#define AT91_EEFC_FCR_FCMD_CLB 0x9
+#define AT91_EEFC_FCR_FCMD_GLB 0xA
+#define AT91_EEFC_FCR_FCMD_SGPB 0xB
+#define AT91_EEFC_FCR_FCMD_CGPB 0xC
+#define AT91_EEFC_FCR_FCMD_GGPB 0xD
+
+#define AT91_EEFC_FSR_FRDY 1
+#define AT91_EEFC_FSR_FCMDE 2
+#define AT91_EEFC_FSR_FLOCKE 4
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_H
+#define AT91_H
+
+typedef struct at91_emac {
+ u32 ctl;
+ u32 cfg;
+ u32 sr;
+ u32 tar;
+ u32 tcr;
+ u32 tsr;
+ u32 rbqp;
+ u32 reserved0;
+ u32 rsr;
+ u32 isr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 man;
+ u32 reserved1[2];
+ u32 fra;
+ u32 scol;
+ u32 mocl;
+ u32 ok;
+ u32 seqe;
+ u32 ale;
+ u32 dte;
+ u32 lcol;
+ u32 ecol;
+ u32 cse;
+ u32 tue;
+ u32 cde;
+ u32 elr;
+ u32 rjb;
+ u32 usf;
+ u32 sqee;
+ u32 drfc;
+ u32 reserved2[3];
+ u32 hsh;
+ u32 hsl;
+ u32 sa1l;
+ u32 sa1h;
+ u32 sa2l;
+ u32 sa2h;
+ u32 sa3l;
+ u32 sa3h;
+ u32 sa4l;
+ u32 sa4h;
+} at91_emac_t;
+
+#define AT91_EMAC_CTL_LB 0x0001
+#define AT91_EMAC_CTL_LBL 0x0002
+#define AT91_EMAC_CTL_RE 0x0004
+#define AT91_EMAC_CTL_TE 0x0008
+#define AT91_EMAC_CTL_MPE 0x0010
+#define AT91_EMAC_CTL_CSR 0x0020
+#define AT91_EMAC_CTL_ISR 0x0040
+#define AT91_EMAC_CTL_WES 0x0080
+#define AT91_EMAC_CTL_BP 0x1000
+
+#define AT91_EMAC_CFG_SPD 0x0001
+#define AT91_EMAC_CFG_FD 0x0002
+#define AT91_EMAC_CFG_BR 0x0004
+#define AT91_EMAC_CFG_CAF 0x0010
+#define AT91_EMAC_CFG_NBC 0x0020
+#define AT91_EMAC_CFG_MTI 0x0040
+#define AT91_EMAC_CFG_UNI 0x0080
+#define AT91_EMAC_CFG_BIG 0x0100
+#define AT91_EMAC_CFG_EAE 0x0200
+#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF
+#define AT91_EMAC_CFG_MCLK_8 0x0000
+#define AT91_EMAC_CFG_MCLK_16 0x0400
+#define AT91_EMAC_CFG_MCLK_32 0x0800
+#define AT91_EMAC_CFG_MCLK_64 0x0C00
+#define AT91_EMAC_CFG_RTY 0x1000
+#define AT91_EMAC_CFG_RMII 0x2000
+
+#define AT91_EMAC_SR_LINK 0x0001
+#define AT91_EMAC_SR_MDIO 0x0002
+#define AT91_EMAC_SR_IDLE 0x0004
+
+#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF)
+#define AT91_EMAC_TCR_NCRC 0x8000
+
+#define AT91_EMAC_TSR_OVR 0x0001
+#define AT91_EMAC_TSR_COL 0x0002
+#define AT91_EMAC_TSR_RLE 0x0004
+#define AT91_EMAC_TSR_TXIDLE 0x0008
+#define AT91_EMAC_TSR_BNQ 0x0010
+#define AT91_EMAC_TSR_COMP 0x0020
+#define AT91_EMAC_TSR_UND 0x0040
+
+#define AT91_EMAC_RSR_BNA 0x0001
+#define AT91_EMAC_RSR_REC 0x0002
+#define AT91_EMAC_RSR_OVR 0x0004
+
+/* ISR, IER, IDR, IMR use the same bits */
+#define AT91_EMAC_IxR_DONE 0x0001
+#define AT91_EMAC_IxR_RCOM 0x0002
+#define AT91_EMAC_IxR_RBNA 0x0004
+#define AT91_EMAC_IxR_TOVR 0x0008
+#define AT91_EMAC_IxR_TUND 0x0010
+#define AT91_EMAC_IxR_RTRY 0x0020
+#define AT91_EMAC_IxR_TBRE 0x0040
+#define AT91_EMAC_IxR_TCOM 0x0080
+#define AT91_EMAC_IxR_TIDLE 0x0100
+#define AT91_EMAC_IxR_LINK 0x0200
+#define AT91_EMAC_IxR_ROVR 0x0400
+#define AT91_EMAC_IxR_HRESP 0x0800
+
+#define AT91_EMAC_MAN_DATA_MASK 0xFFFF
+#define AT91_EMAC_MAN_CODE_802_3 0x00020000
+#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18)
+#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23)
+#define AT91_EMAC_MAN_RW_R 0x20000000
+#define AT91_EMAC_MAN_RW_W 0x10000000
+#define AT91_EMAC_MAN_HIGH 0x40000000
+#define AT91_EMAC_MAN_LOW 0x80000000
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * General Purpose Backup Registers
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_GPBR_H
+#define AT91_GPBR_H
+
+/*
+ * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
+ * 32 Bit registers (buffered by the Vbu power).
+ *
+ * Please consider carefully before using this resource for tasks
+ * that do not really need nonvolatile registers. Maybe you can
+ * store information in EEPROM or FLASH instead.
+ *
+ * However, if you use a GPBR please document its use here and
+ * reference the define in your code!
+ *
+ * known typical uses of the GPBRs:
+ * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
+ * GPBR[1]: unused
+ * GPBR[2]: unused
+ * GPBR[3]: bootcount (u-boot)
+ */
+#define AT91_GPBR_INDEX_TIMEOFF 0
+#define AT91_GPBR_INDEX_BOOTCOUNT 3
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_gpbr {
+ u32 reg[4];
+} at91_gpbr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_MATRIX_H
+#define AT91_MATRIX_H
+
+#ifdef __ASSEMBLY__
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
+#else
+#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
+#endif
+
+#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
+
+#else
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_MATRIX_MASTERS 6
+#define AT91_MATRIX_SLAVES 5
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_MASTERS 1
+#define AT91_MATRIX_SLAVES 5
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_MASTERS 9
+#define AT91_MATRIX_SLAVES 7
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MASTERS 11
+#define AT91_MATRIX_SLAVES 8
+#else
+#error CPU not supported. Please update at91_matrix.h
+#endif
+
+typedef struct at91_priority {
+ u32 a;
+ u32 b;
+} at91_priority_t;
+
+typedef struct at91_matrix {
+ u32 mcfg[AT91_MATRIX_MASTERS];
+#if defined(CONFIG_AT91SAM9261)
+ u32 scfg[AT91_MATRIX_SLAVES];
+ u32 res61_1[3];
+ u32 tcr;
+ u32 res61_2[2];
+ u32 csa;
+ u32 pucr;
+ u32 res61_3[114];
+#else
+ u32 reserve1[16 - AT91_MATRIX_MASTERS];
+ u32 scfg[AT91_MATRIX_SLAVES];
+ u32 reserve2[16 - AT91_MATRIX_SLAVES];
+ at91_priority_t pr[AT91_MATRIX_SLAVES];
+ u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
+ u32 mrcr; /* 0x100 Master Remap Control */
+ u32 reserve4[3];
+#if defined(CONFIG_AT91SAM9G45)
+ u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
+ u32 womr; /* 0x1E4 Write Protect Mode */
+ u32 wpsr; /* 0x1E8 Write Protect Status */
+ u32 resg45_1[10];
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+ u32 res60_1[3];
+ u32 csa;
+ u32 res60_2[56];
+#elif defined(CONFIG_AT91SAM9263)
+ u32 res63_1;
+ u32 tcmr;
+ u32 res63_2[2];
+ u32 csa[2];
+ u32 res63_3[54];
+#else
+ u32 reserve5[60];
+#endif
+#endif
+} at91_matrix_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_CSA_DBPUC 0x00000100
+#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
+#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
+
+#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
+#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
+#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
+#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
+
+#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
+
+#if defined CONFIG_AT91SAM9261
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_MCFG_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_MCFG_RCB1 (1 << 1)
+#endif
+
+/* Undefined Length Burst Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
+#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
+#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
+#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
+#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
+#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
+#define AT91_MATRIX_MCFG_ULBT_128 0x00000007
+#endif
+
+/* Default Master Type */
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
+
+/* Fixed Index of Default Master */
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
+#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
+#endif
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
+ defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
+#endif
+
+/* Arbitration Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
+#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
+#endif
+
+/* Master Remap Control Register */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_MRCR_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_MRCR_RCB1 (1 << 1)
+#endif
+#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MRCR_RCB2 0x00000004
+#define AT91_MATRIX_MRCR_RCB3 0x00000008
+#define AT91_MATRIX_MRCR_RCB4 0x00000010
+#define AT91_MATRIX_MRCR_RCB5 0x00000020
+#define AT91_MATRIX_MRCR_RCB6 0x00000040
+#define AT91_MATRIX_MRCR_RCB7 0x00000080
+#define AT91_MATRIX_MRCR_RCB8 0x00000100
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MRCR_RCB9 0x00000200
+#define AT91_MATRIX_MRCR_RCB10 0x00000400
+#define AT91_MATRIX_MRCR_RCB11 0x00000800
+#endif
+
+/* TCM Configuration Register */
+#if defined(CONFIG_AT91SAM9G45)
+/* Size of ITCM enabled memory block */
+#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
+#define AT91_MATRIX_TCMR_ITCM_32 0x00000040
+/* Size of DTCM enabled memory block */
+#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
+#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
+#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
+/* Wait state TCM register */
+#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
+#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
+#endif
+#if defined(CONFIG_AT91SAM9263)
+/* Size of ITCM enabled memory block */
+#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
+#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
+#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
+/* Size of DTCM enabled memory block */
+#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
+#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
+#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
+#endif
+#if defined(CONFIG_AT91SAM9261)
+/* Size of ITCM enabled memory block */
+#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
+#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
+#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
+#define AT91_MATRIX_TCMR_ITCM_64 0x00000007
+/* Size of DTCM enabled memory block */
+#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
+#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
+#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
+#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
+#endif
+
+#if defined(CONFIG_AT91SAM9G45)
+/* Video Mode Configuration Register */
+#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
+#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
+/* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
+#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
+#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
+/* Write Protect Status Register */
+#define AT91_MATRIX_WPSR_NO_WPV 0x00000000
+#define AT91_MATRIX_WPSR_WPV 0x00000001
+#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
+#endif
+
+/* USB Pad Pull-Up Control Register */
+#if defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_USBPUCR_PUON 0x40000000
+#endif
+
+#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
+#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
+#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
+#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_MC_H
+#define AT91_MC_H
+
+#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60)
+#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64)
+#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70)
+#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90)
+#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94)
+#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_ebi {
+ u32 csa; /* 0x00 Chip Select Assignment Register */
+ u32 cfgr; /* 0x04 Configuration Register */
+ u32 reserved[2];
+} at91_ebi_t;
+
+#define AT91_EBI_CSA_CS0A 0x0001
+#define AT91_EBI_CSA_CS1A 0x0002
+
+#define AT91_EBI_CSA_CS3A 0x0008
+#define AT91_EBI_CSA_CS4A 0x0010
+
+typedef struct at91_sdramc {
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
+ u32 cr; /* 0x08 SDRAMC Configuration Register */
+ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
+ u32 lpr; /* 0x10 SDRAMC Low Power Register */
+ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
+ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
+ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
+ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
+ u32 reserved[3];
+} at91_sdramc_t;
+
+typedef struct at91_smc {
+ u32 csr[8]; /* 0x00 SDRAMC Mode Register */
+} at91_smc_t;
+
+#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
+#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
+#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
+#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
+#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
+#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
+#define AT91_SMC_CSR_DRP 0x00008000
+#define AT91_SMC_CSR_DBW_8 0x00004000
+#define AT91_SMC_CSR_DBW_16 0x00002000
+#define AT91_SMC_CSR_BAT_8 0x00000000
+#define AT91_SMC_CSR_BAT_16 0x00001000
+#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
+#define AT91_SMC_CSR_WSEN 0x00000080
+#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
+
+typedef struct at91_bfc {
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+} at91_bfc_t;
+
+typedef struct at91_mc {
+ u32 rcr; /* 0x00 MC Remap Control Register */
+ u32 asr; /* 0x04 MC Abort Status Register */
+ u32 aasr; /* 0x08 MC Abort Address Status Reg */
+ u32 mpr; /* 0x0C MC Master Priority Register */
+ u32 reserved1[20]; /* 0x10-0x5C */
+ at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
+ at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
+ at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
+ at91_bfc_t bfc; /* 0xC0 BFC User Interface */
+ u32 reserved2[15];
+} at91_mc_t;
+
+#endif
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
+
+typedef struct at91_pdc {
+ u32 rpr; /* 0x100 Receive Pointer Register */
+ u32 rcr; /* 0x104 Receive Counter Register */
+ u32 tpr; /* 0x108 Transmit Pointer Register */
+ u32 tcr; /* 0x10C Transmit Counter Register */
+ u32 pnpr; /* 0x110 Receive Next Pointer Register */
+ u32 pncr; /* 0x114 Receive Next Counter Register */
+ u32 tnpr; /* 0x118 Transmit Next Pointer Register */
+ u32 tncr; /* 0x11C Transmit Next Counter Register */
+ u32 ptcr; /* 0x120 Transfer Control Register */
+ u32 ptsr; /* 0x124 Transfer Status Register */
+} at91_pdc_t;
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+
+#define AT91_ASM_PIO_RANGE 0x200
+#define AT91_ASM_PIOC_ASR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
+#define AT91_ASM_PIOC_BSR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
+#define AT91_ASM_PIOC_PDR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOC_PUDR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
+
+#define AT91_ASM_PIOD_PDR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOD_PUDR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
+#define AT91_ASM_PIOD_ASR \
+ (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_port {
+ u32 per; /* 0x00 PIO Enable Register */
+ u32 pdr; /* 0x04 PIO Disable Register */
+ u32 psr; /* 0x08 PIO Status Register */
+ u32 reserved0;
+ u32 oer; /* 0x10 Output Enable Register */
+ u32 odr; /* 0x14 Output Disable Registerr */
+ u32 osr; /* 0x18 Output Status Register */
+ u32 reserved1;
+ u32 ifer; /* 0x20 Input Filter Enable Register */
+ u32 ifdr; /* 0x24 Input Filter Disable Register */
+ u32 ifsr; /* 0x28 Input Filter Status Register */
+ u32 reserved2;
+ u32 sodr; /* 0x30 Set Output Data Register */
+ u32 codr; /* 0x34 Clear Output Data Register */
+ u32 odsr; /* 0x38 Output Data Status Register */
+ u32 pdsr; /* 0x3C Pin Data Status Register */
+ u32 ier; /* 0x40 Interrupt Enable Register */
+ u32 idr; /* 0x44 Interrupt Disable Register */
+ u32 imr; /* 0x48 Interrupt Mask Register */
+ u32 isr; /* 0x4C Interrupt Status Register */
+ u32 mder; /* 0x50 Multi-driver Enable Register */
+ u32 mddr; /* 0x54 Multi-driver Disable Register */
+ u32 mdsr; /* 0x58 Multi-driver Status Register */
+ u32 reserved3;
+ u32 pudr; /* 0x60 Pull-up Disable Register */
+ u32 puer; /* 0x64 Pull-up Enable Register */
+ u32 pusr; /* 0x68 Pad Pull-up Status Register */
+ u32 reserved4;
+#if defined(CPU_HAS_PIO3)
+ u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6; /* */
+#else
+ u32 asr; /* 0x70 Select A Register */
+ u32 bsr; /* 0x74 Select B Register */
+ u32 absr; /* 0x78 AB Select Status Register */
+ u32 reserved5[9]; /* */
+#endif
+ u32 ower; /* 0xA0 Output Write Enable Register */
+ u32 owdr; /* 0xA4 Output Write Disable Register */
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
+ u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
+ u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr; /* 0xC0 Edge Select Register */
+ u32 lsr; /* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
+ u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr; /* 0xE0 Lock Status */
+ u32 wpmr; /* 0xE4 Write Protect Mode Register */
+ u32 wpsr; /* 0xE8 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt; /* 0x100 Schmitt Trigger Register */
+ u32 reserved12[63];
+#else
+ u32 reserved6[85];
+#endif
+} at91_port_t;
+
+typedef union at91_pio {
+ struct {
+ at91_port_t pioa;
+ at91_port_t piob;
+ at91_port_t pioc;
+ at91_port_t piod; /* not present in all hardware */
+ at91_port_t pioe;/* not present in all hardware */
+ };
+ at91_port_t port[5];
+} at91_pio_t;
+
+#ifdef CONFIG_AT91_GPIO
+int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
+int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_output(unsigned port, unsigned pin, int value);
+int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_value(unsigned port, unsigned pin, int value);
+int at91_get_pio_value(unsigned port, unsigned pin);
+#endif
+#endif
+
+#define AT91_PIO_PORTA 0x0
+#define AT91_PIO_PORTB 0x1
+#define AT91_PIO_PORTC 0x2
+#define AT91_PIO_PORTD 0x3
+#define AT91_PIO_PORTE 0x4
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+typedef struct at91_pit {
+ u32 mr; /* 0x00 Mode Register */
+ u32 sr; /* 0x04 Status Register */
+ u32 pivr; /* 0x08 Periodic Interval Value Register */
+ u32 piir; /* 0x0C Periodic Interval Image Register */
+} at91_pit_t;
+
+#define AT91_PIT_MR_IEN 0x02000000
+#define AT91_PIT_MR_EN 0x01000000
+#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
+#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#ifdef __ASSEMBLY__
+
+#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
+#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
+#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
+#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
+#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
+
+#else
+
+#include <asm/types.h>
+
+typedef struct at91_pmc {
+ u32 scer; /* 0x00 System Clock Enable Register */
+ u32 scdr; /* 0x04 System Clock Disable Register */
+ u32 scsr; /* 0x08 System Clock Status Register */
+ u32 reserved0;
+ u32 pcer; /* 0x10 Peripheral Clock Enable Register */
+ u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
+ u32 pcsr; /* 0x18 Peripheral Clock Status Register */
+ u32 uckr; /* 0x1C UTMI Clock Register */
+ u32 mor; /* 0x20 Main Oscilator Register */
+ u32 mcfr; /* 0x24 Main Clock Frequency Register */
+ u32 pllar; /* 0x28 PLL A Register */
+ u32 pllbr; /* 0x2C PLL B Register */
+ u32 mckr; /* 0x30 Master Clock Register */
+ u32 reserved1;
+ u32 usb; /* 0x38 USB Clock Register */
+ u32 reserved2;
+ u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
+ u32 reserved3[4];
+ u32 ier; /* 0x60 Interrupt Enable Register */
+ u32 idr; /* 0x64 Interrupt Disable Register */
+ u32 sr; /* 0x68 Status Register */
+ u32 imr; /* 0x6C Interrupt Mask Register */
+ u32 reserved4[4];
+ u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
+ u32 reserved5[21];
+ u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
+ u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CPU_HAS_PCR
+ u32 reserved6[8];
+ u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
+ u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
+ u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
+ u32 pcr; /* 0x10c Periperial Control Register */
+ u32 ocr; /* 0x110 Oscillator Calibration Register */
+#else
+ u32 reserved8[5];
+#endif
+} at91_pmc_t;
+
+#endif /* end not assembly */
+
+#define AT91_PMC_MOR_MOSCEN 0x01
+#define AT91_PMC_MOR_OSCBYPASS 0x02
+#define AT91_PMC_MOR_MOSCRCEN 0x08
+#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16)
+#define AT91_PMC_MOR_MOSCSEL (1 << 24)
+
+#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
+#else
+#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
+#endif
+#define AT91_PMC_PLLAR_29 0x20000000
+#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
+#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
+#define AT91_PMC_PLLBR_USBDIV_4 0x20000000
+
+#define AT91_PMC_MCFR_MAINRDY 0x00010000
+#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
+
+#define AT91_PMC_MCKR_CSS_SLOW 0x00000000
+#define AT91_PMC_MCKR_CSS_MAIN 0x00000001
+#define AT91_PMC_MCKR_CSS_PLLA 0x00000002
+#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
+#define AT91_PMC_MCKR_CSS_MASK 0x00000003
+
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#define AT91_PMC_MCKR_PRES_1 0x00000000
+#define AT91_PMC_MCKR_PRES_2 0x00000010
+#define AT91_PMC_MCKR_PRES_4 0x00000020
+#define AT91_PMC_MCKR_PRES_8 0x00000030
+#define AT91_PMC_MCKR_PRES_16 0x00000040
+#define AT91_PMC_MCKR_PRES_32 0x00000050
+#define AT91_PMC_MCKR_PRES_64 0x00000060
+#define AT91_PMC_MCKR_PRES_MASK 0x00000070
+#else
+#define AT91_PMC_MCKR_PRES_1 0x00000000
+#define AT91_PMC_MCKR_PRES_2 0x00000004
+#define AT91_PMC_MCKR_PRES_4 0x00000008
+#define AT91_PMC_MCKR_PRES_8 0x0000000C
+#define AT91_PMC_MCKR_PRES_16 0x00000010
+#define AT91_PMC_MCKR_PRES_32 0x00000014
+#define AT91_PMC_MCKR_PRES_64 0x00000018
+#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
+#endif
+
+#ifdef CONFIG_AT91RM9200
+#define AT91_PMC_MCKR_MDIV_1 0x00000000
+#define AT91_PMC_MCKR_MDIV_2 0x00000100
+#define AT91_PMC_MCKR_MDIV_3 0x00000200
+#define AT91_PMC_MCKR_MDIV_4 0x00000300
+#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
+#else
+#define AT91_PMC_MCKR_MDIV_1 0x00000000
+#define AT91_PMC_MCKR_MDIV_2 0x00000100
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#define AT91_PMC_MCKR_MDIV_3 0x00000300
+#endif
+#define AT91_PMC_MCKR_MDIV_4 0x00000200
+#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
+#endif
+
+#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000
+#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
+#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
+
+#define AT91_PMC_MCKR_H32MXDIV 0x01000000
+
+#define AT91_PMC_IXR_MOSCS 0x00000001
+#define AT91_PMC_IXR_LOCKA 0x00000002
+#define AT91_PMC_IXR_LOCKB 0x00000004
+#define AT91_PMC_IXR_MCKRDY 0x00000008
+#define AT91_PMC_IXR_LOCKU 0x00000040
+#define AT91_PMC_IXR_PCKRDY0 0x00000100
+#define AT91_PMC_IXR_PCKRDY1 0x00000200
+#define AT91_PMC_IXR_PCKRDY2 0x00000400
+#define AT91_PMC_IXR_PCKRDY3 0x00000800
+#define AT91_PMC_IXR_MOSCSELS 0x00010000
+
+#define AT91_PMC_PCR_PID_MASK (0x3f)
+#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
+#define AT91_PMC_PCR_EN (0x1 << 28)
+
+#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
+#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
+#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
+#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
+#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
+#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
+#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
+#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
+#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
+#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
+#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
+#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
+#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
+
+#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
+#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
+#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
+
+#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
+#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
+
+#define AT91_PMC_DIV (0xff << 0) /* Divider */
+#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
+#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
+#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
+#define AT91_PMC_USBDIV_1 (0 << 28)
+#define AT91_PMC_USBDIV_2 (1 << 28)
+#define AT91_PMC_USBDIV_4 (2 << 28)
+#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
+#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
+
+#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
+#define AT91_PMC_CSS_SLOW (0 << 0)
+#define AT91_PMC_CSS_MAIN (1 << 0)
+#define AT91_PMC_CSS_PLLA (2 << 0)
+#define AT91_PMC_CSS_PLLB (3 << 0)
+#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
+#define AT91_PMC_PRES_1 (0 << 2)
+#define AT91_PMC_PRES_2 (1 << 2)
+#define AT91_PMC_PRES_4 (2 << 2)
+#define AT91_PMC_PRES_8 (3 << 2)
+#define AT91_PMC_PRES_16 (4 << 2)
+#define AT91_PMC_PRES_32 (5 << 2)
+#define AT91_PMC_PRES_64 (6 << 2)
+#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
+#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
+#define AT91RM9200_PMC_MDIV_2 (1 << 8)
+#define AT91RM9200_PMC_MDIV_3 (2 << 8)
+#define AT91RM9200_PMC_MDIV_4 (3 << 8)
+#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
+#define AT91SAM9_PMC_MDIV_2 (1 << 8)
+#define AT91SAM9_PMC_MDIV_4 (2 << 8)
+#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
+#define AT91SAM9_PMC_MDIV_6 (3 << 8)
+#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
+#define AT91_PMC_PDIV_1 (0 << 12)
+#define AT91_PMC_PDIV_2 (1 << 12)
+
+#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
+#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
+#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
+#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
+#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
+
+#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
+#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
+#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
+#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
+#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
+#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
+#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
+#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
+#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+
+#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+/* Reset Controller Status Register */
+#define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04)
+#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rstc {
+ u32 cr; /* Reset Controller Control Register */
+ u32 sr; /* Reset Controller Status Register */
+ u32 mr; /* Reset Controller Mode Register */
+} at91_rstc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RSTC_KEY 0xA5000000
+
+#define AT91_RSTC_CR_PROCRST 0x00000001
+#define AT91_RSTC_CR_PERRST 0x00000004
+#define AT91_RSTC_CR_EXTRST 0x00000008
+
+#define AT91_RSTC_MR_URSTEN 0x00000001
+#define AT91_RSTC_MR_URSTIEN 0x00000010
+#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8)
+#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00
+
+#define AT91_RSTC_SR_NRSTL 0x00010000
+
+#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
+#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
+#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
+#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
+#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
+#define AT91_RSTC_RSTTYP_USER (4 << 8)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Real-time Timer
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rtt {
+ u32 mr; /* Mode Register RW 0x00008000 */
+ u32 ar; /* Alarm Register RW 0xFFFFFFFF */
+ u32 vr; /* Value Register RO 0x00000000 */
+ u32 sr; /* Status Register RO 0x00000000 */
+} at91_rtt_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RTT_MR_RTPRES 0x0000ffff
+#define AT91_RTT_MR_ALMIEN 0x00010000
+#define AT91_RTT_RTTINCIEN 0x00020000
+#define AT91_RTT_RTTRST 0x00040000
+
+#define AT91_RTT_SR_ALMS 0x00000001
+#define AT91_RTT_SR_RTTINC 0x00000002
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
+
+#include <asm/arch/at91_pdc.h>
+
+typedef struct at91_spi {
+ u32 cr; /* 0x00 Control Register */
+ u32 mr; /* 0x04 Mode Register */
+ u32 rdr; /* 0x08 Receive Data Register */
+ u32 tdr; /* 0x0C Transmit Data Register */
+ u32 sr; /* 0x10 Status Register */
+ u32 ier; /* 0x14 Interrupt Enable Register */
+ u32 idr; /* 0x18 Interrupt Disable Register */
+ u32 imr; /* 0x1C Interrupt Mask Register */
+ u32 reserve1[4];
+ u32 csr[4]; /* 0x30 Chip Select Register 0-3 */
+ u32 reserve2[48];
+ at91_pdc_t pdc;
+} at91_spi_t;
+
+#ifdef CONFIG_ATMEL_LEGACY
+
+#define AT91_SPI_CR 0x00 /* Control Register */
+#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
+#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
+#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
+#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_MR 0x04 /* Mode Register */
+#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
+#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
+#define AT91_SPI_PS_FIXED (0 << 1)
+#define AT91_SPI_PS_VARIABLE (1 << 1)
+#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
+#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
+#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
+#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
+
+#define AT91_SPI_RDR 0x08 /* Receive Data Register */
+#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+
+#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
+#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_SR 0x10 /* Status Register */
+#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
+#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
+#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
+#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
+#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
+#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
+#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
+#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
+#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
+#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
+#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
+
+#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
+#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
+#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
+
+#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
+#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
+#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
+#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
+#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
+#define AT91_SPI_BITS_8 (0 << 4)
+#define AT91_SPI_BITS_9 (1 << 4)
+#define AT91_SPI_BITS_10 (2 << 4)
+#define AT91_SPI_BITS_11 (3 << 4)
+#define AT91_SPI_BITS_12 (4 << 4)
+#define AT91_SPI_BITS_13 (5 << 4)
+#define AT91_SPI_BITS_14 (6 << 4)
+#define AT91_SPI_BITS_15 (7 << 4)
+#define AT91_SPI_BITS_16 (8 << 4)
+#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
+#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
+#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
+
+#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
+
+#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
+
+#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
+
+#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
+
+#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
+
+#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
+
+#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
+
+#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
+
+#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
+#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
+#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
+#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
+#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
+
+#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
+
+#endif /* CONFIG_ATMEL_LEGACY */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+typedef struct at91_st {
+
+ u32 cr;
+ u32 pimr;
+ u32 wdmr;
+ u32 rtmr;
+ u32 sr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 rtar;
+ u32 crtr;
+} at91_st_t ;
+
+#define AT91_ST_CR_WDRST 1
+
+#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
+#define AT91_ST_WDMR_RSTEN 0x00010000
+#define AT91_ST_WDMR_EXTEN 0x00020000
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_TC_H
+#define AT91_TC_H
+
+typedef struct at91_tcc {
+ u32 ccr; /* 0x00 Channel Control Register */
+ u32 cmr; /* 0x04 Channel Mode Register */
+ u32 reserved1[2];
+ u32 cv; /* 0x10 Counter Value */
+ u32 ra; /* 0x14 Register A */
+ u32 rb; /* 0x18 Register B */
+ u32 rc; /* 0x1C Register C */
+ u32 sr; /* 0x20 Status Register */
+ u32 ier; /* 0x24 Interrupt Enable Register */
+ u32 idr; /* 0x28 Interrupt Disable Register */
+ u32 imr; /* 0x2C Interrupt Mask Register */
+ u32 reserved3[4];
+} at91_tcc_t;
+
+#define AT91_TC_CCR_CLKEN 0x00000001
+#define AT91_TC_CCR_CLKDIS 0x00000002
+#define AT91_TC_CCR_SWTRG 0x00000004
+
+#define AT91_TC_CMR_CPCTRG 0x00004000
+
+#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
+#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
+#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
+#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
+#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
+#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
+#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
+#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
+
+typedef struct at91_tc {
+ at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
+ u32 bcr; /* 0xC0 TC Block Control Register */
+ u32 bmr; /* 0xC4 TC Block Mode Register */
+} at91_tc_t;
+
+#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
+#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
+#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
+#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
+
+#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
+#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
+#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
+#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
+
+#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
+#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
+#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
+#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
+ *
+ * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#ifdef __ASSEMBLY__
+
+#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
+
+#else
+
+typedef struct at91_wdt {
+ u32 cr;
+ u32 mr;
+ u32 sr;
+} at91_wdt_t;
+
+#endif
+
+#define AT91_WDT_CR_WDRSTT 1
+#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
+
+#define AT91_WDT_MR_WDV(x) (x & 0xfff)
+#define AT91_WDT_MR_WDFIEN 0x00001000
+#define AT91_WDT_MR_WDRSTEN 0x00002000
+#define AT91_WDT_MR_WDRPROC 0x00004000
+#define AT91_WDT_MR_WDDIS 0x00008000
+#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16)
+#define AT91_WDT_MR_WDDBGHLT 0x10000000
+#define AT91_WDT_MR_WDIDLEHLT 0x20000000
+
+#endif
--- /dev/null
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AT91RM9200_H__
+#define __AT91RM9200_H__
+
+#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
+#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
+#define CONFIG_AT91_GPIO /* and require always gpio features */
+
+/* Periperial Identifiers */
+
+#define ATMEL_ID_SYS 1 /* System Peripheral */
+#define ATMEL_ID_PIOA 2 /* PIO port A */
+#define ATMEL_ID_PIOB 3 /* PIO port B */
+#define ATMEL_ID_PIOC 4 /* PIO port C */
+#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_USART2 8 /* USART 2 */
+#define ATMEL_ID_USART3 9 /* USART 3 */
+#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
+#define ATMEL_ID_UDP 11 /* USB Device Port */
+#define ATMEL_ID_TWI 12 /* Two Wire Interface */
+#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
+#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */
+#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */
+#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
+#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
+#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
+#define ATMEL_ID_TC3 20 /* Timer Counter 3 */
+#define ATMEL_ID_TC4 21 /* Timer Counter 4 */
+#define ATMEL_ID_TC5 22 /* Timer Counter 5 */
+#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */
+#define ATMEL_ID_EMAC 24 /* Ethernet MAC */
+#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */
+
+#define ATMEL_USB_HOST_BASE 0x00300000
+
+#define ATMEL_BASE_TC 0xFFFA0000
+#define ATMEL_BASE_UDP 0xFFFB0000
+#define ATMEL_BASE_MCI 0xFFFB4000
+#define ATMEL_BASE_TWI 0xFFFB8000
+#define ATMEL_BASE_EMAC 0xFFFBC000
+#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
+#define ATMEL_BASE_USART0 ATMEL_BASE_USART
+#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000)
+#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000)
+#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000)
+
+#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */
+#define ATMEL_BASE_SPI 0xFFFE0000
+
+#define ATMEL_BASE_AIC 0xFFFFF000
+#define ATMEL_BASE_DBGU 0xFFFFF200
+#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */
+#define ATMEL_BASE_PIOA 0xFFFFF400
+#define ATMEL_BASE_PIOB 0xFFFFF600
+#define ATMEL_BASE_PIOC 0xFFFFF800
+#define ATMEL_BASE_PIOD 0xFFFFFA00
+#define ATMEL_BASE_PMC 0xFFFFFC00
+#define ATMEL_BASE_ST 0xFFFFFD00
+#define ATMEL_BASE_RTC 0xFFFFFE00
+#define ATMEL_BASE_MC 0xFFFFFF00
+
+#define AT91_PIO_BASE ATMEL_BASE_PIO
+
+/* AT91RM9200 Periperial Multiplexing A */
+/* Port A */
+#define ATMEL_PMX_AA_EREFCK 0x00000080
+#define ATMEL_PMX_AA_ETXCK 0x00000080
+#define ATMEL_PMX_AA_ETXEN 0x00000100
+#define ATMEL_PMX_AA_ETX0 0x00000200
+#define ATMEL_PMX_AA_ETX1 0x00000400
+#define ATMEL_PMX_AA_ECRS 0x00000800
+#define ATMEL_PMX_AA_ECRSDV 0x00000800
+#define ATMEL_PMX_AA_ERX0 0x00001000
+#define ATMEL_PMX_AA_ERX1 0x00002000
+#define ATMEL_PMX_AA_ERXER 0x00004000
+#define ATMEL_PMX_AA_EMDC 0x00008000
+#define ATMEL_PMX_AA_EMDIO 0x00010000
+
+#define ATMEL_PMX_AA_TXD2 0x00800000
+
+#define ATMEL_PMX_AA_TWD 0x02000000
+#define ATMEL_PMX_AA_TWCK 0x04000000
+
+/* Port B */
+#define ATMEL_PMX_BA_ERXCK 0x00080000
+#define ATMEL_PMX_BA_ECOL 0x00040000
+#define ATMEL_PMX_BA_ERXDV 0x00020000
+#define ATMEL_PMX_BA_ERX3 0x00010000
+#define ATMEL_PMX_BA_ERX2 0x00008000
+#define ATMEL_PMX_BA_ETXER 0x00004000
+#define ATMEL_PMX_BA_ETX3 0x00002000
+#define ATMEL_PMX_BA_ETX2 0x00001000
+
+/* Port B */
+
+#define ATMEL_PMX_CA_BFCK 0x00000001
+#define ATMEL_PMX_CA_BFRDY 0x00000002
+#define ATMEL_PMX_CA_SMOE 0x00000002
+#define ATMEL_PMX_CA_BFAVD 0x00000004
+#define ATMEL_PMX_CA_BFBAA 0x00000008
+#define ATMEL_PMX_CA_SMWE 0x00000008
+#define ATMEL_PMX_CA_BFOE 0x00000010
+#define ATMEL_PMX_CA_BFWE 0x00000020
+#define ATMEL_PMX_CA_NWAIT 0x00000040
+#define ATMEL_PMX_CA_A23 0x00000080
+#define ATMEL_PMX_CA_A24 0x00000100
+#define ATMEL_PMX_CA_A25 0x00000200
+#define ATMEL_PMX_CA_CFRNW 0x00000200
+#define ATMEL_PMX_CA_NCS4 0x00000400
+#define ATMEL_PMX_CA_CFCS 0x00000400
+#define ATMEL_PMX_CA_NCS5 0x00000800
+#define ATMEL_PMX_CA_CFCE1 0x00001000
+#define ATMEL_PMX_CA_NCS6 0x00001000
+#define ATMEL_PMX_CA_CFCE2 0x00002000
+#define ATMEL_PMX_CA_NCS7 0x00002000
+#define ATMEL_PMX_CA_D16_31 0xFFFF0000
+
+#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
+#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
+
+#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
+ *
+ * (C) 2006 Andrew Victor
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoCs:
+ * AT91SAM9260, AT91SAM9G20, AT91SAM9XE
+ *
+ * Note that those SoCs are mostly software and pin compatible,
+ * therefore this file applies to all of them. Differences between
+ * those SoCs are concentrated at the end of this file.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9260_H
+#define AT91SAM9260_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Peripherals */
+#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
+#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
+#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
+#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_USART2 8 /* USART 2 */
+#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
+#define ATMEL_ID_UDP 10 /* USB Device Port */
+#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
+#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+/* Reserved: 15 */
+/* Reserved: 16 */
+#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
+#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
+#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
+#define ATMEL_ID_UHP 20 /* USB Host port */
+#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
+#define ATMEL_ID_ISI 22 /* Image Sensor Interface */
+#define ATMEL_ID_USART3 23 /* USART 3 */
+#define ATMEL_ID_USART4 24 /* USART 4 */
+/* USART5 or TWI1: 25 */
+#define ATMEL_ID_TC3 26 /* Timer Counter 3 */
+#define ATMEL_ID_TC4 27 /* Timer Counter 4 */
+#define ATMEL_ID_TC5 28 /* Timer Counter 5 */
+#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_TCB0 0xfffa0000
+#define ATMEL_BASE_TC0 0xfffa0000
+#define ATMEL_BASE_TC1 0xfffa0040
+#define ATMEL_BASE_TC2 0xfffa0080
+#define ATMEL_BASE_UDP0 0xfffa4000
+#define ATMEL_BASE_MCI 0xfffa8000
+#define ATMEL_BASE_TWI0 0xfffac000
+#define ATMEL_BASE_USART0 0xfffb0000
+#define ATMEL_BASE_USART1 0xfffb4000
+#define ATMEL_BASE_USART2 0xfffb8000
+#define ATMEL_BASE_SSC0 0xfffbc000
+#define ATMEL_BASE_ISI0 0xfffc0000
+#define ATMEL_BASE_EMAC0 0xfffc4000
+#define ATMEL_BASE_SPI0 0xfffc8000
+#define ATMEL_BASE_SPI1 0xfffcc000
+#define ATMEL_BASE_USART3 0xfffd0000
+#define ATMEL_BASE_USART4 0xfffd4000
+/* USART5 or TWI1: 0xfffd8000 */
+#define ATMEL_BASE_TCB1 0xfffdc000
+#define ATMEL_BASE_TC3 0xfffdc000
+#define ATMEL_BASE_TC4 0xfffdc040
+#define ATMEL_BASE_TC5 0xfffdc080
+#define ATMEL_BASE_ADC 0xfffe0000
+/* Reserved: 0xfffe4000 - 0xffffe7ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS 0xffffe800
+#define ATMEL_BASE_SDRAMC 0xffffea00
+#define ATMEL_BASE_SMC 0xffffec00
+#define ATMEL_BASE_MATRIX 0xffffee00
+#define ATMEL_BASE_CCFG 0xffffef14
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_DBGU 0xfffff200
+#define ATMEL_BASE_PIOA 0xfffff400
+#define ATMEL_BASE_PIOB 0xfffff600
+#define ATMEL_BASE_PIOC 0xfffff800
+/* EEFC: 0xfffffa00 */
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWN 0xfffffd10
+#define ATMEL_BASE_RTT 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+/* GPBR(non-XE SoCs): 0xfffffd50 */
+/* GPBR(XE SoCs): 0xfffffd60 */
+/* Reserved: 0xfffffd70 - 0xffffffff */
+
+/*
+ * Internal Memory common on all these SoCs
+ */
+#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */
+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
+/* SRAM or FLASH: 0x00200000 */
+/* SRAM: 0x00300000 */
+/* Reserved: 0x00400000 */
+#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
+#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+#define ATMEL_BASE_CS6 0x70000000
+#define ATMEL_BASE_CS7 0x80000000
+
+/*
+ * Other misc defines
+ */
+#ifndef CONFIG_DM_GPIO
+#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#endif
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+
+/*
+ * SoC specific defines
+ */
+#if defined(CONFIG_AT91SAM9XE)
+# define ATMEL_CPU_NAME "AT91SAM9XE"
+# define ATMEL_ID_TWI1 25 /* TWI 1 */
+# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */
+# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */
+# define ATMEL_BASE_TWI1 0xfffd8000
+# define ATMEL_BASE_EEFC 0xfffffa00
+# define ATMEL_BASE_GPBR 0xfffffd60
+#elif defined(CONFIG_AT91SAM9260)
+# define ATMEL_CPU_NAME "AT91SAM9260"
+# define ATMEL_ID_USART5 25 /* USART 5 */
+# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
+# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
+# define ATMEL_BASE_USART5 0xfffd8000
+# define ATMEL_BASE_GPBR 0xfffffd50
+#elif defined(CONFIG_AT91SAM9G20)
+# define ATMEL_CPU_NAME "AT91SAM9G20"
+# define ATMEL_ID_USART5 25 /* USART 5 */
+# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
+# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
+# define ATMEL_BASE_USART5 0xfffd8000
+# define ATMEL_BASE_GPBR 0xfffffd50
+#endif
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * However, on the AT91SAM9260/9G20/9XE there exist only
+ * 6 Masters and 5 Slaves!
+ */
+struct at91_matrix {
+ u32 mcfg[16]; /* Master Configuration Registers */
+ u32 scfg[16]; /* Slave Configuration Registers */
+ u32 pras[16][2]; /* Priority Assignment Slave Registers */
+ u32 mrcr; /* Master Remap Control Register */
+ u32 filler[0x06];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17)
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0)
+#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0)
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
+ *
+ * Copyright (C) SAN People
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoCs:
+ * AT91SAM9261, AT91SAM9G10
+ *
+ * Note that those SoCs are mostly software and pin compatible,
+ * therefore this file applies to all of them. Differences between
+ * those SoCs are concentrated at the end of this file.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Peripherals */
+#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
+#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
+#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
+/* Reserved: 5 */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_USART2 8 /* USART 2 */
+#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
+#define ATMEL_ID_UDP 10 /* USB Device Port */
+#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
+#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */
+#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
+#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
+#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
+#define ATMEL_ID_UHP 20 /* USB Host port */
+#define ATMEL_ID_LCDC 21 /* LDC Controller */
+/* Reserved: 22-28 */
+#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_TCB0 0xfffa0000
+#define ATMEL_BASE_TC0 0xfffa0000
+#define ATMEL_BASE_TC1 0xfffa0040
+#define ATMEL_BASE_TC2 0xfffa0080
+#define ATMEL_BASE_UDP0 0xfffa4000
+#define ATMEL_BASE_MCI 0xfffa8000
+#define ATMEL_BASE_TWI0 0xfffac000
+#define ATMEL_BASE_USART0 0xfffb0000
+#define ATMEL_BASE_USART1 0xfffb4000
+#define ATMEL_BASE_USART2 0xfffb8000
+#define ATMEL_BASE_SSC0 0xfffbc000
+#define ATMEL_BASE_SSC1 0xfffc0000
+#define ATMEL_BASE_SSC2 0xfffc4000
+#define ATMEL_BASE_SPI0 0xfffc8000
+#define ATMEL_BASE_SPI1 0xfffcc000
+/* Reserved: 0xfffc4000 - 0xffffe9ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS 0xffffea00
+#define ATMEL_BASE_SDRAMC 0xffffea00
+#define ATMEL_BASE_SMC 0xffffec00
+#define ATMEL_BASE_MATRIX 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_DBGU 0xfffff200
+#define ATMEL_BASE_PIOA 0xfffff400
+#define ATMEL_BASE_PIOB 0xfffff600
+#define ATMEL_BASE_PIOC 0xfffff800
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWN 0xfffffd10
+#define ATMEL_BASE_RTT 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_GPBR 0xfffffd50
+
+/*
+ * Internal Memory common on all these SoCs
+ */
+#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */
+
+#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
+#define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */
+
+#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */
+#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
+#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+#define ATMEL_BASE_CS6 0x70000000
+#define ATMEL_BASE_CS7 0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+
+/*
+ * SoC specific defines
+ */
+#if defined(CONFIG_AT91SAM9261)
+# define ATMEL_CPU_NAME "AT91SAM9261"
+#elif defined(CONFIG_AT91SAM9G10)
+# define ATMEL_CPU_NAME "AT91SAM9G10"
+#endif
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+ u32 mcfg; /* Master Configuration Registers */
+ u32 scfg[5]; /* Slave Configuration Registers */
+ u32 filler[6];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
+ *
+ * (C) 2007 Atmel Corporation.
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoC:
+ * AT91SAM9263
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9263_H
+#define AT91SAM9263_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Peripherals */
+#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
+#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
+#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
+/* Reserved: 5 */
+/* Reserved: 6 */
+#define ATMEL_ID_USART0 7 /* USART 0 */
+#define ATMEL_ID_USART1 8 /* USART 1 */
+#define ATMEL_ID_USART2 9 /* USART 2 */
+#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */
+#define ATMEL_ID_CAN 12 /* CAN */
+#define ATMEL_ID_TWI 13 /* Two-Wire Interface */
+#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_AC97C 18 /* AC97 Controller */
+#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
+#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_EMAC 21 /* Ethernet */
+/* Reserved: 22 */
+#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */
+#define ATMEL_ID_UDP 24 /* USB Device Port */
+#define ATMEL_ID_ISI 25 /* Image Sensor Interface */
+#define ATMEL_ID_LCDC 26 /* LCD Controller */
+#define ATMEL_ID_DMA 27 /* DMA Controller */
+/* Reserved: 28 */
+#define ATMEL_ID_UHP 29 /* USB Host port */
+#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_UDP 0xfff78000
+#define ATMEL_BASE_TCB0 0xfff7c000
+#define ATMEL_BASE_TC0 0xfff7c000
+#define ATMEL_BASE_TC1 0xfff7c040
+#define ATMEL_BASE_TC2 0xfff7c080
+#define ATMEL_BASE_MCI0 0xfff80000
+#define ATMEL_BASE_MCI1 0xfff84000
+#define ATMEL_BASE_TWI 0xfff88000
+#define ATMEL_BASE_USART0 0xfff8c000
+#define ATMEL_BASE_USART1 0xfff90000
+#define ATMEL_BASE_USART2 0xfff94000
+#define ATMEL_BASE_SSC0 0xfff98000
+#define ATMEL_BASE_SSC1 0xfff9c000
+#define ATMEL_BASE_AC97C 0xfffa0000
+#define ATMEL_BASE_SPI0 0xfffa4000
+#define ATMEL_BASE_SPI1 0xfffa8000
+#define ATMEL_BASE_CAN 0xfffac000
+#define ATMEL_BASE_PWMC 0xfffb8000
+#define ATMEL_BASE_EMAC 0xfffbc000
+#define ATMEL_BASE_ISI 0xfffc4000
+#define ATMEL_BASE_2DGE 0xfffc8000
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_ECC0 0xffffe000
+#define ATMEL_BASE_SDRAMC0 0xffffe200
+#define ATMEL_BASE_SMC0 0xffffe400
+#define ATMEL_BASE_ECC1 0xffffe600
+#define ATMEL_BASE_SDRAMC1 0xffffe800
+#define ATMEL_BASE_SMC1 0xffffea00
+#define ATMEL_BASE_MATRIX 0xffffec00
+#define ATMEL_BASE_CCFG 0xffffed10
+#define ATMEL_BASE_DBGU 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_PIOA 0xfffff200
+#define ATMEL_BASE_PIOB 0xfffff400
+#define ATMEL_BASE_PIOC 0xfffff600
+#define ATMEL_BASE_PIOD 0xfffff800
+#define ATMEL_BASE_PIOE 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWC 0xfffffd10
+#define ATMEL_BASE_RTT0 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_RTT1 0xfffffd50
+#define ATMEL_BASE_GPBR 0xfffffd60
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */
+
+#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */
+
+#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */
+
+#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */
+#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */
+#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
+#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+#define ATMEL_BASE_CS6 0x70000000
+#define ATMEL_BASE_CS7 0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME "AT91SAM9263"
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
+ *
+ * Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9263_MATRIX_H
+#define AT91SAM9263_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * Note: not all masters/slaves are available
+ */
+struct at91_matrix {
+ u32 mcfg[16]; /* Master Configuration Registers */
+ u32 scfg[16]; /* Slave Configuration Registers */
+ u32 pras[16][2]; /* Priority Assignment Slave Registers */
+ u32 mrcr; /* Master Remap Control Register */
+ u32 filler[0x06];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
+#define __ASM_ARCH_AT91SAM9_MATRIX_H
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#include <asm/arch/at91sam9260_matrix.h>
+#elif defined(CONFIG_AT91SAM9261)
+#include <asm/arch/at91sam9261_matrix.h>
+#elif defined(CONFIG_AT91SAM9263)
+#include <asm/arch/at91sam9263_matrix.h>
+#elif defined(CONFIG_AT91SAM9RL)
+#include <asm/arch/at91sam9rl_matrix.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45_matrix.h>
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+#include <asm/arch/at91sam9x5_matrix.h>
+#else
+#error "Unsupported AT91SAM9/CAP9 processor"
+#endif
+
+#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
--- /dev/null
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
+
+#ifdef __ASSEMBLY__
+
+#ifndef ATMEL_BASE_SDRAMC
+#define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0
+#endif
+
+#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
+#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
+#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
+#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
+
+#else
+struct sdramc_reg {
+ u32 mr;
+ u32 tr;
+ u32 cr;
+ u32 lpr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 isr;
+ u32 mdr;
+};
+
+int sdramc_initialize(unsigned int sdram_address,
+ const struct sdramc_reg *p);
+#endif
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91_SDRAMC_MODE_NORMAL 0
+#define AT91_SDRAMC_MODE_NOP 1
+#define AT91_SDRAMC_MODE_PRECHARGE 2
+#define AT91_SDRAMC_MODE_LMR 3
+#define AT91_SDRAMC_MODE_REFRESH 4
+#define AT91_SDRAMC_MODE_EXT_LMR 5
+#define AT91_SDRAMC_MODE_DEEP 6
+
+#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+#define AT91_SDRAMC_NC_8 (0 << 0)
+#define AT91_SDRAMC_NC_9 (1 << 0)
+#define AT91_SDRAMC_NC_10 (2 << 0)
+#define AT91_SDRAMC_NC_11 (3 << 0)
+#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+#define AT91_SDRAMC_NR_11 (0 << 2)
+#define AT91_SDRAMC_NR_12 (1 << 2)
+#define AT91_SDRAMC_NR_13 (2 << 2)
+#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
+#define AT91_SDRAMC_NB_2 (0 << 4)
+#define AT91_SDRAMC_NB_4 (1 << 4)
+#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
+#define AT91_SDRAMC_CAS_1 (1 << 5)
+#define AT91_SDRAMC_CAS_2 (2 << 5)
+#define AT91_SDRAMC_CAS_3 (3 << 5)
+#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
+#define AT91_SDRAMC_DBW_32 (0 << 7)
+#define AT91_SDRAMC_DBW_16 (1 << 7)
+#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
+#define AT91_SDRAMC_TWR_VAL(x) (x << 8)
+#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
+#define AT91_SDRAMC_TRC_VAL(x) (x << 12)
+#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
+#define AT91_SDRAMC_TRP_VAL(x) (x << 16)
+#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
+#define AT91_SDRAMC_TRCD_VAL(x) (x << 20)
+#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
+#define AT91_SDRAMC_TRAS_VAL(x) (x << 24)
+#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_TXSR_VAL(x) (x << 28)
+
+#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
+#define AT91_SDRAMC_LPCB_DISABLE 0
+#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
+#define AT91_SDRAMC_LPCB_POWER_DOWN 2
+#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
+#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
+#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
+#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
+#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
+#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
+#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
+#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
+
+#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
+#define AT91_SDRAMC_MD_SDRAM 0
+#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#ifdef __ASSEMBLY__
+
+#ifndef ATMEL_BASE_SMC
+#define ATMEL_BASE_SMC ATMEL_BASE_SMC0
+#endif
+
+#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
+#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
+#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
+#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
+
+#else
+
+typedef struct at91_cs {
+ u32 setup; /* 0x00 SMC Setup Register */
+ u32 pulse; /* 0x04 SMC Pulse Register */
+ u32 cycle; /* 0x08 SMC Cycle Register */
+ u32 mode; /* 0x0C SMC Mode Register */
+} at91_cs_t;
+
+typedef struct at91_smc {
+ at91_cs_t cs[8];
+} at91_smc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x) (x & 0x7f)
+#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8)
+#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
+
+#define AT91_SMC_MODE_RM_NCS 0x00000000
+#define AT91_SMC_MODE_RM_NRD 0x00000001
+#define AT91_SMC_MODE_WM_NCS 0x00000000
+#define AT91_SMC_MODE_WM_NWE 0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
+#define AT91_SMC_MODE_EXNW_READY 0x00000030
+
+#define AT91_SMC_MODE_BAT 0x00000100
+#define AT91_SMC_MODE_DBW_8 0x00000000
+#define AT91_SMC_MODE_DBW_16 0x00001000
+#define AT91_SMC_MODE_DBW_32 0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF 0x00100000
+#define AT91_SMC_MODE_PMEN 0x01000000
+#define AT91_SMC_MODE_PS_4 0x00000000
+#define AT91_SMC_MODE_PS_8 0x10000000
+#define AT91_SMC_MODE_PS_16 0x20000000
+#define AT91_SMC_MODE_PS_32 0x30000000
+
+#endif
--- /dev/null
+/*
+ * Chip-specific header file for the AT91SAM9M1x family
+ *
+ * (C) 2008 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9G45
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
+#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */
+#define ATMEL_ID_TRNG 6 /* True Random Number Generator */
+#define ATMEL_ID_USART0 7 /* USART 0 */
+#define ATMEL_ID_USART1 8 /* USART 1 */
+#define ATMEL_ID_USART2 9 /* USART 2 */
+#define ATMEL_ID_USART3 10 /* USART 3 */
+#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */
+#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */
+#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA 21 /* DMA Controller */
+#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
+#define ATMEL_ID_LCDC 23 /* LCD Controller */
+#define ATMEL_ID_AC97C 24 /* AC97 Controller */
+#define ATMEL_ID_EMAC 25 /* Ethernet MAC */
+#define ATMEL_ID_ISI 26 /* Image Sensor Interface */
+#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */
+#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
+#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_VDEC 30 /* Video Decoder */
+#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_UDPHS 0xfff78000
+#define ATMEL_BASE_TC0 0xfff7c000
+#define ATMEL_BASE_TC1 0xfff7c040
+#define ATMEL_BASE_TC2 0xfff7c080
+#define ATMEL_BASE_MCI0 0xfff80000
+#define ATMEL_BASE_TWI0 0xfff84000
+#define ATMEL_BASE_TWI1 0xfff88000
+#define ATMEL_BASE_USART0 0xfff8c000
+#define ATMEL_BASE_USART1 0xfff90000
+#define ATMEL_BASE_USART2 0xfff94000
+#define ATMEL_BASE_USART3 0xfff98000
+#define ATMEL_BASE_SSC0 0xfff9c000
+#define ATMEL_BASE_SSC1 0xfffa0000
+#define ATMEL_BASE_SPI0 0xfffa4000
+#define ATMEL_BASE_SPI1 0xfffa8000
+#define ATMEL_BASE_AC97C 0xfffac000
+#define ATMEL_BASE_TSC 0xfffb0000
+#define ATMEL_BASE_ISI 0xfffb4000
+#define ATMEL_BASE_PWMC 0xfffb8000
+#define ATMEL_BASE_EMAC 0xfffbc000
+#define ATMEL_BASE_AES 0xfffc0000
+#define ATMEL_BASE_TDES 0xfffc4000
+#define ATMEL_BASE_SHA 0xfffc8000
+#define ATMEL_BASE_TRNG 0xfffcc000
+#define ATMEL_BASE_MCI1 0xfffd0000
+#define ATMEL_BASE_TC3 0xfffd4000
+#define ATMEL_BASE_TC4 0xfffd4040
+#define ATMEL_BASE_TC5 0xfffd4080
+/* Reserved: 0xfffd8000 - 0xffffe1ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS 0xffffe200
+#define ATMEL_BASE_ECC 0xffffe200
+#define ATMEL_BASE_DDRSDRC1 0xffffe400
+#define ATMEL_BASE_DDRSDRC0 0xffffe600
+#define ATMEL_BASE_SMC 0xffffe800
+#define ATMEL_BASE_MATRIX 0xffffea00
+#define ATMEL_BASE_DMA 0xffffec00
+#define ATMEL_BASE_DBGU 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_PIOA 0xfffff200
+#define ATMEL_BASE_PIOB 0xfffff400
+#define ATMEL_BASE_PIOC 0xfffff600
+#define ATMEL_BASE_PIOD 0xfffff800
+#define ATMEL_BASE_PIOE 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWN 0xfffffd10
+#define ATMEL_BASE_RTT 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_GPBR 0xfffffd60
+#define ATMEL_BASE_RTC 0xfffffdb0
+/* Reserved: 0xfffffdc0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
+#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
+#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
+#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
+#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+#define ATMEL_BASE_CS6 0x70000000
+#define ATMEL_BASE_CS7 0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME "AT91SAM9G45"
+
+#endif
--- /dev/null
+/*
+ * Matrix-centric header file for the AT91SAM9M1x family
+ *
+ * Copyright (C) 2008 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+ u32 mcfg[16];
+ u32 scfg[16];
+ u32 pras[16][2];
+ u32 mrcr; /* 0x100 Master Remap Control */
+ u32 filler[3];
+ u32 tcmr;
+ u32 filler2;
+ u32 ddrmpr;
+ u32 filler3[3];
+ u32 ebicsa;
+ u32 filler4[47];
+ u32 wpmr;
+ u32 wpsr;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91_MATRIX_ULBT_128 (7 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+#define AT91_MATRIX_M6PR_SHIFT 24
+#define AT91_MATRIX_M7PR_SHIFT 28
+
+#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
+#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
+#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
+#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91_MATRIX_RCB9 (1 << 9)
+#define AT91_MATRIX_RCB10 (1 << 10)
+
+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
+#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
+#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Common definitions.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_H
+#define AT91SAM9RL_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Peripherals */
+#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
+#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
+#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
+#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_USART2 8 /* USART 2 */
+#define ATMEL_ID_USART3 9 /* USART 3 */
+#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
+#define ATMEL_ID_TWI0 11 /* TWI 0 */
+#define ATMEL_ID_TWI1 12 /* TWI 1 */
+#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_TC0 16 /* Timer Counter 0 */
+#define ATMEL_ID_TC1 17 /* Timer Counter 1 */
+#define ATMEL_ID_TC2 18 /* Timer Counter 2 */
+#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC 20 /* Touch Screen Controller */
+#define ATMEL_ID_DMA 21 /* DMA Controller */
+#define ATMEL_ID_UDPHS 22 /* USB Device HS */
+#define ATMEL_ID_LCDC 23 /* LCD Controller */
+#define ATMEL_ID_AC97C 24 /* AC97 Controller */
+#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define ATMEL_BASE_TCB0 0xfffa0000
+#define ATMEL_BASE_TC0 0xfffa0000
+#define ATMEL_BASE_TC1 0xfffa0040
+#define ATMEL_BASE_TC2 0xfffa0080
+#define ATMEL_BASE_MCI 0xfffa4000
+#define ATMEL_BASE_TWI0 0xfffa8000
+#define ATMEL_BASE_TWI1 0xfffac000
+#define ATMEL_BASE_USART0 0xfffb0000
+#define ATMEL_BASE_USART1 0xfffb4000
+#define ATMEL_BASE_USART2 0xfffb8000
+#define ATMEL_BASE_USART3 0xfffbc000
+#define ATMEL_BASE_SSC0 0xfffc0000
+#define ATMEL_BASE_SSC1 0xfffc4000
+#define ATMEL_BASE_PWMC 0xfffc8000
+#define ATMEL_BASE_SPI0 0xfffcc000
+#define ATMEL_BASE_TSC 0xfffd0000
+#define ATMEL_BASE_UDPHS 0xfffd4000
+#define ATMEL_BASE_AC97C 0xfffd8000
+#define ATMEL_BASE_SYS 0xffffc000
+
+/*
+ * System Peripherals
+ */
+#define ATMEL_BASE_DMA 0xffffe600
+#define ATMEL_BASE_ECC 0xffffe800
+#define ATMEL_BASE_SDRAMC 0xffffea00
+#define ATMEL_BASE_SMC 0xffffec00
+#define ATMEL_BASE_MATRIX 0xffffee00
+#define ATMEL_BASE_CCFG 0xffffef10
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_DBGU 0xfffff200
+#define ATMEL_BASE_PIOA 0xfffff400
+#define ATMEL_BASE_PIOB 0xfffff600
+#define ATMEL_BASE_PIOC 0xfffff800
+#define ATMEL_BASE_PIOD 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWC 0xfffffd10
+#define ATMEL_BASE_RTT 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_SCKCR 0xfffffd50
+#define ATMEL_BASE_GPBR 0xfffffd60
+#define ATMEL_BASE_RTC 0xfffffe00
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
+
+#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
+#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000 /* NAND */
+#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */
+#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME "AT91SAM9RL"
+
+#endif
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_MATRIX_H
+#define AT91SAM9RL_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+ u32 mcfg[16]; /* Master Configuration Registers */
+ u32 scfg[16]; /* Slave Configuration Registers */
+ u32 pras[16][2]; /* Priority Assignment Slave Registers */
+ u32 mrcr; /* Master Remap Control Register */
+ u32 filler[7];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
--- /dev/null
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9x5 & AT91SAM9N12
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AT91SAM9X5_H__
+#define __AT91SAM9X5_H__
+
+#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
+#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
+#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
+#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */
+#define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */
+#define ATMEL_ID_USART0 5 /* USART 0 */
+#define ATMEL_ID_USART1 6 /* USART 1 */
+#define ATMEL_ID_USART2 7 /* USART 2 */
+#define ATMEL_ID_USART3 8 /* USART 3 */
+#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
+#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_UART0 15 /* UART 0 */
+#define ATMEL_ID_UART1 16 /* UART 1 */
+#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_ADC 19 /* ADC Controller */
+#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
+#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
+#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
+#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
+#define ATMEL_ID_LCDC 25 /* LCD Controller */
+#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
+#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
+#define ATMEL_ID_TRNG 30 /* True Random Number Generator */
+#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define ATMEL_BASE_SPI0 0xf0000000
+#define ATMEL_BASE_SPI1 0xf0004000
+#define ATMEL_BASE_HSMCI0 0xf0008000
+#define ATMEL_BASE_HSMCI1 0xf000c000
+#define ATMEL_BASE_SSC 0xf0010000
+#define ATMEL_BASE_CAN0 0xf8000000
+#define ATMEL_BASE_CAN1 0xf8004000
+#define ATMEL_BASE_TC0 0xf8008000
+#define ATMEL_BASE_TC1 0xf8008040
+#define ATMEL_BASE_TC2 0xf8008080
+#define ATMEL_BASE_TC3 0xf800c000
+#define ATMEL_BASE_TC4 0xf800c040
+#define ATMEL_BASE_TC5 0xf800c080
+#define ATMEL_BASE_TWI0 0xf8010000
+#define ATMEL_BASE_TWI1 0xf8014000
+#define ATMEL_BASE_TWI2 0xf8018000
+#define ATMEL_BASE_USART0 0xf801c000
+#define ATMEL_BASE_USART1 0xf8020000
+#define ATMEL_BASE_USART2 0xf8024000
+#define ATMEL_BASE_USART3 0xf8028000
+#define ATMEL_BASE_EMAC0 0xf802c000
+#define ATMEL_BASE_EMAC1 0xf8030000
+#define ATMEL_BASE_PWM 0xf8034000
+#define ATMEL_BASE_LCDC 0xf8038000
+#define ATMEL_BASE_UDPHS 0xf803c000
+#define ATMEL_BASE_UART0 0xf8040000
+#define ATMEL_BASE_UART1 0xf8044000
+#define ATMEL_BASE_ISI 0xf8048000
+#define ATMEL_BASE_ADC 0xf804c000
+#define ATMEL_BASE_SYS 0xffffc000
+
+/*
+ * System Peripherals
+ */
+#define ATMEL_BASE_FUSE 0xffffdc00
+#define ATMEL_BASE_MATRIX 0xffffde00
+#define ATMEL_BASE_PMECC 0xffffe000
+#define ATMEL_BASE_PMERRLOC 0xffffe600
+#define ATMEL_BASE_DDRSDRC 0xffffe800
+#define ATMEL_BASE_SMC 0xffffea00
+#define ATMEL_BASE_DMAC0 0xffffec00
+#define ATMEL_BASE_DMAC1 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_DBGU 0xfffff200
+#define ATMEL_BASE_PIOA 0xfffff400
+#define ATMEL_BASE_PIOB 0xfffff600
+#define ATMEL_BASE_PIOC 0xfffff800
+#define ATMEL_BASE_PIOD 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffe00
+#define ATMEL_BASE_SHDWC 0xfffffe10
+#define ATMEL_BASE_PIT 0xfffffe30
+#define ATMEL_BASE_WDT 0xfffffe40
+#define ATMEL_BASE_GPBR 0xfffffe60
+#define ATMEL_BASE_RTC 0xfffffeb0
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */
+#else /* AT91SAM9X5 */
+#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
+#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
+#endif
+
+/* 9x5 series chip id definitions */
+#define ARCH_ID_AT91SAM9X5 0x819a05a0
+#define ARCH_ID_VERSION_MASK 0x1f
+#define ARCH_EXID_AT91SAM9G15 0x00000000
+#define ARCH_EXID_AT91SAM9G35 0x00000001
+#define ARCH_EXID_AT91SAM9X35 0x00000002
+#define ARCH_EXID_AT91SAM9G25 0x00000003
+#define ARCH_EXID_AT91SAM9X25 0x00000004
+
+#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
+#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
+#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
+#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
+#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
+#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
+
+/*
+ * Cpu Name
+ */
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_CPU_NAME "AT91SAM9N12"
+#else /* AT91SAM9X5 */
+#define ATMEL_CPU_NAME get_cpu_name()
+#endif
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 4
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
+
+/*
+ * at91sam9x5 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac1(void);
+unsigned int has_emac0(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Matrix-centric header file for the AT91SAM9X5 family
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AT91SAM9X5_MATRIX_H__
+#define __AT91SAM9X5_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+
+/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
+struct at91_matrix {
+ u32 mcfg[16];
+ u32 scfg[16];
+ u32 pras[16][2];
+ u32 mrcr; /* 0x100 Master Remap Control */
+ u32 filler[5];
+#ifdef CONFIG_AT91SAM9X5
+ u32 filler1[2];
+#endif
+ /* EBI Chip Select Assignment Register
+ * 0x118: AT91SAM9N12
+ * 0x120: AT91SAM9X5
+ */
+ u32 ebicsa;
+ u32 filler4[47];
+#ifdef CONFIG_AT91SAM9N12
+ u32 filler5[2];
+#endif
+ u32 wpmr;
+ u32 wpsr;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91_MATRIX_ULBT_128 (7 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+#define AT91_MATRIX_M6PR_SHIFT 24
+#define AT91_MATRIX_M7PR_SHIFT 28
+
+#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
+#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
+#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
+#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91_MATRIX_RCB9 (1 << 9)
+#define AT91_MATRIX_RCB10 (1 << 10)
+
+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
+#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91_MATRIX_MP_OFF (0 << 25)
+#define AT91_MATRIX_MP_ON (1 << 25)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_MPDDRC_H__
+#define __ATMEL_MPDDRC_H__
+
+/*
+ * Only define the needed register in mpddr
+ * If other register needed, will add them later
+ */
+struct atmel_mpddr {
+ u32 mr;
+ u32 rtr;
+ u32 cr;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 reserved[2];
+ u32 md;
+};
+
+int ddr2_init(const unsigned int ram_address,
+ const struct atmel_mpddr *mpddr);
+
+/* Bit field in mode register */
+#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
+#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
+#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2
+#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3
+#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4
+#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
+#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
+#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
+
+/* Bit field in configuration register */
+#define ATMEL_MPDDRC_CR_NC_MASK 0x3
+#define ATMEL_MPDDRC_CR_NC_COL_9 0x0
+#define ATMEL_MPDDRC_CR_NC_COL_10 0x1
+#define ATMEL_MPDDRC_CR_NC_COL_11 0x2
+#define ATMEL_MPDDRC_CR_NC_COL_12 0x3
+#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2)
+#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4)
+#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
+#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
+#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
+#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
+#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16)
+#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
+#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20)
+#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21)
+#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22)
+#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23)
+
+/* Bit field in timing parameter 0 register */
+#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0
+#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4
+#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8
+#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12
+#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16
+#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20
+#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
+#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24
+#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1
+#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28
+#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
+
+/* Bit field in timing parameter 1 register */
+#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0
+#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f
+#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8
+#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff
+#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16
+#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff
+#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24
+#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
+
+/* Bit field in timing parameter 2 register */
+#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0
+#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
+#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4
+#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
+#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8
+#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf
+#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12
+#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7
+#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16
+#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
+
+/* Bit field in Memory Device Register */
+#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
+#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
+#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
+#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
+#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ATMEL_SERIAL_H
+#define _ATMEL_SERIAL_H
+
+/* Information about a serial port */
+struct atmel_serial_platdata {
+ uint32_t base_addr;
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2005-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_USBA_UDC_H__
+#define __ATMEL_USBA_UDC_H__
+
+#include <linux/usb/atmel_usba_udc.h>
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
+ [idx] = { \
+ .name = nam, \
+ .index = idx, \
+ .fifo_size = maxpkt, \
+ .nr_banks = maxbk, \
+ .can_dma = dma, \
+ .can_isoc = isoc, \
+ }
+
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+ defined(CONFIG_AT91SAM9X5)
+static struct usba_ep_data usba_udc_ep[] = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 1024, 2, 1, 1),
+ EP("ep2", 2, 1024, 2, 1, 1),
+ EP("ep3", 3, 1024, 3, 1, 0),
+ EP("ep4", 4, 1024, 3, 1, 0),
+ EP("ep5", 5, 1024, 3, 1, 1),
+ EP("ep6", 6, 1024, 3, 1, 1),
+};
+#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+static struct usba_ep_data usba_udc_ep[] = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 1024, 3, 1, 0),
+ EP("ep2", 2, 1024, 3, 1, 0),
+ EP("ep3", 3, 1024, 2, 1, 0),
+ EP("ep4", 4, 1024, 2, 1, 0),
+ EP("ep5", 5, 1024, 2, 1, 0),
+ EP("ep6", 6, 1024, 2, 1, 0),
+ EP("ep7", 7, 1024, 2, 1, 0),
+ EP("ep8", 8, 1024, 2, 0, 0),
+ EP("ep9", 9, 1024, 2, 0, 0),
+ EP("ep10", 10, 1024, 2, 0, 0),
+ EP("ep11", 11, 1024, 2, 0, 0),
+ EP("ep12", 12, 1024, 2, 0, 0),
+ EP("ep13", 13, 1024, 2, 0, 0),
+ EP("ep14", 14, 1024, 2, 0, 0),
+ EP("ep15", 15, 1024, 2, 0, 0),
+};
+#else
+# error "NO usba_udc_ep defined"
+#endif
+
+#undef EP
+
+struct usba_platform_data pdata = {
+ .num_ep = ARRAY_SIZE(usba_udc_ep),
+ .ep = usba_udc_ep,
+};
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARM_ARCH_CLK_H__
+#define __ASM_ARM_ARCH_CLK_H__
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/global_data.h>
+
+static inline unsigned long get_cpu_clk_rate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.cpu_clk_rate_hz;
+}
+
+static inline unsigned long get_main_clk_rate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.main_clk_rate_hz;
+}
+
+static inline unsigned long get_mck_clk_rate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.mck_rate_hz;
+}
+
+static inline unsigned long get_plla_clk_rate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.plla_rate_hz;
+}
+
+static inline unsigned long get_pllb_clk_rate(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.pllb_rate_hz;
+}
+
+static inline u32 get_pllb_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ return gd->arch.at91_pllb_usb_init;
+}
+
+#ifdef CPU_HAS_H32MXDIV
+static inline unsigned int get_h32mxdiv(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
+}
+#else
+static inline unsigned int get_h32mxdiv(void)
+{
+ return 0;
+}
+#endif
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
+{
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_mci_clk_rate(void)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+static inline unsigned long get_pit_clk_rate(void)
+{
+ if (get_h32mxdiv())
+ return get_mck_clk_rate() / 2;
+ else
+ return get_mck_clk_rate();
+}
+
+int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
+void at91_periph_clk_disable(int id);
+#endif /* __ASM_ARM_ARCH_CLK_H__ */
--- /dev/null
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
+ *
+ * Copyright (C) 2005 HP Labs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_AT91_GPIO_H
+#define __ASM_ARCH_AT91_GPIO_H
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_ATMEL_LEGACY
+
+#define PIN_BASE 0
+
+#define MAX_GPIO_BANKS 5
+
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+
+#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
+
+#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
+
+#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
+
+#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
+
+#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
+#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
+#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
+#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
+#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
+#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
+#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
+#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
+#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
+#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
+#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
+#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
+#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
+#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
+#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
+#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
+#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
+#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
+#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
+#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
+#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
+#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
+#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
+#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
+#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
+#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
+#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
+#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
+#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
+#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
+#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
+#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
+
+static unsigned long at91_pios[] = {
+ ATMEL_BASE_PIOA,
+ ATMEL_BASE_PIOB,
+ ATMEL_BASE_PIOC,
+#ifdef ATMEL_BASE_PIOD
+ ATMEL_BASE_PIOD,
+#ifdef ATMEL_BASE_PIOE
+ ATMEL_BASE_PIOE
+#endif
+#endif
+};
+
+static inline void *pin_to_controller(unsigned pin)
+{
+ pin -= PIN_BASE;
+ pin /= 32;
+ return (void *)(at91_pios[pin]);
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+ pin -= PIN_BASE;
+ return 1 << (pin % 32);
+}
+
+/* The following macros are need for backward compatibility */
+#define at91_set_GPIO_periph(x, y) \
+ at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_A_periph(x, y) \
+ at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_B_periph(x, y) \
+ at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_output(x, y) \
+ at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_input(x, y) \
+ at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_value(x, y) \
+ at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_get_gpio_value(x) \
+ at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
+#else
+#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
+#define at91_get_gpio_value(x) at91_get_pio_value(x)
+#endif
+
+#define GPIO_PIOA_BASE (0)
+#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
+#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
+#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
+
+static inline unsigned at91_gpio_to_port(unsigned gpio)
+{
+ return gpio / 32;
+}
+
+static inline unsigned at91_gpio_to_pin(unsigned gpio)
+{
+ return gpio % 32;
+}
+
+/* Platform data for each GPIO port */
+struct at91_port_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
+#endif /* __ASM_ARCH_AT91_GPIO_H */
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARM_ARCH_HARDWARE_H__
+#define __ASM_ARM_ARCH_HARDWARE_H__
+
+#if defined(CONFIG_AT91RM9200)
+# include <asm/arch/at91rm9200.h>
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \
+ defined(CONFIG_AT91SAM9XE)
+# include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
+# include <asm/arch/at91sam9261.h>
+#elif defined(CONFIG_AT91SAM9263)
+# include <asm/arch/at91sam9263.h>
+#elif defined(CONFIG_AT91SAM9RL)
+# include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+# include <asm/arch/at91sam9g45.h>
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+# include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
+#elif defined(CONFIG_SAMA5D4)
+# include <asm/arch/sama5d4.h>
+#else
+# error "Unsupported AT91 processor"
+#endif
+
+#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */
--- /dev/null
+/*
+ * Bus Matrix header file for the SAMA5 family
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_MATRIX_H
+#define __SAMA5_MATRIX_H
+
+struct atmel_matrix {
+ u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
+ u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
+ u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
+ u32 res1[20]; /* 0x100 ~ 0x14c */
+ u32 meier; /* 0x150: Master Error Interrupt Enable Register */
+ u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
+ u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
+ u32 mesr; /* 0x15c: Master Error Status Register */
+ u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
+ u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
+ u32 wpmr; /* 0x1E4: Write Protection Mode Register */
+ u32 wpsr; /* 0x1E8: Write Protection Status Register */
+ u32 res3[5]; /* 0x1EC ~ 0x1FC */
+ u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */
+ u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */
+ u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */
+ u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
+};
+
+/* Bit field in WPMR */
+#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
+#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
+
+#endif
--- /dev/null
+/*
+ * Special Function Register (SFR)
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_SFR_H
+#define __SAMA5_SFR_H
+
+struct atmel_sfr {
+ u32 reserved1; /* 0x00 */
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 reserved2; /* 0x08 */
+ u32 reserved3; /* 0x0c */
+ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
+ u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
+ u32 reserved4[4]; /* 0x18 ~ 0x24 */
+ u32 secure; /* 0x28: Security Configuration Register */
+ u32 reserved5[5]; /* 0x2c ~ 0x3c */
+ u32 ebicfg; /* 0x40: EBI Configuration Register */
+ u32 reserved6[2]; /* 0x44 ~ 0x48 */
+ u32 sn0; /* 0x4c */
+ u32 sn1; /* 0x50 */
+ u32 aicredir; /* 0x54 */
+};
+
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
+
+/* Bit field in AICREDIR */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
+
+#endif
--- /dev/null
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
+#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */
+#define ATMEL_ID_SMD 11 /* SMD Soft Modem */
+#define ATMEL_ID_USART0 12 /* USART 0 */
+#define ATMEL_ID_USART1 13 /* USART 1 */
+#define ATMEL_ID_USART2 14 /* USART 2 */
+#define ATMEL_ID_USART3 15 /* USART 3 */
+#define ATMEL_ID_UART0 16
+#define ATMEL_ID_UART1 17
+#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1 22 /* */
+#define ATMEL_ID_MCI2 23 /* */
+#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0 26 /* */
+#define ATMEL_ID_TC1 27 /* */
+#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0 30 /* DMA Controller */
+#define ATMEL_ID_DMA1 31 /* DMA Controller */
+#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */
+#define ATMEL_ID_GMAC 34
+#define ATMEL_ID_EMAC 35 /* Ethernet MAC */
+#define ATMEL_ID_LCDC 36 /* LCD Controller */
+#define ATMEL_ID_ISI 37 /* Image Sensor Interface */
+#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0 40
+#define ATMEL_ID_CAN1 41
+#define ATMEL_ID_SHA 42
+#define ATMEL_ID_AES 43
+#define ATMEL_ID_TDES 44
+#define ATMEL_ID_TRNG 45
+#define ATMEL_ID_ARM 46
+#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE 48
+#define ATMEL_ID_MPDDRC 49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3 0x8a5c07c0
+#define ARCH_EXID_SAMA5D31 0x00444300
+#define ARCH_EXID_SAMA5D33 0x00414300
+#define ARCH_EXID_SAMA5D34 0x00414301
+#define ARCH_EXID_SAMA5D35 0x00584300
+#define ARCH_EXID_SAMA5D36 0x00004301
+
+#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+#define cpu_is_sama5d36() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D36))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0 0xf0000000
+#define ATMEL_BASE_SPI0 0xf0004000
+#define ATMEL_BASE_SSC0 0xf000C000
+#define ATMEL_BASE_TC2 0xf0010000
+#define ATMEL_BASE_TWI0 0xf0014000
+#define ATMEL_BASE_TWI1 0xf0018000
+#define ATMEL_BASE_USART0 0xf001c000
+#define ATMEL_BASE_USART1 0xf0020000
+#define ATMEL_BASE_UART0 0xf0024000
+#define ATMEL_BASE_GMAC 0xf0028000
+#define ATMEL_BASE_PWMC 0xf002c000
+#define ATMEL_BASE_LCDC 0xf0030000
+#define ATMEL_BASE_ISI 0xf0034000
+#define ATMEL_BASE_SFR 0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1 0xf8000000
+#define ATMEL_BASE_MCI2 0xf8004000
+#define ATMEL_BASE_SPI1 0xf8008000
+#define ATMEL_BASE_SSC1 0xf800c000
+#define ATMEL_BASE_CAN1 0xf8010000
+#define ATMEL_BASE_TC3 0xf8014000
+#define ATMEL_BASE_TSADC 0xf8018000
+#define ATMEL_BASE_TWI2 0xf801c000
+#define ATMEL_BASE_USART2 0xf8020000
+#define ATMEL_BASE_USART3 0xf8024000
+#define ATMEL_BASE_UART1 0xf8028000
+#define ATMEL_BASE_EMAC 0xf802c000
+#define ATMEL_BASE_UDPHS 0xf8030000
+#define ATMEL_BASE_SHA 0xf8034000
+#define ATMEL_BASE_AES 0xf8038000
+#define ATMEL_BASE_TDES 0xf803c000
+#define ATMEL_BASE_TRNG 0xf8040000
+/* Reserved: 0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS 0xffffc000
+#define ATMEL_BASE_SMC 0xffffc000
+#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE 0xffffe400
+#define ATMEL_BASE_DMAC0 0xffffe600
+#define ATMEL_BASE_DMAC1 0xffffe800
+#define ATMEL_BASE_MPDDRC 0xffffea00
+#define ATMEL_BASE_MATRIX 0xffffec00
+#define ATMEL_BASE_DBGU 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_PIOA 0xfffff200
+#define ATMEL_BASE_PIOB 0xfffff400
+#define ATMEL_BASE_PIOC 0xfffff600
+#define ATMEL_BASE_PIOD 0xfffff800
+#define ATMEL_BASE_PIOE 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffe00
+#define ATMEL_BASE_SHDWN 0xfffffe10
+#define ATMEL_BASE_PIT 0xfffffe30
+#define ATMEL_BASE_WDT 0xfffffe40
+#define ATMEL_BASE_SCKCR 0xfffffe50
+#define ATMEL_BASE_GPBR 0xfffffe60
+#define ATMEL_BASE_RTC 0xfffffeb0
+/* Reserved: 0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
+#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
+#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_CS1 0x40000000
+#define ATMEL_BASE_CS2 0x50000000
+#define ATMEL_BASE_CS3 0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV 0x3fff
+#define CPU_HAS_PCR
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
+#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
+#else
+struct at91_cs {
+ u32 setup; /* 0x600 SMC Setup Register */
+ u32 pulse; /* 0x604 SMC Pulse Register */
+ u32 cycle; /* 0x608 SMC Cycle Register */
+ u32 timings; /* 0x60C SMC Cycle Register */
+ u32 mode; /* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+ u32 reserved[384];
+ struct at91_cs cs[4];
+};
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x) (x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS 0x00000000
+#define AT91_SMC_MODE_RM_NRD 0x00000001
+#define AT91_SMC_MODE_WM_NCS 0x00000000
+#define AT91_SMC_MODE_WM_NWE 0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
+#define AT91_SMC_MODE_EXNW_READY 0x00000030
+
+#define AT91_SMC_MODE_BAT 0x00000100
+#define AT91_SMC_MODE_DBW_8 0x00000000
+#define AT91_SMC_MODE_DBW_16 0x00001000
+#define AT91_SMC_MODE_DBW_32 0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF 0x00100000
+#define AT91_SMC_MODE_PMEN 0x01000000
+#define AT91_SMC_MODE_PS_4 0x00000000
+#define AT91_SMC_MODE_PS_8 0x10000000
+#define AT91_SMC_MODE_PS_16 0x20000000
+#define AT91_SMC_MODE_PS_32 0x30000000
+
+#endif
--- /dev/null
+/*
+ * Chip-specific header file for the SAMA5D4 SoC
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5D4_H
+#define __SAMA5D4_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* It's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
+#define ATMEL_ID_SYS 1 /* System Controller */
+#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer */
+#define ATMEL_ID_WDT 4 /* Watchdog timer */
+#define ATMEL_ID_PIOD 5 /* Parallel I/O Controller D */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
+#define ATMEL_ID_ICM 9 /* Integrity Check Monitor */
+#define ATMEL_ID_PKCC 10 /* Public Key Crypto Controller */
+#define ATMEL_ID_AES 12 /* Advanced Encryption Standard */
+#define ATMEL_ID_AESB 13 /* AES Bridge*/
+#define ATMEL_ID_TDES 14 /* Triple Data Encryption Standard */
+#define ATMEL_ID_SHA 15 /* SHA Signature */
+#define ATMEL_ID_MPDDRC 16 /* MPDDR controller */
+#define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */
+#define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */
+#define ATMEL_ID_VDEC 19 /* Video Decoder */
+#define ATMEL_ID_SBM 20 /* Secure Box Module */
+#define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */
+#define ATMEL_ID_PIOA 23 /* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB 24 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 25 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOE 26 /* Parallel I/O Controller E */
+#define ATMEL_ID_UART0 27 /* UART 0 */
+#define ATMEL_ID_UART1 28 /* UART 1 */
+#define ATMEL_ID_USART2 29 /* USART 2 */
+#define ATMEL_ID_USART3 30 /* USART 3 */
+#define ATMEL_ID_USART4 31 /* USART 4 */
+#define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1 36 /* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 38 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SPI2 39 /* Serial Peripheral Interface 2 */
+#define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
+#define ATMEL_ID_TC1 41 /* Timer Counter 1 (ch. 3, 4, 5) */
+#define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */
+#define ATMEL_ID_PWMC 43 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_ADC 44 /* Touch Screen ADC Controller */
+#define ATMEL_ID_DBGU 45 /* Debug Unit Interrupt */
+#define ATMEL_ID_UHPHS 46 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 47 /* USB Device High Speed */
+#define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1 49 /* Synchronous Serial Controller 1 */
+#define ATMEL_ID_XDMAC1 50 /* DMA Controller 1 */
+#define ATMEL_ID_LCDC 51 /* LCD Controller */
+#define ATMEL_ID_ISI 52 /* Image Sensor Interface */
+#define ATMEL_ID_TRNG 53 /* True Random Number Generator */
+#define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
+#define ATMEL_ID_GMAC1 55 /* Ethernet MAC 1 */
+#define ATMEL_ID_IRQ 56 /* IRQ Interrupt ID */
+#define ATMEL_ID_SFC 57 /* Fuse Controller */
+#define ATMEL_ID_SECURAM 59 /* Secured RAM */
+#define ATMEL_ID_SMD 61 /* SMD Soft Modem */
+#define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */
+#define ATMEL_ID_CATB 63 /* Capacitive Touch Controller */
+#define ATMEL_ID_SFR 64 /* Special Funcion Register */
+#define ATMEL_ID_AIC 65 /* Advanced Interrupt Controller */
+#define ATMEL_ID_SAIC 66 /* Secured Advanced Interrupt Controller */
+#define ATMEL_ID_L2CC 67 /* L2 Cache Controller */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_LCDC 0xf0000000
+#define ATMEL_BASE_DMAC1 0xf0004000
+#define ATMEL_BASE_ISI 0xf0008000
+#define ATMEL_BASE_PKCC 0xf000C000
+#define ATMEL_BASE_MPDDRC 0xf0010000
+#define ATMEL_BASE_DMAC0 0xf0014000
+#define ATMEL_BASE_PMC 0xf0018000
+#define ATMEL_BASE_MATRIX0 0xf001c000
+#define ATMEL_BASE_AESB 0xf0020000
+/* Reserved: 0xf0024000 - 0xf8000000 */
+#define ATMEL_BASE_MCI0 0xf8000000
+#define ATMEL_BASE_UART0 0xf8004000
+#define ATMEL_BASE_SSC0 0xf8008000
+#define ATMEL_BASE_PWMC 0xf800c000
+#define ATMEL_BASE_SPI0 0xf8010000
+#define ATMEL_BASE_TWI0 0xf8014000
+#define ATMEL_BASE_TWI1 0xf8018000
+#define ATMEL_BASE_TC0 0xf801c000
+#define ATMEL_BASE_GMAC0 0xf8020000
+#define ATMEL_BASE_TWI2 0xf8024000
+#define ATMEL_BASE_SFR 0xf8028000
+#define ATMEL_BASE_USART0 0xf802c000
+#define ATMEL_BASE_USART1 0xf8030000
+/* Reserved: 0xf8034000 - 0xfc000000 */
+#define ATMEL_BASE_MCI1 0xfc000000
+#define ATMEL_BASE_UART1 0xfc004000
+#define ATMEL_BASE_USART2 0xfc008000
+#define ATMEL_BASE_USART3 0xfc00c000
+#define ATMEL_BASE_USART4 0xfc010000
+#define ATMEL_BASE_SSC1 0xfc014000
+#define ATMEL_BASE_SPI1 0xfc018000
+#define ATMEL_BASE_SPI2 0xfc01c000
+#define ATMEL_BASE_TC1 0xfc020000
+#define ATMEL_BASE_TC2 0xfc024000
+#define ATMEL_BASE_GMAC1 0xfc028000
+#define ATMEL_BASE_UDPHS 0xfc02c000
+#define ATMEL_BASE_TRNG 0xfc030000
+#define ATMEL_BASE_ADC 0xfc034000
+#define ATMEL_BASE_TWI3 0xfc038000
+
+#define ATMEL_BASE_MATRIX1 0xfc054000
+
+#define ATMEL_BASE_SMC 0xfc05c000
+#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
+
+#define ATMEL_BASE_PIOD 0xfc068000
+#define ATMEL_BASE_RSTC 0xfc068600
+#define ATMEL_BASE_PIT 0xfc068630
+#define ATMEL_BASE_WDT 0xfc068640
+
+#define ATMEL_BASE_DBGU 0xfc069000
+#define ATMEL_BASE_PIOA 0xfc06a000
+#define ATMEL_BASE_PIOB 0xfc06b000
+#define ATMEL_BASE_PIOC 0xfc06c000
+#define ATMEL_BASE_PIOE 0xfc06d000
+#define ATMEL_BASE_AIC 0xfc06e000
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */
+#define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */
+#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
+#define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */
+#define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI 0x00700000
+#define ATMEL_BASE_DAP 0x00800000
+#define ATMEL_BASE_SMD 0x00900000
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_CS1 0x60000000
+#define ATMEL_BASE_CS2 0x70000000
+#define ATMEL_BASE_CS3 0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV 0x3fff
+#define CPU_HAS_PCR
+#define CPU_HAS_H32MXDIV
+
+/* sama5d4 series chip id definitions */
+#define ARCH_ID_SAMA5D4 0x8a5c07c0
+#define ARCH_EXID_SAMA5D41 0x00000001
+#define ARCH_EXID_SAMA5D42 0x00000002
+#define ARCH_EXID_SAMA5D43 0x00000003
+#define ARCH_EXID_SAMA5D44 0x00000004
+
+#define cpu_is_sama5d4() (get_chip_id() == ARCH_ID_SAMA5D4)
+#define cpu_is_sama5d41() (cpu_is_sama5d4() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D41))
+#define cpu_is_sama5d42() (cpu_is_sama5d4() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D42))
+#define cpu_is_sama5d43() (cpu_is_sama5d4() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D43))
+#define cpu_is_sama5d44() (cpu_is_sama5d4() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D44))
+
+/*
+ * No PMECC Galois table in ROM
+ */
+#define NO_GALOIS_TABLE_IN_ROM
+
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
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