]> git.sur5r.net Git - u-boot/commitdiff
x86: baytrail: pci region 3 is not always mapped to end of ram
authorAndrew Bradford <andrew.bradford@kodakalaris.com>
Wed, 3 Jun 2015 16:37:39 +0000 (12:37 -0400)
committerSimon Glass <sjg@chromium.org>
Thu, 4 Jun 2015 09:03:18 +0000 (03:03 -0600)
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/baytrail/pci.c

index 6c291f9ee9c25ab44e733d845785807d30192692..48409de5c4d51013ddbd2fec0387d9fe78d70a44 100644 (file)
@@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose)
        pci_set_region(hose->regions + 3,
                       0,
                       0,
-                      gd->ram_size,
+                      gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000,
                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
        hose->region_count = 4;