arm: vf610: add NFC clock support

Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 5256624adf4691c33d68395faef0ab06594de7fc..724682c683c70d1f94b0d6c43e005bd63215a12a 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -156,14 +156,27 @@ struct anadig_reg {
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET       18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK         (0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)           (((v) & 0x3) << 18)
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET          12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK            (0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v)              (((v) & 0x3) << 12)
 
 #define CCM_CSCDR1_RMII_CLK_EN                 (1 << 24)
 
+#define CCM_CSCDR2_NFC_EN                      (1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN             (1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV                 (1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET         4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK           (0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v)             (((v) & 0xf) << 4)
+
 #define CCM_CSCDR2_ESDHC1_EN                   (1 << 29)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET       20
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK         (0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)           (((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET          13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK            (0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v)              (((v) & 0x7) << 13)
 #define CCM_CSCDR3_QSPI0_EN                    (1 << 4)
 #define CCM_CSCDR3_QSPI0_DIV(v)                        ((v) << 3)
 #define CCM_CSCDR3_QSPI0_X2_DIV(v)             ((v) << 2)
@@ -195,6 +208,7 @@ struct anadig_reg {
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
 #define CCM_CCGR9_FEC0_CTRL_MASK               0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK               (0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK               0x3
 
 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index bd6f680b63baaa00ffb01b27291f38461494441f..bb002172c9d282fbd6fa06c9a100a95b8709f644 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -86,6 +86,7 @@
 #define ESDHC1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x00032000)
 #define ENET_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00051000)
+#define NFC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE                0x20000000