]> git.sur5r.net Git - u-boot/commitdiff
armv8/ls1043aqds: add QSPI boot support
authorQianyu Gong <qianyu.gong@nxp.com>
Mon, 25 Jan 2016 07:16:07 +0000 (15:16 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 27 Jan 2016 16:29:09 +0000 (08:29 -0800)
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
board/freescale/ls1043aqds/MAINTAINERS
board/freescale/ls1043aqds/README
board/freescale/ls1043aqds/ls1043aqds.c
configs/ls1043aqds_qspi_defconfig [new file with mode: 0644]
include/configs/ls1043a_common.h
include/configs/ls1043aqds.h

index b10ee430cfb5766c176cc32e3f17be096921cb2d..15ade84c48ae6da4b71b4b88d6638f20f2466e79 100644 (file)
@@ -151,6 +151,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
          PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
index 868bb7297997e4d6a1f621294f40ce490c4c4a9d..65a0af193097cd99c96a72b875558cf641ea68f5 100644 (file)
@@ -8,3 +8,4 @@ F:      configs/ls1043aqds_nor_ddr3_defconfig
 F:     configs/ls1043aqds_nand_defconfig
 F:     configs/ls1043aqds_sdcard_ifc_defconfig
 F:     configs/ls1043aqds_sdcard_qspi_defconfig
+F:     configs/ls1043aqds_qspi_defconfig
index 6261a778aaaf4d45ce7d99f22f41a1ca826b4838..a6fd7a35f5455ce43d4458381a76c2db93c8dcf8 100644 (file)
@@ -94,3 +94,4 @@ a) Promjet Boot
 b) NOR boot
 c) NAND boot
 d) SD boot
+e) QSPI boot
index bb1444740956260c63501722acec0dae3dac2057..01db07822237a21aac9ef2a8842e263b4101b218 100644 (file)
@@ -47,7 +47,7 @@ enum {
 int checkboard(void)
 {
        char buf[64];
-#ifndef CONFIG_SD_BOOT
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
        u8 sw;
 #endif
 
@@ -55,6 +55,8 @@ int checkboard(void)
 
 #ifdef CONFIG_SD_BOOT
        puts("SD\n");
+#elif defined(CONFIG_QSPI_BOOT)
+       puts("QSPI\n");
 #else
        sw = QIXIS_READ(brdcfg[0]);
        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..cb076c9
--- /dev/null
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
index 8900daee9501d443e7eeb3db0d146cb02c6a9860..6150bc1a74fa42659e5824eecfb2b181f3192eac 100644 (file)
 #endif
 
 /* IFC */
-#ifndef CONFIG_SD_BOOT_QSPI
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_IFC
 /*
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 #define CONFIG_SPI_FLASH_STMICRO       /* cs0 */
 #define CONFIG_SPI_FLASH_SST           /* cs1 */
 #define CONFIG_SPI_FLASH_EON           /* cs2 */
-#ifndef CONFIG_SD_BOOT_QSPI
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SF_DEFAULT_BUS          1
 #define CONFIG_SF_DEFAULT_CS           0
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 
-#ifdef CONFIG_SD_BOOT_QSPI
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR                0x400d0000
 #define CONFIG_ENV_SPI_BUS             0
index 60d189bf09cb39f58ff3be787dee1570a6fc9350..4ab8e13ba1a90154661668dda90bd349c8c5a9fa 100644 (file)
 #include "ls1043a_common.h"
 
 #define CONFIG_DISPLAY_CPUINFO
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#else
 #define CONFIG_DISPLAY_BOARDINFO
+#endif
 
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE           0x82000000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE           0x40010000
 #else
 #define CONFIG_SYS_TEXT_BASE           0x60100000
 #endif
@@ -118,7 +124,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * IFC Definitions
  */
-#ifndef CONFIG_SD_BOOT_QSPI
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_NOR0_CSPR_EXT       (0x0)
 #define CONFIG_SYS_NOR0_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
                                CSPR_PORT_SIZE_16 | \
@@ -210,7 +216,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 << 10)
 #endif
 
-#ifdef CONFIG_SD_BOOT_QSPI
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
@@ -233,8 +239,10 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_NAND               0x09
 #define QIXIS_LBMAP_SD                 0x00
 #define QIXIS_LBMAP_SD_QSPI            0xff
+#define QIXIS_LBMAP_QSPI               0xff
 #define QIXIS_RCW_SRC_NAND             0x106
 #define QIXIS_RCW_SRC_SD               0x040
+#define QIXIS_RCW_SRC_QSPI             0x045
 #define QIXIS_RST_CTL_RESET            0x41
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
@@ -362,7 +370,7 @@ unsigned long get_board_ddr_clk(void);
 #define VDD_MV_MAX                     1212
 
 /* QSPI device */
-#ifdef CONFIG_SD_BOOT_QSPI
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_QSPI
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SPI_FLASH_SPANSION
@@ -421,6 +429,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV         0
 #define CONFIG_ENV_SIZE                        0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE           0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)