+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
#ifndef _ASM_IO_H
#define _ASM_IO_H
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
-/*
- * ISA space is 'always mapped' on a typical x86 system, no need to
- * explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define isa_readb(a) readb((a))
-#define isa_readw(a) readw((a))
-#define isa_readl(a) readl((a))
-#define isa_writeb(b,a) writeb(b,(a))
-#define isa_writew(w,a) writew(w,(a))
-#define isa_writel(l,a) writel(l,(a))
-#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
-
-
-static inline int check_signature(unsigned long io_addr,
- const unsigned char *signature, int length)
-{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-
-/**
- * isa_check_signature - find BIOS signatures
- * @io_addr: mmio address to check
- * @signature: signature block
- * @length: length of signature
- *
- * Perform a signature comparison with the ISA mmio address io_addr.
- * Returns 1 on a match.
- *
- * This function is deprecated. New drivers should use ioremap and
- * check_signature.
- */
-
-
-static inline int isa_check_signature(unsigned long io_addr,
- const unsigned char *signature, int length)
-{
- int retval = 0;
- do {
- if (isa_readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-
#endif /* __KERNEL__ */
#ifdef SLOW_IO_BY_JUMPING
#define __iormb() dmb()
#define __iowmb() dmb()
-#endif
+#endif /* _ASM_IO_H */
#include <asm/acpi_s3.h>
#include <asm/acpi_table.h>
#include <asm/post.h>
+#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
static bool omnia_detect_sata(void)
{
struct udevice *bus, *dev;
- int ret;
+ int ret, retry = 3;
u16 mode;
puts("SERDES0 card detect: ");
return false;
}
- ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
- if (ret) {
+ for (; retry > 0; --retry) {
+ ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
+ if (!ret)
+ break;
+ }
+
+ if (!retry) {
puts("I2C read failed! Default PEX\n");
return false;
}
Note that PCIE_ECAM_BASE is set up by the FSP so the value used
by U-Boot matches that value.
+config TARGET_THEADORABLE_X86_CONGA_QA3_E3845
+ bool "theadorable-x86 baseboard & conga-QA3/E3845"
+ help
+ This is the theadorable-x86 baseboard board equipped with the
+ conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
+ micro-SD, USB 2, USB 3, SATA, serial console and HDMI 1.3 video
+ out. It requires some binary blobs - see README.x86 for details.
+
+ Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+ by U-Boot matches that value.
+
endchoice
source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
-if TARGET_CONGA_QEVAL20_QA3_E3845
-
config SYS_BOARD
default "conga-qeval20-qa3-e3845"
default "baytrail"
config SYS_CONFIG_NAME
- default "conga-qeval20-qa3-e3845"
+ default "conga-qeval20-qa3-e3845" if TARGET_CONGA_QEVAL20_QA3_E3845
+ default "theadorable-x86-conga-qa3-e3845" if TARGET_THEADORABLE_X86_CONGA_QA3_E3845
config SYS_TEXT_BASE
default 0xfff00000 if !EFI_STUB
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SPI_FLASH_STMICRO
+ imply SPI_FLASH_SPANSION
+ imply SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xe0000000
-
-endif
S: Maintained
F: board/congatec/conga-qeval20-qa3-e3845
F: include/configs/conga-qeval20-qa3-e3845.h
+F: include/configs/theadorable-x86-conga-qa3-e3845.h
F: configs/conga-qeval20-qa3-e3845_defconfig
F: configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+F: configs/theadorable-x86-conga-qa3-e3845_defconfig
+F: configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
F: arch/x86/dts/conga-qeval20-qa3-e3845.dts
choice
prompt "Mainboard model"
- optional
-config TARGET_DFI_BT700
- bool "DFI BT700 BayTrail"
+config TARGET_Q7X_151_DFI_BT700
+ bool "DFI BT700 BayTrail on DFI Q7X-151 baseboard"
imply SCSI
help
This is the DFI Q7X-151 baseboard equipped with the
Note that PCIE_ECAM_BASE is set up by the FSP so the value used
by U-Boot matches that value.
+config TARGET_THEADORABLE_X86_DFI_BT700
+ bool "DFI BT700 BayTrail on theadorable-x86 baseboard"
+ imply SCSI
+ help
+ This is the theadorable-x86 baseboard equipped with the
+ DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
+ Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
+ USB 3, SATA, serial console and DisplayPort video out.
+ It requires some binary blobs - see README.x86 for details.
+
+ Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+ by U-Boot matches that value.
+
endchoice
source "board/dfi/dfi-bt700/Kconfig"
-if TARGET_DFI_BT700
-
config SYS_BOARD
default "dfi-bt700"
default "baytrail"
config SYS_CONFIG_NAME
- default "dfi-bt700"
+ default "dfi-bt700" if TARGET_Q7X_151_DFI_BT700
+ default "theadorable-x86-dfi-bt700" if TARGET_THEADORABLE_X86_DFI_BT700
config SYS_TEXT_BASE
default 0xfff00000 if !EFI_STUB
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SPI_FLASH_STMICRO
+ imply SPI_FLASH_SPANSION
+ imply SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xe0000000
-
-endif
S: Maintained
F: board/dfi/dfi-bt700
F: include/configs/dfi-bt700.h
+F: include/configs/theadorable-x86-dfi-bt700.h
F: configs/dfi-bt700-q7x-151_defconfig
F: configs/theadorable-x86-dfi-bt700_defconfig
F: arch/x86/dts/dfi-bt700.dtsi
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
-CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_HAVE_ACPI_RESUME=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
CONFIG_E1000=y
-CONFIG_DEBUG_UART_BASE=0x3f8
-CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_X86=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
-CONFIG_TARGET_DFI_BT700=y
-CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_HAVE_ACPI_RESUME=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
CONFIG_E1000=y
-CONFIG_DEBUG_UART_BASE=0x3f8
-CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
--- /dev/null
+CONFIG_X86=y
+CONFIG_VENDOR_CONGATEC=y
+CONFIG_TARGET_THEADORABLE_X86_CONGA_QA3_E3845=y
+CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
+CONFIG_INTERNAL_UART=y
+CONFIG_FLASH_DESCRIPTOR_FILE="descriptor-pcie-x4.bin"
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_INTEL=y
+CONFIG_WINBOND_W83627=y
+CONFIG_E1000=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
--- /dev/null
+CONFIG_X86=y
+CONFIG_VENDOR_CONGATEC=y
+CONFIG_TARGET_THEADORABLE_X86_CONGA_QA3_E3845=y
+CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
+CONFIG_INTERNAL_UART=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_INTEL=y
+CONFIG_WINBOND_W83627=y
+CONFIG_E1000=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_X86=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
-CONFIG_TARGET_DFI_BT700=y
+CONFIG_TARGET_THEADORABLE_X86_DFI_BT700=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_HAVE_ACPI_RESUME=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
#include <asm/arch/soc.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+#include <asm-generic/gpio.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
#define MVPP22_BM_MC_RLS_REG 0x64d4
+#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
/* TX Scheduler registers */
#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
#define MVPP2_MAX_TXD 16
/* Amount of Tx descriptors that can be reserved at once by CPU */
-#define MVPP2_CPU_DESC_CHUNK 64
+#define MVPP2_CPU_DESC_CHUNK 16
/* Max number of Tx descriptors in each aggregated queue */
-#define MVPP2_AGGR_TXQ_SIZE 256
+#define MVPP2_AGGR_TXQ_SIZE 16
/* Descriptor aligned size */
#define MVPP2_DESC_ALIGNED_SIZE 32
struct mii_dev *bus;
int probe_done;
+ u8 num_ports;
};
struct mvpp2_pcpu_stats {
phy_interface_t phy_interface;
int phy_node;
int phyaddr;
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc phy_reset_gpio;
+ struct gpio_desc phy_tx_disable_gpio;
+#endif
int init;
unsigned int link;
unsigned int duplex;
mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
lower_32_bits(bm_pool->dma_addr));
+ if (priv->hw_version == MVPP22)
+ mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
+ (upper_32_bits(bm_pool->dma_addr) &
+ MVPP22_BM_POOL_BASE_HIGH_MASK));
mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
if (err)
goto err_unroll_pools;
- mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
+ mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
}
return 0;
}
}
- mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
- MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
-
return new_pool;
}
val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
/*
* Configure GIG MAC to 1000Base-X mode connected to a fiber
val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
/* configure GIG MAC to SGMII mode */
val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
/* configure GIG MAC to SGMII mode */
val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
port->rxqs[queue] = rxq;
}
- /* Configure Rx queue group interrupt for this port */
- if (priv->hw_version == MVPP21) {
- mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
- CONFIG_MV_ETH_RXQ);
- } else {
- u32 val;
-
- val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
- mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
- val = (CONFIG_MV_ETH_RXQ <<
- MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
- mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
- }
/* Create Rx descriptor rings */
for (queue = 0; queue < rxq_number; queue++) {
{
int port_node = dev_of_offset(dev);
const char *phy_mode_str;
- int phy_node;
+ int phy_node, mdio_off, cp_node;
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
+ u64 mdio_addr;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
+ mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
+
+ /* TODO: This WA for mdio issue. U-boot 2017 don't have
+ * mdio driver and on MACHIATOBin board ports from CP1
+ * connected to mdio on CP0.
+ * WA is to get mdio address from phy handler parent
+ * base address. WA should be removed after
+ * mdio driver implementation.
+ */
+ mdio_addr = fdtdec_get_uint(gd->fdt_blob,
+ mdio_off, "reg", 0);
+
+ cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
+ mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
+ cp_node);
+
+ port->priv->mdio_base = (void *)mdio_addr;
+
+ if (port->priv->mdio_base < 0) {
+ dev_err(&pdev->dev, "could not find mdio base address\n");
+ return -1;
+ }
} else {
phy_node = 0;
}
return -EINVAL;
}
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &port->phy_reset_gpio, GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
+ &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
+#endif
+
/*
* ToDo:
* Not sure if this DT property "phy-speed" will get accepted, so
return 0;
}
+#ifdef CONFIG_DM_GPIO
+/* Port GPIO initialization */
+static void mvpp2_gpio_init(struct mvpp2_port *port)
+{
+ if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
+ dm_gpio_set_value(&port->phy_reset_gpio, 0);
+ udelay(1000);
+ dm_gpio_set_value(&port->phy_reset_gpio, 1);
+ }
+
+ if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
+ dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
+}
+#endif
+
/* Ports initialization */
static int mvpp2_port_probe(struct udevice *dev,
struct mvpp2_port *port,
}
mvpp2_port_power_up(port);
+#ifdef CONFIG_DM_GPIO
+ mvpp2_gpio_init(port);
+#endif
+
priv->port_list[port->id] = port;
+ priv->num_ports++;
return 0;
}
return -EINVAL;
}
- /* MBUS windows configuration */
- dram_target_info = mvebu_mbus_dram_info();
- if (dram_target_info)
- mvpp2_conf_mbus_windows(dram_target_info, priv);
-
if (priv->hw_version == MVPP22)
mvpp2_axi_init(priv);
+ else {
+ /* MBUS windows configuration */
+ dram_target_info = mvebu_mbus_dram_info();
+ if (dram_target_info)
+ mvpp2_conf_mbus_windows(dram_target_info, priv);
+ }
if (priv->hw_version == MVPP21) {
/* Disable HW PHY polling */
if (priv->hw_version == MVPP22)
mvpp2_tx_fifo_init(priv);
- /* Reset Rx queue group interrupt configuration */
- for (i = 0; i < MVPP2_MAX_PORTS; i++) {
- if (priv->hw_version == MVPP21) {
- mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
- CONFIG_MV_ETH_RXQ);
- continue;
- } else {
- u32 val;
-
- val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
- mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
- val = (CONFIG_MV_ETH_RXQ <<
- MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
- mvpp2_write(priv,
- MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
- }
- }
-
if (priv->hw_version == MVPP21)
writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
int pool, rx_bytes, err;
int rx_received;
struct mvpp2_rx_queue *rxq;
- u32 cause_rx_tx, cause_rx, cause_misc;
u8 *data;
- cause_rx_tx = mvpp2_read(port->priv,
- MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
- cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
- cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
- if (!cause_rx_tx && !cause_misc)
- return 0;
-
- cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
-
/* Process RX packets */
- cause_rx |= port->pending_cause_rx;
- rxq = mvpp2_get_rx_queue(port, cause_rx);
+ rxq = port->rxqs[0];
/* Get number of received packets and clamp the to-do */
rx_received = mvpp2_rxq_received(port, rxq->id);
return rx_bytes;
}
-/* Drain Txq */
-static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
- int enable)
-{
- u32 val;
-
- mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
- val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
- if (enable)
- val |= MVPP2_TXQ_DRAIN_EN_MASK;
- else
- val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
- mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
-}
-
static int mvpp2_send(struct udevice *dev, void *packet, int length)
{
struct mvpp2_port *port = dev_get_priv(dev);
tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
} while (tx_done);
- /* Enable TXQ drain */
- mvpp2_txq_drain(port, txq, 1);
-
timeout = 0;
do {
if (timeout++ > 10000) {
tx_done = mvpp2_txq_sent_desc_proc(port, txq);
} while (!tx_done);
- /* Disable TXQ drain */
- mvpp2_txq_drain(port, txq, 0);
-
return 0;
}
int err;
/* Only call the probe function for the parent once */
- if (!priv->probe_done) {
+ if (!priv->probe_done)
err = mvpp2_base_probe(dev->parent);
- priv->probe_done = 1;
- }
port->priv = dev_get_priv(dev->parent);
gop_port_init(port);
}
- /* Initialize network controller */
- err = mvpp2_init(dev, priv);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to initialize controller\n");
- return err;
+ if (!priv->probe_done) {
+ /* Initialize network controller */
+ err = mvpp2_init(dev, priv);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to initialize controller\n");
+ return err;
+ }
+ priv->num_ports = 0;
+ priv->probe_done = 1;
}
err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
struct mvpp2 *priv = port->priv;
int i;
+ priv->num_ports--;
+
+ if (priv->num_ports)
+ return 0;
+
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Common options, macros and default environment for all
+ * theadorable x86 based boards
+ */
+
+#ifndef __THEADORABLE_X86_COMMON_H
+#define __THEADORABLE_X86_COMMON_H
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+
+#define CONFIG_PREBOOT
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_RTL8152
+
+#define VIDEO_IO_OFFSET 0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+
+/* Environment settings */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x006ec000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "tftpdir=" DEF_ENV_TFTPDIR "\0" \
+ "eth_init=" DEF_ENV_ETH_INIT "\0" \
+ "ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0" \
+ "yocto_part=" __stringify(DEF_ENV_YOCTO_PART) "\0" \
+ "ubuntu_tty=" __stringify(DEF_ENV_UBUNTU_TTY) "\0" \
+ "yocto_tty=" __stringify(DEF_ENV_YOCTO_TTY) "\0" \
+ "start_eth=if test -n \"${eth_init}\";" \
+ "then run eth_init;else sleep 0;fi\0" \
+ "kernel-ver=4.8.0-54\0" \
+ "boot=zboot 03000000 0 04000000 ${filesize}\0" \
+ "mtdparts=mtdparts=intel-spi:4k(descriptor),7084k(me)," \
+ "8k(env1),8k(env2),64k(mrc),640k(u-boot)," \
+ "64k(vga),-(fsp)\0" \
+ "addtty_ubuntu=setenv bootargs ${bootargs} " \
+ "console=ttyS${ubuntu_tty},${baudrate}\0" \
+ "addtty_yocto=setenv bootargs ${bootargs} " \
+ "console=ttyS${yocto_tty},${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "intel-spi.writeable=1 vmalloc=300M " \
+ "pci=realloc=on,hpmemsize=0x12000000\0" \
+ "bootcmd=if env exists recovery_status;" \
+ "then run swupdate;" \
+ "else run yocto_boot;run swupdate;" \
+ "fi\0" \
+ "ubuntu_args=setenv bootargs " \
+ "root=/dev/sda${ubuntu_part} ro\0" \
+ "ubuntu_args_quiet=setenv bootargs " \
+ "root=/dev/sda${ubuntu_part} ro quiet\0" \
+ "ubuntu_load=load scsi 0:${ubuntu_part} 03000000 " \
+ "/boot/vmlinuz-${kernel-ver}-generic;" \
+ "load scsi 0:${ubuntu_part} 04000000 " \
+ "/boot/initrd.img-${kernel-ver}-generic\0" \
+ "ubuntu_boot=run ubuntu_args_quiet addmtd addmisc " \
+ "ubuntu_load boot\0" \
+ "ubuntu_boot_console=run ubuntu_args addtty_ubuntu " \
+ "addmtd addmisc ubuntu_load boot\0" \
+ "net_args=setenv bootargs root=/dev/sda${ubuntu_part} ro\0" \
+ "net_boot=run start_eth net_args addtty_yocto addmtd addmisc;" \
+ "tftp 03000000 ${tftpdir}/bzImage;" \
+ "load scsi 0:${ubuntu_part} 04000000 " \
+ "/boot/initrd.img-${kernel-ver}-generic;" \
+ "run boot\0" \
+ "yocto_args=setenv bootargs root=/dev/sda${yocto_part} " \
+ "ip=dhcp panic=1\0" \
+ "yocto_args_fast=setenv bootargs root=/dev/sda${yocto_part} " \
+ "quiet panic=1\0" \
+ "yocto_boot=run yocto_args addmtd addmisc addtty_yocto;" \
+ "if run yocto_load;then zboot 03000000;fi\0" \
+ "yocto_boot_fast=run yocto_args_fast addmtd addmisc " \
+ "addtty_yocto yocto_load;zboot 03000000\0" \
+ "yocto_boot_tftp=run yocto_args addmtd addmisc addtty_yocto " \
+ "start_eth yocto_load_tftp;zboot 03000000\0" \
+ "yocto_kernel=bzImage\0" \
+ "yocto_load=load scsi 0:${yocto_part} 03000000 " \
+ "/boot/${yocto_kernel}\0" \
+ "yocto_load_tftp=tftp 03000000 dfi/bzImage\0" \
+ "swupdate=if env exists swupdate_factory;" \
+ "then run swupdate_usb;run swupdate_run;" \
+ "else setenv swupdate_part 2;run swupdate_mmc;" \
+ "run swupdate_run;setenv swupdate_part 1;" \
+ "run swupdate_mmc;run swupdate_usb;" \
+ "run swupdate_run;" \
+ "fi\0" \
+ "swupdate-initrd=/boot/swupdate-image-theadorable.ext4.gz\0" \
+ "swupdate-kernel=/boot/bzImage\0" \
+ "swupdate_args=setenv bootargs root=/dev/ram rw ip=dhcp panic=1\0" \
+ "swupdate_dev=0\0" \
+ "swupdate_factory=0\0" \
+ "swupdate_interface=usb\0" \
+ "swupdate_kernel=vmlinuz-4.4.0-28-generic\0" \
+ "swupdate_load=load ${swupdate_interface} ${swupdate_dev}:" \
+ "${swupdate_part} 03000000 ${swupdate-kernel}" \
+ " && load ${swupdate_interface} ${swupdate_dev}:" \
+ "${swupdate_part} 04000000 ${swupdate-initrd}\0" \
+ "swupdate_mmc=setenv swupdate_interface mmc;" \
+ "setenv swupdate_dev ${swupdate_mmcdev};" \
+ "setenv swupdate_part 1;" \
+ "mmc dev ${swupdate_dev};mmc rescan\0" \
+ "swupdate_mmcdev=0\0" \
+ "swupdate_part=1\0" \
+ "swupdate_run=run swupdate_args addtty_yocto addmtd addmisc;" \
+ "if run swupdate_load;then run boot;" \
+ "else echo SWUpdate cannot be started from " \
+ "${swupdate_interface};" \
+ "fi\0" \
+ "swupdate_usb=setenv swupdate_interface usb;" \
+ "setenv swupdate_dev 0;setenv swupdate_part 1;" \
+ "usb start\0" \
+ "logo_tftp=tftp ${loadaddr} ${tftpdir}/logo.bmp;" \
+ "bmp display ${loadaddr}\0" \
+ "preboot=scsi scan;load scsi 0:${ubuntu_part} ${loadaddr} " \
+ "/boot/logo/logo.bmp;bmp display ${loadaddr}\0" \
+ "rootpath=/tftpboot/theadorable-x86-conga/work/" \
+ "rootfs-yocto-swupdate-2017-03-29\0" \
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+ "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+ "set_bootargs_nfs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},tcp,nfsvers=3\0" \
+ "net_nfs=run start_eth set_bootargs_nfs addtty_yocto addip " \
+ "addmtd addmisc;tftp 03000000 ${tftpdir}/bzImage;" \
+ "zboot 03000000\0" \
+ "load_uboot=tftp ${loadaddr} ${tftpdir}/u-boot.rom\0" \
+ "update_uboot=sf probe;" \
+ "sf update ${loadaddr} 0 800000;saveenv\0" \
+ "upd_uboot=run start_eth load_uboot update_uboot\0"
+
+#endif /* __THEADORABLE_X86_COMMON_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+/* Set the board specific parameters */
+#define DEF_ENV_TFTPDIR "theadorable-x86-conga"
+#define DEF_ENV_ETH_INIT ""
+#define DEF_ENV_UBUNTU_PART 2
+#define DEF_ENV_UBUNTU_TTY 0 /* Use ttyS0 */
+#define DEF_ENV_YOCTO_PART 3
+#define DEF_ENV_YOCTO_TTY 0 /* Use ttyS0 */
+
+/*
+ * Include the theadorable-x86 common options, macros and default
+ * environment
+ */
+#include <configs/theadorable-x86-common.h>
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+/* Use BayTrail internal HS UART which is memory-mapped */
+#undef CONFIG_SYS_NS16550_PORT_MAPPED
+
+/* Set the board specific parameters */
+#define DEF_ENV_TFTPDIR "theadorable-x86-dfi"
+#define DEF_ENV_ETH_INIT "usb reset"
+#define DEF_ENV_UBUNTU_PART 1
+#define DEF_ENV_UBUNTU_TTY 4 /* Use ttyS4 */
+#define DEF_ENV_YOCTO_PART 2
+#define DEF_ENV_YOCTO_TTY 1 /* Use ttyS1 */
+
+/*
+ * Include the theadorable-x86 common options, macros and default
+ * environment
+ */
+#include <configs/theadorable-x86-common.h>
+
+#endif /* __CONFIG_H */
#define FLASH_CFI_BY16 0x02
#define FLASH_CFI_BY32 0x04
#define FLASH_CFI_BY64 0x08
-/* convert between bit value and numeric value */
-#define CFI_FLASH_SHIFT_WIDTH 3
/*
* Values for the flash device interface
*/
projects / u-boot / commitdiff