void at91_periph_clk_enable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 regval;
- if (id > 31)
- writel(1 << (id - 32), &pmc->pcer1);
- else
- writel(1 << id, &pmc->pcer);
+ if (id > AT91_PMC_PCR_PID_MASK)
+ return;
+
+ regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
+
+ writel(regval, &pmc->pcr);
+}
+
+void at91_periph_clk_disable(int id)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 regval;
+
+ if (id > AT91_PMC_PCR_PID_MASK)
+ return;
+
+ regval = AT91_PMC_PCR_CMD_WRITE | id;
+
+ writel(regval, &pmc->pcr);
}
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#define AT91_PMC_IXR_MOSCSELS 0x00010000
+#define AT91_PMC_PCR_PID_MASK (0x3f)
+#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
+#define AT91_PMC_PCR_EN (0x1 << 28)
+
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
int at91_clock_init(unsigned long main_clock);
void at91_periph_clk_enable(int id);
+void at91_periph_clk_disable(int id);
#endif /* __ASM_ARM_ARCH_CLK_H__ */