config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
- default y if ARCH_SUNXI || TEGRA
- default y if ARCH_LS2080A
- default y if ARCH_MESON
- default y if ARCH_ROCKCHIP
- default n
imply USE_BOOTCOMMAND
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP if CMD_NET
select CMD_PING if CMD_NET
select CMD_PXE if NET
+ select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
endif # FIT
+config IMAGE_FORMAT_LEGACY
+ bool "Enable support for the legacy image format"
+ default y if !FIT_SIGNATURE
+ help
+ This option enables the legacy image format. It is enabled by
+ default for backward compatibility, unless FIT_SIGNATURE is
+ set where it is disabled so that unsigned images cannot be
+ loaded. If a board needs the legacy image format support in this
+ case, enable it here.
+
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
+# change __FILE__ to the relative path from the srctree
+KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
+
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
endif
KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+ifeq ($(cc-name),clang)
+KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
+KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
+KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
+KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
+KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
+endif
# turn jbsr into jsr for m68k
ifeq ($(ARCH),m68k)
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
-- legacy image format:
- CONFIG_IMAGE_FORMAT_LEGACY
- enables the legacy image format support in U-Boot.
-
- Default:
- enabled if CONFIG_FIT_SIGNATURE is not defined.
-
- CONFIG_DISABLE_IMAGE_LEGACY
- disable the legacy image format
-
- This define is introduced, as the legacy image format is
- enabled per default for backward compatibility.
-
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
#include <linux/types.h>
#include <api_public.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG
#undef DEBUG
select DM_GPIO
select DM_MMC
select HAVE_BLOCK_DEVICE
+ select SPI
select LZO
imply CMD_GETTIME
imply CMD_HASH
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+config SYS_ARCH_TIMER
+ bool "ARM Generic Timer support"
+ depends on CPU_V7 || ARM64
+ default y if ARM64
+ help
+ The ARM Generic Timer (aka arch-timer) provides an architected
+ interface to a timer source on an SoC.
+ It is mandantory for ARMv8 implementation and widely available
+ on ARMv7 systems.
+
config ARM_SMCCC
bool "Support for ARM SMC Calling Convention (SMCCC)"
depends on CPU_V7 || ARM64
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select SPI
config TARGET_DEVKIT3250
bool "Support devkit3250"
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select SPI
select SPI_FLASH
select PL01X_SERIAL
select DM_SPI
select DM_GPIO
select DM_KEYBOARD
+ select SPI
imply FAT_WRITE
config ARCH_S5PC1XX
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
+ select SYS_ARCH_TIMER
imply CMD_MTDPARTS
imply FIT
imply CMD_SAVES
config ARCH_MESON
bool "Amlogic Meson"
+ imply DISTRO_DEFAULTS
help
Support for the Meson SoC family developed by Amlogic Inc.,
targeted at media players and tablet computers. We currently
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
imply CMD_GPT
+ imply DISTRO_DEFAULTS
imply FAT_WRITE
imply OF_LIBFDT_OVERLAY
imply PRE_CONSOLE_BUFFER
select CLK
select SPL_CLK if SPL
select CLK_ZYNQ
+ select SPI
imply CMD_CLK
imply FAT_WRITE
imply CMD_SPL
config TEGRA
bool "NVIDIA Tegra"
+ imply DISTRO_DEFAULTS
imply FAT_WRITE
config TARGET_VEXPRESS64_AEMV8A
select DM_PWM
select DM_REGULATOR
select ENABLE_ARM_SOC_BOOT0_HOOK
+ select SPI
imply CMD_FASTBOOT
+ imply DISTRO_DEFAULTS
imply FASTBOOT
imply FAT_WRITE
imply USB_FUNCTION_FASTBOOT
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
+ imply SYS_NS16550
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# LLVM support
-LLVMS_RELFLAGS := $(call cc-option,-mllvm,) \
- $(call cc-option,-target arm-none-eabi,) \
- $(call cc-option,-arm-use-movt=0,)
+LLVM_RELFLAGS := $(call cc-option,-mllvm,) \
+ $(call cc-option,-mno-movt,)
PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
PLATFORM_CPPFLAGS += -D__ARM__
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-DECLARE_GLOBAL_DATA_PTR;
-
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)TIMER
-obj-y += generic_timer.o
+obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
obj-y += exceptions.o
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
+ imply DISTRO_DEFAULTS
imply PANIC_HANG
config FSL_LSCH2
#endif
#include <fsl_immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#include <asm/arch/mc_me_regs.h>
#include "cpu.h"
-DECLARE_GLOBAL_DATA_PTR;
-
u32 cpu_mask(void)
{
return readl(MC_ME_CS);
#include <common.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);
#include "r8a7790-lager.dts"
#include "r8a7790-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
#include "r8a7793-gose.dts"
#include "r8a7793-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
#include "r8a7794-alt.dts"
#include "r8a7794-u-boot.dtsi"
+
+&scif2 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&cru {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+&timer3 {
+ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+ u-boot,dm-spl;
+ clock-frequency = <24000000>;
+};
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
+#include "rk3188-radxarock-u-boot.dtsi"
/ {
model = "Radxa Rock";
status = "okay";
};
-&uart2 {
- status = "okay";
- u-boot,dm-spl;
-};
-
&uart3 {
status = "okay";
};
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
- u-boot,dm-spl;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
+ timer3: timer@2000e000 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x2000e000 0x20>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-spl;
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
#include <asm/arch/clock.h>
#include <asm/ti-common/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Structure for Iodelay configuration registers.
* Theoretical max for g_delay is 21560 ps.
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* ARMv7M does not support ARM instruction mode. However, the
* interworking BLX and BX instructions do encode the ARM/Thumb
select DM_SPI
select DM_GPIO
select DM_ETH
+ select SPI
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
select SUPPORT_SPL
select DM
select DM_SPI
+ select SPI
config TARGET_MEESC
bool "Support meesc"
select DM_SPI
select DM_GPIO
select DM_ETH
+ select SPI
config TARGET_SMARTWEB
bool "Support smartweb"
select SUPPORT_SPL
select DM
select DM_SPI
+ select SPI
config TARGET_WB45N
bool "Support Laird WB45N"
#include <asm/arch/clk.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static void switch_to_main_crystal_osc(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#include <spi_flash.h>
#include <mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
void puts(const char *str)
{
#define FSYS1_MMC0_DIV_MASK 0xff0f
#define FSYS1_MMC0_DIV_VAL 0x0701
-DECLARE_GLOBAL_DATA_PTR;
-
struct arm_clk_ratios arm_clk_ratios[] = {
#ifdef CONFIG_EXYNOS5420
{
#include <common.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_EXYNOS7420
static struct mm_region exynos7420_mem_map[] = {
{
#include <asm/arch/clock.h>
#include <mapmem.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
* @src: - Address of data to be encapsulated
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
+ select SYS_ARCH_TIMER
endchoice
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define PCC_CLKSRC_TYPES 2
#define PCC_CLKSRC_NUM 7
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
scg_p scg1_regs = (scg_p)SCG1_RBASE;
static u32 scg_src_get_rate(enum scg_clk clksrc)
#include <errno.h>
#include <linux/iopoll.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 decode_frac_pll(enum clk_root_src frac_pll)
#include <asm/io.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
static struct clk_root_map root_array[] = {
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
-DECLARE_GLOBAL_DATA_PTR;
-
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Armada 3700 */
#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
#include <ahci.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Dummy implementation that can be overwritten by a board
* specific function
#include <asm/io.h>
#include <asm/arch/soc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define TIMER_LOAD_VAL 0xffffffff
static int init_done __attribute__((section(".data"))) = 0;
void spl_board_init(void)
{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
/* Prepare console output */
preloader_console_init();
-
+#endif
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
#include <asm/omap_common.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
#include <asm/emif.h>
#include <asm/omap_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO
depends on ARCH_QEMU
select CPU_V7
select ARCH_SUPPORT_PSCI
+ select SYS_ARCH_TIMER
config TARGET_QEMU_ARM_64BIT
bool "Support qemu_arm64"
bool "Gose board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_KOELSCH
bool "Koelsch board"
bool "Lager board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_KZM9G
bool "KZM9D board"
bool "Alt board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_SILK
bool "Silk board"
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT
- select SYS_NS16550
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
ifndef CONFIG_ARM64
+ifndef CONFIG_ROCKCHIP_RK3188
obj-y += rk_timer.o
endif
+endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
# pip install pyelftools
from elftools.elf.elffile import ELFFile
-from elftools.elf.sections import SymbolTableSection
-from elftools.elf.segments import Segment, InterpSegment, NoteSegment
ELF_SEG_P_TYPE='p_type'
ELF_SEG_P_PADDR='p_paddr'
#include <asm/arch/timer.h>
#include <asm/arch/uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0x20008000
#define DEBUG_UART_BASE 0x20068000
hang();
}
- rockchip_timer_init();
-
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);
#include <asm/gpio.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_late_init(void)
{
struct rk3188_grf *grf;
{
return BOOT_DEVICE_MMC1;
}
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0x11000000
#define SGRF_BASE 0x10140000
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0xff770000
void board_init_f(ulong dummy)
{
#include <asm/arch/periph.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_debug_uart_init(void)
{
}
#include <asm/arch/timer.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
#include <spl.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#include <dm.h>
#include <asm/arch/clock_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
#include <asm/arch/freeze_controller.h>
#include <linux/errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
#define SCANMGR_STAT_ACTIVE (1 << 31)
#define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
select CPU_V7
select PINCTRL_STM32
select STM32_RESET
+ select SYS_ARCH_TIMER
select SYSRESET_SYSCON
help
target STMicroelectronics SOC STM32MP1 family
}
#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
#endif
/* The sunxi internal brom will try to loader external bootloader
#include <asm/arch/dram.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
/*
select DM_SPI
select DM_SPI_FLASH
select MISC
+ select SPI
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
select BOARD_EARLY_INIT_F
#include <common.h>
#include <asm/arch/tegra.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_early_init_f(void)
{
return 0;
#include <asm/arch/tegra.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern unsigned long nvtboot_boot_x0;
/*
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_ZYNQ_DDRC_INIT
void zynq_ddrc_init(void) {}
#else
#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_init_f(ulong dummy)
{
ps7_init();
#include <asm/io.h>
#include <asm/u-boot.h>
-DECLARE_GLOBAL_DATA_PTR;
-
bool boot_linux;
u32 spl_boot_device(void)
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
#include <fsl_qe.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
* For deriving usb clock from 100MHz sysclk, reference divisor is set
#include <fdt_support.h>
#include <asm/mp.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
* on our cache or tlb entries.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
struct exception_table_entry
{
unsigned long insn, fixup;
{ 0x300, SIGSEGV }, /* address error (store) */
{ 0x400, SIGBUS }, /* instruction bus error */
{ 0x500, SIGINT }, /* interrupt */
- { 0x600, SIGBUS }, /* alingment */
+ { 0x600, SIGBUS }, /* alignment */
{ 0x700, SIGTRAP }, /* breakpoint trap */
{ 0x800, SIGFPE }, /* fpu unavail */
{ 0x900, SIGALRM }, /* decrementer */
#include <image.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This function jumps to an image with argument. Normally an FDT or ATAGS
* image.
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
#include <common.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818
struct arm_z_header {
#include <asm/io.h>
#include <asm/pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
#include <qfw.h>
#include <asm/cpu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
{
if (size < CPU_MAX_NAME_LEN)
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Miscellaneous platform dependent initializations
*/
#include <common.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Global declaration of gd */
struct global_data *global_data_ptr;
#include <common.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
UCLASS_DRIVER(lpc) = {
.id = UCLASS_LPC,
.name = "lpc",
#include <linux/compiler.h>
#include <linux/libfdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Memory lay-out:
*
#include <asm/io.h>
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_VIDEO_MXS
#define LCD_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
#include <asm/io.h>
#include "fpga.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int altera_pre_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
#include "platinum.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
#include "platinum.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
{
struct pt_regs regs;
#include "pinmux-config-cei-tk1-som.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
#include <fsl_esdhc.h>
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_FSL_ESDHC
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
#include <fsl_esdhc.h>
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum ddr_config {
DDR_16BIT_256MB,
DDR_32BIT_512MB,
#include <power/tps65218.h>
#include "board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum display_type {
NONE,
DVI,
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#include "../common/board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
#include "../common/board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#include <asm/fsl_i2c.h>
#include "vme8349pin.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_DDR_RAW_TIMING
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
#endif
#include "vid.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
MUX_TYPE_CAN,
MUX_TYPE_IIC2,
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
#include <asm/io.h>
#include <asm/immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <asm/io.h>
#include <asm/immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#include <asm/fsl_i2c.h>
#include "../common/pq-mds-pib.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include "../common/ngpixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Hynix H5TQ1G83TFR-H9C
#include "gsc.h"
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
#include <miiphy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_MUX_CHANNELS 2
enum {
#include <miiphy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_MUX_CHANNELS 2
enum {
#include "../common/dp501.h"
#include "controlcenterd-id.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
HWVER_100 = 0,
HWVER_110 = 1,
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
return 0;
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.base = CONFIG_SYS_USB_OTG_BASE,
#include "../common/common.h"
#include "kmp204x.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
#include "novena.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL \
(PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
printf("Board: MPC8308 P1M\n");
#include "pinmux-config-jetson-tk1.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
#include <asm/ehci-omap.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
#include <mach/ath79.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#include <mach/ath79.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := alt.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := alt_spl.o
+else
+obj-y := alt.o qos.o
+endif
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF2_MSTP719 (1 << 19)
-#define ETHER_MSTP813 (1 << 13)
-#define IIC1_MSTP323 (1 << 23)
-#define MMC0_MSTP315 (1 << 15)
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP312 (1 << 12)
+#define TMU0_MSTP125 BIT(25)
+#define MMC0_MSTP315 BIT(15)
#define SD1CKCR 0xE6150078
-#define SD1_97500KHZ 0x7
+#define SD_97500KHZ 0x7
int board_early_init_f(void)
{
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF2 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* IIC1 / sh-i2c ch1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
-
-#ifdef CONFIG_SH_MMCIF
- /* MMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
-#endif
-
-#ifdef CONFIG_SH_SDHI
- /* SDHI0, 1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
-
- /*
- * SD0 clock is set to 97.5MHz by default.
- * Set SD1 to the 97.5MHz as well.
- */
- writel(SD1_97500KHZ, SD1CKCR);
-#endif
return 0;
}
+#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7794_pinmux_init();
-
- /* Ether Enable */
-#if defined(CONFIG_R8A7794_ETHERNET_B)
- gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
- gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
- gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
- gpio_request(GPIO_FN_ETH_LINK_B, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
- gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
- gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
- gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
- gpio_request(GPIO_FN_ETH_MDC_B, NULL);
-#else
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
-#endif
- gpio_request(GPIO_FN_IRQ8, NULL);
-
- /* PHY reset */
- gpio_request(GPIO_GP_1_24, NULL);
- gpio_direction_output(GPIO_GP_1_24, 0);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
mdelay(20);
- gpio_set_value(GPIO_GP_1_24, 1);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
udelay(1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
-#ifdef CONFIG_SH_ETHER
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-
- return ret;
-#else
return 0;
-#endif
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
- gpio_request(GPIO_GP_4_31, NULL);
- gpio_set_value(GPIO_GP_4_31, 1);
-
- ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD1_DATA0, NULL);
- gpio_request(GPIO_FN_SD1_DATA1, NULL);
- gpio_request(GPIO_FN_SD1_DATA2, NULL);
- gpio_request(GPIO_FN_SD1_DATA3, NULL);
- gpio_request(GPIO_FN_SD1_CLK, NULL);
- gpio_request(GPIO_FN_SD1_CMD, NULL);
- gpio_request(GPIO_FN_SD1_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_request(GPIO_GP_2_29, NULL);
- gpio_direction_output(GPIO_GP_2_26, 1);
- gpio_direction_output(GPIO_GP_2_29, 1);
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
+ fdtdec_setup_memory_banksize();
- /* SDHI 1 */
- gpio_request(GPIO_GP_4_26, NULL);
- gpio_request(GPIO_GP_4_29, NULL);
- gpio_direction_output(GPIO_GP_4_26, 1);
- gpio_direction_output(GPIO_GP_4_29, 1);
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
-#endif
- return ret;
+ return 0;
}
-int dram_init(void)
+/* KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 1;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
- i2c_set_bus_num(1); /* PowerIC connected to ch1 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
+
+ data |= BIT(1);
+
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF2_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(alt_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
--- /dev/null
+/*
+ * board/renesas/alt/alt_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF2_MSTP719 BIT(19)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD1CKCR 0xE6150078
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00000000 },
+ { 0x0094, 0x00000000 },
+ { 0x0098, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x40000000 },
+ { 0x002c, 0x00000155 },
+ { 0x0030, 0x00000002 },
+ { 0x0034, 0x00000000 },
+ { 0x0038, 0x00000000 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x60000000 },
+ { 0x0044, 0x36dab6db },
+ { 0x0048, 0x926da012 },
+ { 0x004c, 0x0008c383 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000140 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x5bffffff },
+ { 0x0010, 0x01bfe1ff },
+ { 0x0014, 0x5bffffff },
+ { 0x0018, 0x0f4b200f },
+ { 0x001c, 0x03ffffff },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0x00000000 },
+ { 0x0104, 0x4203fc00 },
+ { 0x0108, 0x00000000 },
+ { 0x010c, 0x159007ff },
+ { 0x0110, 0x80000000 },
+ { 0x0114, 0x00de481f },
+ { 0x0118, 0x00000000 },
+ };
+
+ static const struct reg_config pfc_with_unlock2[] = {
+ { 0x0060, 0xffffffff },
+ { 0x0064, 0xfffff000 },
+ { 0x0068, 0x55555500 },
+ { 0x006c, 0xffffff00 },
+ { 0x0070, 0x00000000 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
+ writel(~pfc_with_unlock2[i].val, pfc_base);
+ writel(pfc_with_unlock2[i].val,
+ pfc_base | pfc_with_unlock2[i].off);
+ }
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x24000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x0004c000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x01000000 },
+ { 0x2000, 0x24000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x0084c380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x00000009 },
+ { 0x0044, 0x00000007 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x00000009 },
+ { 0x0054, 0x000a0009 },
+ { 0x0058, 0x00000021 },
+ { 0x005c, 0x00000018 },
+ { 0x0060, 0x00000005 },
+ { 0x0064, 0x0000001b },
+ { 0x0068, 0x00000007 },
+ { 0x006c, 0x0000000a },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000010 },
+ { 0x0078, 0x000000ae },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x50213005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082008 },
+ { 0x0380, 0x00020003 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c4e1 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcb6d0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x85589955 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a852400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300210b4 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000b50 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000010 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081450 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
#
-# board/renesas/alt/Makefile
+# board/renesas/gose/Makefile
#
# Copyright (C) 2014 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := gose.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := gose_spl.o
+else
+obj-y := gose.o qos.o
+endif
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
-
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP312 (1 << 12)
-#define SDHI2_MSTP311 (1 << 11)
+#define TMU0_MSTP125 BIT(25)
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE615026C
int board_early_init_f(void)
{
- /* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* SDHI */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
- SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD1 and SD2 to the 97.5MHz as well.
+ */
writel(SD_97500KHZ, SD1CKCR);
writel(SD_97500KHZ, SD2CKCR);
return 0;
}
-#define PUPR5 0xE6060114
-#define PUPR5_ETH 0x3FFC0000
-#define PUPR5_ETH_MAGIC (1 << 27)
+#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7793_pinmux_init();
-
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
- gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
- gpio_direction_output(GPIO_GP_5_22, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_22, 1);
- udelay(1);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
-#ifdef CONFIG_SH_ETHER
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-#endif
-
- return ret;
+ return 0;
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DATA0, NULL);
- gpio_request(GPIO_FN_SD2_DATA1, NULL);
- gpio_request(GPIO_FN_SD2_DATA2, NULL);
- gpio_request(GPIO_FN_SD2_DATA3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_7_17, NULL);
- gpio_request(GPIO_GP_2_12, NULL);
- gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI 1 */
- gpio_request(GPIO_GP_7_18, NULL);
- gpio_request(GPIO_GP_2_13, NULL);
- gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
- if (ret)
- return ret;
-
- /* SDHI 2 */
- gpio_request(GPIO_GP_7_19, NULL);
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
+ fdtdec_setup_memory_banksize();
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
+ return 0;
}
-int dram_init(void)
+/* KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 6;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
+
+ data |= BIT(1);
- i2c_set_bus_num(2); /* PowerIC connected to ch2 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(gose_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
--- /dev/null
+/*
+ * board/renesas/gose/gose_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x60000000 },
+ { 0x0094, 0x60000000 },
+ { 0x0098, 0x00800200 },
+ { 0x009c, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x000244c8 },
+ { 0x002c, 0x00000000 },
+ { 0x0030, 0x00002400 },
+ { 0x0034, 0x01520000 },
+ { 0x0038, 0x00724003 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x00000000 },
+ { 0x0048, 0x00000000 },
+ { 0x004c, 0x00000000 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000000 },
+ { 0x0058, 0x00000000 },
+ { 0x005c, 0x00000000 },
+ { 0x0160, 0x00000000 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x3bc001e7 },
+ { 0x0010, 0x5bffffff },
+ { 0x0014, 0x1ffffffb },
+ { 0x0018, 0x01bffff0 },
+ { 0x001c, 0xcf7fffff },
+ { 0x0074, 0x0381fc00 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0xffffffdf },
+ { 0x0104, 0xc883c3ff },
+ { 0x0108, 0x1201f3c9 },
+ { 0x010c, 0x00000000 },
+ { 0x0110, 0xffffeb04 },
+ { 0x0114, 0xc003ffff },
+ { 0x0118, 0x0800000f },
+ { 0x011c, 0x001800f0 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x04381000 },
+ { 0x5000, 0x00000000 },
+ { 0x5800, 0x000e0000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x2000, 0x04381010 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00000000 },
+ { 0x5000, 0x00400000 },
+ { 0x5400, 0x00000000 },
+ { 0x5800, 0x000e0380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0280, 0x0000a55a },
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0001c000 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20042004 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c561 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcdb60 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := lager.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := lager_spl.o
+else
+obj-y := lager.o qos.o
+endif
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
-#define MMC1_MSTP305 (1 << 5)
+#define TMU0_MSTP125 BIT(25)
-#define MSTPSR3 0xE6150048
-#define SMSTPCR3 0xE615013C
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP313 (1 << 13)
-#define SDHI2_MSTP312 (1 << 12)
-
-#define SD2CKCR 0xE6150078
-#define SD2_97500KHZ 0x7
+#define SD1CKCR 0xE6150078
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
int board_early_init_f(void)
{
- /* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
- /* eMMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
- /* SDHI0, 2 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
/*
* SD0 clock is set to 97.5MHz by default.
- * Set SD2 to the 97.5MHz as well.
+ * Set SD1 and SD2 to the 97.5MHz as well.
*/
- writel(SD2_97500KHZ, SD2CKCR);
+ writel(SD_97500KHZ, SD1CKCR);
+ writel(SD_97500KHZ, SD2CKCR);
return 0;
}
-DECLARE_GLOBAL_DATA_PTR;
+#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7790_pinmux_init();
-
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
- gpio_direction_output(GPIO_GP_5_31, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_31, 1);
- udelay(1);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_ETHER
- u32 val;
- unsigned char enetaddr[6];
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
+ return 0;
+}
-#endif
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
- return ret;
+ return 0;
}
-/* lager has KSZ8041NL/RNL */
-#define PHY_CONTROL1 0x1E
-#define PHY_LED_MODE 0xC0000
+/* KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
#define PHY_LED_MODE_ACK 0x4000
int board_phy_config(struct phy_device *phydev)
{
return 0;
}
-int board_mmc_init(bd_t *bis)
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_ARCH_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
- gpio_request(GPIO_FN_MMC1_D0, NULL);
- gpio_request(GPIO_FN_MMC1_D1, NULL);
- gpio_request(GPIO_FN_MMC1_D2, NULL);
- gpio_request(GPIO_FN_MMC1_D3, NULL);
- gpio_request(GPIO_FN_MMC1_D4, NULL);
- gpio_request(GPIO_FN_MMC1_D5, NULL);
- gpio_request(GPIO_FN_MMC1_D6, NULL);
- gpio_request(GPIO_FN_MMC1_D7, NULL);
- gpio_request(GPIO_FN_MMC1_CLK, NULL);
- gpio_request(GPIO_FN_MMC1_CMD, NULL);
-
- ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DAT0, NULL);
- gpio_request(GPIO_FN_SD2_DAT1, NULL);
- gpio_request(GPIO_FN_SD2_DAT2, NULL);
- gpio_request(GPIO_FN_SD2_DAT3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
+ struct udevice *dev;
+ const u8 pmic_bus = 2;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
- /*
- * SDHI 0
- * need JP3 set to pin-1 side on board.
- */
- gpio_request(GPIO_GP_5_24, NULL);
- gpio_request(GPIO_GP_5_29, NULL);
- gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
- gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
if (ret)
- return ret;
+ hang();
- /* SDHI 2 */
- gpio_request(GPIO_GP_5_25, NULL);
- gpio_request(GPIO_GP_5_30, NULL);
- gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
- gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */
+ data |= BIT(1);
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-
-int dram_init(void)
+enum env_location env_get_location(enum env_operation op, int prio)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ const u32 load_magic = 0xb33fc0de;
- return 0;
-}
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
-const struct rmobile_sysinfo sysinfo = {
- CONFIG_ARCH_RMOBILE_BOARD_STRING
-};
-
-void reset_cpu(ulong addr)
-{
- u8 val;
+ if (prio)
+ return ENVL_UNKNOWN;
- i2c_set_bus_num(3); /* PowerIC connected to ch3 */
- i2c_init(400000, 0);
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ return ENVL_SPI_FLASH;
}
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
-
-U_BOOT_DEVICE(lager_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
--- /dev/null
+/*
+ * board/renesas/lager/lager_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00000000 },
+ { 0x0094, 0x00000000 },
+ { 0x0098, 0xc0000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x20000000 },
+ { 0x0030, 0x00001249 },
+ { 0x0034, 0x00000278 },
+ { 0x0038, 0x00000841 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x10000000 },
+ { 0x0048, 0x00000001 },
+ { 0x004c, 0x0004aab0 },
+ { 0x0050, 0x37301b00 },
+ { 0x0054, 0x00048da3 },
+ { 0x0058, 0x089044a1 },
+ { 0x005c, 0x2a3a55b4 },
+ { 0x0160, 0x00000003 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x2aef3fff },
+ { 0x000c, 0x3fffffff },
+ { 0x0010, 0xff7fc07f },
+ { 0x0014, 0x7f3ff3f8 },
+ { 0x0018, 0x1cfdfff7 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0x1fffffff },
+ { 0x0104, 0xffff0318 },
+ { 0x0108, 0x387fffe1 },
+ { 0x010c, 0x00803f80 },
+ { 0x0110, 0x1520009f },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x00000000 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x3000, 0x4000, 0x5000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0x63020000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0xe3020000 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x02150326 },
+ { 0x38, 0x077f077f },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181ee4 },
+ { 0x0290, 0x00000060 },
+ { 0x02a0, 0x330657b2 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000071 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x10030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000005 },
+ { 0x0064, 0x00000018 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000300 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082008 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000000f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c481 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fdb6c0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d5cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868300 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
{
struct udevice *dev;
const u8 pmic_bus = 1;
- const u8 pmic_addr = 0x58;
+ const u8 pmic_addr = 0x5a;
u8 data;
int ret;
#include <asm/arch/uart.h>
#include <asm/arch/sdram_rk3036.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
#include <asm/io.h>
#include <asm/arch/uart.h>
-DECLARE_GLOBAL_DATA_PTR;
#include <power/regulator.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
struct udevice *pinctrl, *regulator;
#include <asm/arch/sdram_rk3036.h>
#include <asm/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
#include <asm/arch/grf_rk3368.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int mach_cpu_init(void)
{
return 0;
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int exynos_init(void)
{
return 0;
#include <asm/arch/pinmux.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 get_board_rev(void)
{
return 0;
#include "setup.h"
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int board_rev;
#ifdef CONFIG_REVISION_TAG
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static unsigned int board_rev = -1;
static inline u32 get_model_rev(void);
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <linux/libfdt.h>
#include <fdt_support.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void local_bus_init(void);
int board_early_init_f (void)
#include "../common/factoryset.h"
#include <nand.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SPL_BUILD
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
#include <nand.h>
#include <bmp_layout.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
#include "../common/factoryset.h"
#include "../../../drivers/video/da8xx-fb.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Read header information from EEPROM into global structure.
*/
#include <asm/arch/timer.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int mach_cpu_init(void)
{
return 0;
#include <power/regulator.h>
#include <u-boot/sha256.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
int ret;
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
+#endif
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 125000000,
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
#include <fsl_dcu_fb.h>
#include "div64.h"
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
#include <mach/ddr.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_USB
static void wdr4300_usb_start(void)
{
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include "tqma6_bb.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
#include "cyrus.h"
#include "../common/eeprom.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define GPIO_OPENDRAIN 0x30000000
#define GPIO_DIR 0x3c000004
#define GPIO_INITIAL 0x30000000
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
#include <fdt_support.h>
#include <pca953x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_board_pci_setup(void *blob, bd_t *bd);
static void flash_cs_fixup(void)
#include <fdt_support.h>
#include <pca953x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_board_pci_setup(void *blob, bd_t *bd);
static void flash_cs_fixup(void)
config CMD_LOG
bool "log - Generation, control and access to logging"
+ select LOG
help
This provides access to logging features. It allows the output of
log data to be controlled to a limited extent (setting up the default
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* do_aes() - Handle the "aes" command-line command
* @cmdtp: Command data struct pointer
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* blob_decap() - Decapsulate the data as a blob
* @key_mod: - Pointer to key modifier/key
#include <linux/kernel.h>
#include <linux/sizes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Image booting support
*/
/* Note: depends on enum ec_current_image */
static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* Decode a flash region parameter
*
void eeprom_init(int bus)
{
/* SPI EEPROM */
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+#if defined(CONFIG_MPC8XX_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_init_f();
#endif
int ret = 0;
/* SPI */
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+#if defined(CONFIG_MPC8XX_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
if (read)
spi_read(addr, alen, buffer, len);
else
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Display values from last command.
* Memory modify remembered values are different from display memory.
*/
config LOG
bool "Enable logging support"
+ select DM
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or
#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI)
static int initr_spi(void)
{
- /* PPC does this here */
-#ifdef CONFIG_SPI
+ /* MPC8xx does this here */
+#ifdef CONFIG_MPC8XX_SPI
#if !defined(CONFIG_ENV_IS_IN_EEPROM)
spi_init_f();
#endif
#include <dm.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct cros_ec_dev *board_get_cros_ec_dev(void)
{
struct udevice *dev;
#include <lynxkdi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#error "Lynx KDI support not implemented for configured CPU"
#include <console.h>
#include <version.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
config SPL_SERIAL_SUPPORT
bool "Support serial"
+ select SPL_PRINTF
+ select SPL_STRTO
help
Enable support for serial in SPL. This allows use of a serial UART
for displaying messages while SPL is running. It also brings in
config SPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
+ depends on SPL_SERIAL_SUPPORT
help
While loading from serial is slow it can be a useful backup when
there is no other option. The Ymodem protocol provides a reliable
config TPL_SERIAL_SUPPORT
bool "Support serial"
+ select TPL_PRINTF
+ select TPL_STRTO
help
Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for
details.
config TPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
+ depends on TPL_SERIAL_SUPPORT
help
While loading from serial is slow it can be a useful backup when
there is no other option. The Ymodem protocol provides a reliable
jump_to_image_no_args(&spl_image);
}
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
/*
* This requires UART clocks to be enabled. In order for this to work the
* caller must ensure that the gd pointer is valid.
spl_display_print();
#endif
}
+#endif
/**
* spl_relocate_stack_gd() - Relocate stack ready for board_init_r() execution
#include <mmc.h>
#include <image.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc,
ulong sector, struct image_header *header)
{
#include <net.h>
#include <linux/libfdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)
static ulong spl_net_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
#include <fat.h>
#include <image.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int spl_sata_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
#include <g_dnl.h>
#include <sdp.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int spl_sdp_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
#include <usb.h>
#include <fat.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
#endif
#endif
#include <asm/unaligned.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#include <usb.h>
#define USB_BUFSIZ 512
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_CACHE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_CACHE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_CACHE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATCSPI200_SPI=y
CONFIG_TIMER=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7794=y
CONFIG_TARGET_ALT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_REGULATOR_TPS65910=y
CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_AR933X_UART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATH79_SPI=y
CONFIG_LZMA=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATH79_SPI=y
CONFIG_LZMA=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PHY_MICREL=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
# CONFIG_REGEX is not set
CONFIG_DFU_SF=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RTL8169=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_SPL_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_CROS_EC_LPC=y
CONFIG_RTL8169=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_PHYLIB=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_PHY_MICREL=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_HSSPI=y
CONFIG_USB=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_HSSPI=y
CONFIG_USB=y
CONFIG_E1000=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_USB=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_USB=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CONTROLCENTERDC=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL=y
CONFIG_EFI_PARTITION=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
# CONFIG_VIDEO_VESA is not set
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_PHY_ADDR=31
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_LPC32XX_SSP=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_MXC_UART=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_MXC_UART=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_SPI=y
CONFIG_ICH_SPI=y
# CONFIG_REGEX is not set
CONFIG_EFI=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_E1000=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_E1000=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_E1000=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7793=y
CONFIG_TARGET_GOSE=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_TARGET_IDS8313=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_REMOTEPROC_TI_POWER=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_REMOTEPROC_TI_POWER=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE8080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7790=y
CONFIG_TARGET_LAGER=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_RSA=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_RTL8169=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0xB6000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0xB6000000
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_SPI=y
CONFIG_WDT_BCM6345=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HCD=y
CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATCSPI200_SPI=y
CONFIG_TIMER=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
# CONFIG_REGEX is not set
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_OF_LIBFDT=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_OF_LIBFDT=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CPU=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPI=y
CONFIG_SPL_TIMER=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_NVME=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_USB=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
CONFIG_USB=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_TARGET_S32V234EVB=y
CONFIG_SYS_TEXT_BASE=0x3E800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw"
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LINFLEXUART=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_SPI=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_SILENT_CONSOLE=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
-CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=6
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
CONFIG_SILENT_CONSOLE=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
-CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=6
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_NETDEVICES=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_NETDEVICES=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_NETDEVICES=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_E1000=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_DM_VIDEO=y
# CONFIG_NET is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_REGEX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
CONFIG_E1000=y
+CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_PINCTRL=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATH79_SPI=y
CONFIG_USB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
CONFIG_LPC32XX_SSP=y
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_CLK is not set
# CONFIG_CMD_DM is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
config PARTITIONS
bool "Enable Partition Labels (disklabels) support"
default y
+ select SPL_SPRINTF if SPL
+ select TPL_SPRINTF if TPL
+ select SPL_STRTO if SPL
+ select TPL_STRTO if TPL
help
Partition Labels (disklabels) Supported:
Zero or more of the following:
/* Check all partition types */
#define PART_TYPE_ALL -1
-DECLARE_GLOBAL_DATA_PTR;
-
static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
{
struct part_driver *drv =
necessary, but at least works.
NOTE: target compilation only work for _some_ ARM boards at the moment.
-Also Aarch64 is not supported: Most notably boards which aren't using
-the generic board will fail to compile, but since those are expected
-to be converted this will solve itself. Boards which reassign gd in c
-will also fail to compile, but there is in no strict reason to do so
-in the ARM world, since crt0.S takes care of this. These assignments
-can be avoided by changing the init calls but this is not in mainline yet.
-
-NOTE: without the -mllvm -arm-use-movt=0 flags U-Boot will compile
-fine, but llvm might hardcode addresses in movw / movt pairs, which
-cannot be relocated and U-Boot will fail at runtime.
+Also AArch64 is not supported currently due to a lack of private libgcc
+support. Boards which reassign gd in c will also fail to compile, but there is
+in no strict reason to do so in the ARM world, since crt0.S takes care of this.
+These assignments can be avoided by changing the init calls but this is not in
+mainline yet.
Debian (based)
--------------
Note that we still use binutils for some tools so we must continue to set
CROSS_COMPILE. To compile U-Boot with clang on linux without IAS use e.g.:
make HOSTCC=clang rpi_2_defconfig
-make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8
+make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \
+ CC="clang -target arm-linux-gnueabi" -j8
It can also be used to compile sandbox:
make HOSTCC=clang sandbox_defconfig
In your board's defconfig, enable the DISTRO_DEFAULTS option by adding
a line with "CONFIG_DISTRO_DEFAULTS=y". If you want to enable this
from Kconfig itself, for e.g. all boards using a specific SoC then
-add a "default y if ARCH_FOO" to the DISTRO_DEFAULTS section of
-the Kconfig file in the root of the u-boot sources.
+add a "imply DISTRO_DEFAULTS" to your SoC CONFIG option.
In your board configuration file, include the following:
#include <adc.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_platdata)
#define CHECK_NUMBER true
#define CHECK_MASK (!CHECK_NUMBER)
#include <asm/io.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dwc_ahci_priv {
void *base;
void *wrapper_base;
#include <mach/at91_pmc.h>
#include "pmc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int at91_plladiv_clk_enable(struct clk *clk)
{
return 0;
#include <mach/sama5_sfr.h>
#include "pmc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The purpose of this clock is to generate a 480 MHz signal. A different
* rate can't be configured.
#include <common.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct udevice_id at91_sckc_match[] = {
{ .compatible = "atmel,at91sam9x5-sckc" },
{}
* |---------------------------->
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define CGU_ARC_IDIV 0x080
#define CGU_TUN_IDIV_TUN 0x380
#define CGU_TUN_IDIV_ROM 0x390
#include <dt-bindings/clock/stm32h7-clks.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* RCC CR specific definitions */
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSIRDY BIT(2)
#include <asm/arch/sys_proto.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
#include <dt-bindings/clock/exynos7420-clk.h>
#include "clk-pll.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
.set_rate = rk3036_clk_set_rate,
};
-static int rk3036_clk_probe(struct udevice *dev)
+static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3036_clk_probe(struct udevice *dev)
+{
+ struct rk3036_clk_priv *priv = dev_get_priv(dev);
+
rkclk_init(priv->cru);
return 0;
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
+ .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
.ops = &rk3036_clk_ops,
.bind = rk3036_clk_bind,
.probe = rk3036_clk_probe,
#include <dt-bindings/clock/rk3128-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
.set_rate = rk3128_clk_set_rate,
};
+static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
static int rk3128_clk_probe(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
rkclk_init(priv->cru);
return 0;
.id = UCLASS_CLK,
.of_match = rk3128_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
+ .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
.ops = &rk3128_clk_ops,
.bind = rk3128_clk_bind,
.probe = rk3128_clk_probe,
#include <dm/uclass-internal.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum rk3188_clk_type {
RK3188_CRU,
RK3188A_CRU,
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 3200U * 1000000,
VCO_MIN_HZ = 800 * 1000000,
return -ENOENT;
}
+static int rk3288_clk_enable(struct clk *clk)
+{
+ switch (clk->id) {
+ case HCLK_USBHOST0:
+ case HCLK_HSIC:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3288_clk_set_parent,
#endif
+ .enable = rk3288_clk_enable,
};
static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pll_div {
u32 refdiv;
u32 fbdiv;
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat {
struct dtd_rockchip_rk3368_cru dtd;
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_plat {
struct dtd_rockchip_rk3399_cru dtd;
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
}
-static int rv1108_clk_probe(struct udevice *dev)
+static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
+ return 0;
+}
+
+static int rv1108_clk_probe(struct udevice *dev)
+{
+ struct rv1108_clk_priv *priv = dev_get_priv(dev);
+
rkclk_init(priv->cru);
return 0;
.id = UCLASS_CLK,
.of_match = rv1108_clk_ids,
.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+ .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
.ops = &rv1108_clk_ops,
.bind = rv1108_clk_bind,
.probe = rv1108_clk_probe,
#include <dm/lists.h>
#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cpu_get_desc(struct udevice *dev, char *buf, int size)
{
struct cpu_ops *ops = cpu_get_ops(dev);
#include <asm/arch/system_manager.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sdram_prot_rule {
u32 sdram_start; /* SDRAM start address */
u32 sdram_end; /* SDRAM end address */
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
#include <dm/device-internal.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int dma_get_device(u32 transfer_type, struct udevice **devp)
{
struct udevice *dev;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x1000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
- /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
- * timeout at 1000ms
+ /*
+ * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+ * de-asserted, timeout at 1000ms
*/
- return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
- mask,
- false, FPGA_TIMEOUT_MSEC, false);
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
+ true, FPGA_TIMEOUT_MSEC, false);
}
static int wait_for_f2s_nstatus_pin(unsigned long value)
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
#include <errno.h>
#include <linux/printk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define HSDK_CREG_MAX_GPIO 8
#define GPIO_ACTIVATE 0x2
#include <asm/io.h>
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum imx_rgpio2p_direction {
IMX_RGPIO2P_DIRECTION_IN,
IMX_RGPIO2P_DIRECTION_OUT,
#include <asm/io.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MVEBU_GPIOS_PER_BANK 32
struct mvebu_gpio_regs {
#ifdef CONFIG_DM_GPIO
#include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
{
u32 val;
#include <asm/gpio.h>
#include <linux/bitops.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Register offset for each gpio */
#define REG_OFFSET(x) ((x) * 0x100)
#include <dm/of.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Flags for each GPIO */
#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */
#define GPIOF_HIGH (1 << 1) /* Currently set high */
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
struct sunxi_gpio_platdata {
#include <dt-bindings/gpio/gpio.h>
#include "tegra186_gpio_priv.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra186_gpio_port_data {
const char *name;
uint32_t offset;
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const int CONFIG_SFIO = 0;
static const int CONFIG_GPIO = 1;
static const int DIRECTION_INPUT = 0;
#define HIGHSPEED_TTIMEOUT 3
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Device private data
*/
#include <mapmem.h>
#include <wait_bit.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* i2c register set */
struct cdns_i2c_regs {
u32 control;
#include <fdtdec.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
#define LPI2C_FIFO_SIZE 4
#define LPI2C_TIMEOUT_MS 100
#include "omap24xx_i2c.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define I2C_TIMEOUT 1000
/* Absolutely safe for status update at 100 kHz I2C: */
#include <dm/pinctrl.h>
#include <linux/sizes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* i2c timerout */
#define I2C_TIMEOUT_MS 100
#define I2C_RETRY_COUNT 3
#include <dm/lists.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_i2c_priv {
bool test_mode;
};
.analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
};
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum i2c_type {
TYPE_114,
TYPE_STD,
#include <key_matrix.h>
#include <stdio_dev.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
KBC_MAX_KEYS = 8, /* Maximum keys held down at once */
KBC_REPEAT_RATE_MS = 30,
#include <asm/arch-tegra/timer.h>
#include <linux/input.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
KBC_MAX_GPIO = 24,
KBC_MAX_KPENT = 8, /* size of keypress entry queue */
#include <asm/gpio.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct led_gpio_priv {
struct gpio_desc gpio;
};
#include <mailbox.h>
#include <mailbox-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
{
return (struct mbox_ops *)dev->driver->ops;
uint32_t db_base;
};
-DECLARE_GLOBAL_DATA_PTR;
-
static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
uint32_t reg)
{
CROS_EC_CMD_HASH_TIMEOUT_MS = 2000,
};
-DECLARE_GLOBAL_DATA_PTR;
-
void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len)
{
#ifdef DEBUG
* the EC image in with U-Boot (Vic has demonstrated a prototype for this).
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define KEYBOARD_ROWS 8
#define KEYBOARD_COLS 13
#include <errno.h>
#include <spi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
#define debug_buffer(x, ...)
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_i2c_flash_plat_data {
enum sandbox_i2c_eeprom_test_mode test_mode;
const char *filename;
#include <dm.h>
#include <dt-structs.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_spl_probe(struct udevice *dev)
{
struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev);
#include <asm/test.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct udevice_id sandbox_syscon_ids[] = {
{ .compatible = "sandbox,syscon0", .data = SYSCON0 },
{ .compatible = "sandbox,syscon1", .data = SYSCON1 },
#ifdef CONFIG_DM_MMC
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MMC_CLOCK_MAX 48000000
#define MMC_CLOCK_MIN 400000
#include <mach/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define msleep(a) udelay(a * 1000)
#define SDCMD 0x00 /* Command to SD card - 16 R/W */
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_MMC_CLK_OD
# define CONFIG_SYS_MMC_CLK_OD 150000
#endif
#include <dm/lists.h>
#include "mmc_private.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
#include <asm/arch/periph.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rockchip_mmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_dw_mshc dtplat;
#include <sdhci.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ 400000
#include <mmc.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
-DECLARE_GLOBAL_DATA_PTR;
-
static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
oclk_dly = 0;
sclk_dly = 5;
#ifdef CONFIG_MACH_SUN9I
- } else if (hz <= 50000000) {
+ } else if (hz <= 52000000) {
oclk_dly = 5;
sclk_dly = 4;
} else {
- /* hz > 50000000 */
+ /* hz > 52000000 */
oclk_dly = 2;
sclk_dly = 4;
#else
- } else if (hz <= 50000000) {
+ } else if (hz <= 52000000) {
oclk_dly = 3;
sclk_dly = 4;
} else {
- /* hz > 50000000 */
+ /* hz > 52000000 */
oclk_dly = 1;
sclk_dly = 4;
#endif
{
unsigned int cmd;
unsigned timeout_msecs = 2000;
+ unsigned long start = get_timer(0);
cmd = SUNXI_MMC_CMD_START |
SUNXI_MMC_CMD_UPCLK_ONLY |
SUNXI_MMC_CMD_WAIT_PRE_OVER;
+
writel(cmd, &priv->reg->cmd);
while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
- if (!timeout_msecs--)
+ if (get_timer(start) > timeout_msecs)
return -1;
- udelay(1000);
}
/* clock update sets various irq status bits, clear these */
unsigned i;
unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
unsigned byte_cnt = data->blocksize * data->blocks;
- unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
- if (timeout_usecs < 2000000)
- timeout_usecs = 2000000;
+ unsigned timeout_msecs = byte_cnt >> 8;
+ unsigned long start;
+
+ if (timeout_msecs < 2000)
+ timeout_msecs = 2000;
/* Always read / write data through the CPU */
setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
+ start = get_timer(0);
+
for (i = 0; i < (byte_cnt >> 2); i++) {
while (readl(&priv->reg->status) & status_bit) {
- if (!timeout_usecs--)
+ if (get_timer(start) > timeout_msecs)
return -1;
- udelay(1);
}
if (reading)
uint timeout_msecs, uint done_bit, const char *what)
{
unsigned int status;
+ unsigned long start = get_timer(0);
do {
status = readl(&priv->reg->rint);
- if (!timeout_msecs-- ||
+ if ((get_timer(start) > timeout_msecs) ||
(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
debug("%s timeout %x\n", what,
status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
return -ETIMEDOUT;
}
- udelay(1000);
} while (!(status & done_bit));
return 0;
}
if (cmd->resp_type & MMC_RSP_BUSY) {
+ unsigned long start = get_timer(0);
timeout_msecs = 2000;
+
do {
status = readl(&priv->reg->status);
- if (!timeout_msecs--) {
+ if (get_timer(start) > timeout_msecs) {
debug("busy timeout\n");
error = -ETIMEDOUT;
goto out;
}
- udelay(1000);
} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
}
#include <asm/io.h>
#include <asm/arch-tegra/tegra_mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
int nand_curr_device = -1;
static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#include <dm/lists.h>
#include <dm/uclass-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The different states that our SPI flash transitions between.
* We need to keep track of this across multiple xfer calls since
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
+#define SST26_CMD_READ_BPR 0x72
+#define SST26_CMD_WRITE_BPR 0x42
+
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ SST26_CTL_LOCK,
+ SST26_CTL_UNLOCK,
+ SST26_CTL_CHECK
+};
+
# define CMD_SST_BP 0x02 /* Byte Program */
# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
#include <spi.h>
#include <spi_flash.h>
#include <linux/log2.h>
+#include <linux/sizes.h>
#include <dma.h>
#include "sf_internal.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static void spi_flash_addr(u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
}
#ifdef CONFIG_SPI_FLASH_SST
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * sst26wf016/sst26wf032/sst26wf064 have next block protection:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash (depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
+{
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
+ return -EINVAL;
+
+ if (ofs + len > flash->size)
+ return -EINVAL;
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (flash->size != SZ_2M &&
+ flash->size != SZ_4M &&
+ flash->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (flash->size / SZ_64K / 8);
+
+ cmd = SST26_CMD_READ_BPR;
+ ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+ lptr_64k += SZ_64K;
+ }
+
+ /* 32K and 8K region bits in BPR are after 64k region bits */
+ bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
+
+ /* Process lower 32K block region */
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process upper 32K block region */
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process lower 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* Process upper 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* If we check region status we don't need to write BPR back */
+ if (ctl == SST26_CTL_CHECK)
+ return 0;
+
+ cmd = SST26_CMD_WRITE_BPR;
+ ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to write block-protection register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
+}
+
+static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
+}
+
+/*
+ * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
+ * and negative on errors.
+ */
+static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ /*
+ * is_locked function is used for check before reading or erasing flash
+ * region, so offset and length might be not 64k allighned, so adjust
+ * them to be 64k allighned as sst26_lock_ctl works only with 64k
+ * allighned regions.
+ */
+ ofs -= ofs & (SZ_64K - 1);
+ len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
+
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
+}
+
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
struct spi_slave *spi = flash->spi;
}
#endif
+/* sst26wf series block protection implementation differs from other series */
+#if defined(CONFIG_SPI_FLASH_SST)
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
+ flash->flash_lock = sst26_lock;
+ flash->flash_unlock = sst26_unlock;
+ flash->flash_is_locked = sst26_is_locked;
+ }
+#endif
+
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
flash->page_size = info->page_size;
{"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) },
{"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) },
{"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) },
+ {"s25fl208k", INFO(0x014014, 0x0, 64 * 1024, 16, 0) },
{"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) },
{"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) },
{"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) },
{"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },
{"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
{"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) },
+ {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) },
+ {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
{"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) },
#include <power/regulator.h>
#include "designware.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
#ifdef CONFIG_DM_ETH
}
/* Not sure why all of these are necessary */
-void spi_init_r(void) { /* Nothing to do */ }
-void spi_init_f(void) { /* Nothing to do */ }
void spi_init(void) { /* Nothing to do */ }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
#include "MCD_dma.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct fec_info_dma fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Platform data for the gmac
*
#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/*
* mii_reg_read - miiphy_read callback function.
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
-DECLARE_GLOBAL_DATA_PTR;
-
struct fec_info_s fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
#include <stdio_dev.h>
#include <net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_NETCONSOLE_BUFFER_SIZE
#define CONFIG_NETCONSOLE_BUFFER_SIZE 512
#endif
#include <micrel.h>
#include <phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct phy_driver KSZ804_driver = {
.name = "Micrel KSZ804",
.uid = 0x221510,
#include <micrel.h>
#include <phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* KSZ9021 - KSZ9031 common
*/
#include <dm.h>
#include <pch.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
#define CFG_RD_UR_VAL 0xFFFFFFFF
#define CFG_RD_CRS_VAL 0xFFFF0001
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct pcie_advk - Advk PCIe controller state
*
#include <pci.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_pci_priv {
int dev_count;
};
#include <inttypes.h>
#include <pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
uint offset, ulong value,
enum pci_size_t size)
* use the new standard APIs, with no ifdefs.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define AFI_AXI_BAR0_SZ 0x00
#define AFI_AXI_BAR1_SZ 0x04
#define AFI_AXI_BAR2_SZ 0x08
#include <linux/bitops.h>
#include <linux/compat.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* bits [31:27] are read-only */
#define U2P_R0 0x0
#define U2P_R0_BYPASS_SEL BIT(0)
#include <linux/compat.h>
#include <linux/bitfield.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define USB_R0 0x00
#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
#define USB_R0_P30_PHY_RESET BIT(6)
#include <dm.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct phy_ops *phy_dev_ops(struct udevice *dev)
{
return (struct phy_ops *)dev->driver->ops;
#include <dm.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_phy_priv {
bool initialized;
bool on;
#include <asm/arch/scu_ast2500.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver works with very simple configuration that has the same name
* for group and function. This way it is compatible with the Linux Kernel
#include <asm/arch/pinmux.h>
#include "pinctrl-exynos.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define GPD1_OFFSET 0xc0
static struct exynos_pinctrl_config_data serial2_conf[] = {
#include "sh_pfc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum sh_pfc_model {
SH_PFC_R8A7790 = 0,
SH_PFC_R8A7791,
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* GRF_GPIO0A_IOMUX */
enum {
GPIO0A3_SHIFT = 6,
#include <asm/io.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
/* GPIO0A_IOMUX */
GPIO0A5_SEL_SHIFT = 10,
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* PMUGRF_GPIO0B_IOMUX */
enum {
GPIO0B5_SHIFT = 10,
#include <asm/arch/clock.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rv1108_pinctrl_priv {
struct rv1108_grf *grf;
};
#include <power-domain.h>
#include <power-domain-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev)
{
return (struct power_domain_ops *)dev->driver->ops;
#include <power/act8846_pmic.h>
#include <power/pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "REG", .driver = "act8846_reg"},
{ },
#include <power/pmic.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct sandbox_i2c_pmic_plat_data - platform data for the PMIC
*
#include <power/lp873x.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo", .driver = LP873X_LDO_DRIVER },
{ .prefix = "buck", .driver = LP873X_BUCK_DRIVER },
#include <power/lp87565.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
{ },
#include <power/regulator.h>
#include <power/max77686_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "LDO", .driver = MAX77686_LDO_DRIVER },
{ .prefix = "BUCK", .driver = MAX77686_BUCK_DRIVER },
#include <power/max8997_pmic.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int max8997_reg_count(struct udevice *dev)
{
return PMIC_NUM_OF_REGS;
#include <power/pmic.h>
#include <power/max8998_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int max8998_reg_count(struct udevice *dev)
{
return PMIC_NUM_OF_REGS;
#include <power/palmas.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
{ .prefix = "smps", .driver = PALMAS_SMPS_DRIVER },
#include <power/regulator.h>
#include <power/pfuze100_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
/* sw[x], swbst */
{ .prefix = "s", .driver = PFUZE100_REGULATOR_DRIVER },
#include <power/pmic.h>
#include <spmi/spmi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define PID_SHIFT 8
#define PID_MASK (0xFF << PID_SHIFT)
#define REG_MASK 0xFF
#include <power/pmic.h>
#include <linux/ctype.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
int pmic_bind_children(struct udevice *pmic, ofnode parent,
const struct pmic_child_info *child_info)
#include <power/regulator.h>
#include <power/tps65910_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER },
{ .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER },
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "DCDC_REG", .driver = "rk8xx_buck"},
{ .prefix = "LDO_REG", .driver = "rk8xx_ldo"},
#include <power/pmic.h>
#include <power/s2mps11.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = S2MPS11_OF_LDO_PREFIX, .driver = S2MPS11_LDO_DRIVER },
{ .prefix = S2MPS11_OF_BUCK_PREFIX, .driver = S2MPS11_BUCK_DRIVER },
#include <power/regulator.h>
#include <power/s5m8767.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "LDO", .driver = S5M8767_LDO_DRIVER },
{ .prefix = "BUCK", .driver = S5M8767_BUCK_DRIVER },
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = SANDBOX_OF_LDO_PREFIX, .driver = SANDBOX_LDO_DRIVER },
{ .prefix = SANDBOX_OF_BUCK_PREFIX, .driver = SANDBOX_BUCK_DRIVER },
#include <power/pmic.h>
#include <power/tps65090.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "fet", .driver = TPS65090_FET_DRIVER },
{ },
#include <power/pmic.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct fixed_regulator_platdata {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
#include <power/regulator.h>
#include <power/lp873x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const char lp873x_buck_ctrl[LP873X_BUCK_NUM] = {0x2, 0x4};
static const char lp873x_buck_volt[LP873X_BUCK_NUM] = {0x6, 0x7};
static const char lp873x_ldo_ctrl[LP873X_LDO_NUM] = {0x8, 0x9};
#include <power/regulator.h>
#include <power/lp87565.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
#include <power/regulator.h>
#include <power/max77686_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) { \
.id = _id, \
.register_value = _val, \
#include <power/regulator.h>
#include <power/palmas.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define REGULATOR_ON 0x1
#define REGULATOR_OFF 0x0
#include <linux/ioport.h>
#include <dm/read.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pbias_reg_info {
u32 enable;
u32 enable_mask;
#include <power/pmic.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep)
{
struct dm_regulator_uclass_platdata *uc_pdata;
#include <power/regulator.h>
#include <power/s2mps11.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) { \
.id = _id, \
.register_value = _val, \
#include <power/regulator.h>
#include <power/s5m8767.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct sec_voltage_desc buck_v1 = {
.max = 2225000,
.min = 650000,
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) [_id] = { \
.id = _id, \
.register_value = _val, \
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct exynos_pwm_priv {
struct s5p_timer *regs;
};
#include <asm/arch/pwm.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rk_pwm_priv {
struct rk3288_pwm *regs;
ulong freq;
#include <pwm.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
NUM_CHANNELS = 3,
};
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra_pwm_priv {
struct pwm_ctlr *regs;
};
#include <asm/arch/sdram.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dram_info {
struct ram_info info;
struct clk ddr_clk;
#include <asm/arch/grf_rk3128.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
struct dram_info {
struct ram_info info;
struct rk3128_grf *grf;
#include <asm/arch/sdram_common.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct chan_info {
struct rk3288_ddr_pctl *pctl;
struct rk3288_ddr_publ *publ;
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct chan_info {
struct rk3288_ddr_pctl *pctl;
struct rk3288_ddr_publ *publ;
#include <asm/arch/grf_rk3328.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
struct dram_info {
struct ram_info info;
struct rk3328_grf_regs *grf;
#include <linux/err.h>
#include <time.h>
-DECLARE_GLOBAL_DATA_PTR;
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
#define MEM_MODE_MASK GENMASK(2, 0)
#define NOT_FOUND 0xff
-DECLARE_GLOBAL_DATA_PTR;
-
struct stm32_fmc_regs {
/* 0x0 */
u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
#include <asm/io.h>
#include "stm32mp1_ddr.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static const char *const clkname[] = {
"ddrc1",
"ddrc2",
#include <asm/arch/scu_ast2500.h>
#include <asm/arch/wdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct ast2500_reset_priv {
/* WDT used to perform resets. */
struct udevice *wdt;
#include <reset.h>
#include <reset-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
{
return (struct reset_ops *)dev->driver->ops;
#define debug_buffer(x, ...)
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct sandbox_i2c_rtc_plat_data - platform data for the RTC
*
help
Select this to enable UART on BCM6345 SoCs.
+config FSL_LINFLEXUART
+ bool "Freescale Linflex UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable the Linflex serial module found on some
+ NXP SoCs like S32V234.
+
config FSL_LPUART
bool "Freescale LPUART support"
help
#include <serial.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* data register */
#define ALTERA_JTAG_RVALID BIT(15) /* Read valid */
#include <asm/arch/uart.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct lpc32xx_hsuart_priv {
struct hsuart_regs *hsuart;
};
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_SERIAL
-#error "The linflex serial driver does not have non-DM support."
-#endif
-
static void _linflex_serial_setbrg(struct linflex_fsl *base, int baudrate)
{
u32 clk = mxc_get_clock(MXC_UART_CLK);
#include <linux/compiler.h>
#include <serial.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct meson_uart {
u32 wfifo;
u32 rfifo;
#include <asm/arch/stm32.h>
#include "serial_stm32.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
+ u32 isr = readl(base + ISR_OFFSET(stm32f4));
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
+ if ((isr & USART_ISR_FLAG_RXNE) == 0)
return -EAGAIN;
+ if (isr & USART_ISR_FLAG_ORE) {
+ if (!stm32f4)
+ setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
+ else
+ readl(base + RDR_OFFSET(stm32f4));
+ return -EIO;
+ }
+
return readl(base + RDR_OFFSET(stm32f4));
}
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
return -EAGAIN;
writel(c, base + TDR_OFFSET(stm32f4));
if (input)
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_RXNE ? 1 : 0;
+ USART_ISR_FLAG_RXNE ? 1 : 0;
else
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_TXE ? 0 : 1;
+ USART_ISR_FLAG_TXE ? 0 : 1;
}
static int stm32_serial_probe(struct udevice *dev)
return plat->clock_rate;
};
- /* Disable uart-> disable overrun-> enable uart */
+ /* Disable uart-> enable fifo-> enable uart */
clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
BIT(uart_enable_bit));
- if (plat->uart_info->has_overrun_disable)
- setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
if (plat->uart_info->has_fifo)
setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
+
+#define ICR_OFFSET 0x20
/*
* STM32F4 has one Data Register (DR) for received or transmitted
* data, so map Receive Data Register (RDR) and Transmit Data
struct stm32_uart_info {
u8 uart_enable_bit; /* UART_CR1_UE */
bool stm32f4; /* true for STM32F4, false otherwise */
- bool has_overrun_disable;
bool has_fifo;
};
struct stm32_uart_info stm32f4_info = {
.stm32f4 = true,
.uart_enable_bit = 13,
- .has_overrun_disable = false,
.has_fifo = false,
};
struct stm32_uart_info stm32f7_info = {
.uart_enable_bit = 0,
.stm32f4 = false,
- .has_overrun_disable = true,
.has_fifo = false,
};
struct stm32_uart_info stm32h7_info = {
.uart_enable_bit = 0,
.stm32f4 = false,
- .has_overrun_disable = true,
.has_fifo = true,
};
#define USART_CR3_OVRDIS BIT(12)
-#define USART_SR_FLAG_RXNE BIT(5)
-#define USART_SR_FLAG_TXE BIT(7)
+#define USART_ISR_FLAG_ORE BIT(3)
+#define USART_ISR_FLAG_RXNE BIT(5)
+#define USART_ISR_FLAG_TXE BIT(7)
#define USART_BRR_F_MASK GENMASK(7, 0)
#define USART_BRR_M_SHIFT 4
#define USART_BRR_M_MASK GENMASK(15, 4)
+#define USART_ICR_OREF BIT(3)
#endif
#include <linux/compiler.h>
#include <serial.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
#include <serial.h>
#include <asm/arch/hardware.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
-menu "SPI Support"
+menuconfig SPI
+ bool "SPI Support"
+
+if SPI
config DM_SPI
bool "Enable Driver Model for SPI drivers"
(McSPI). This driver be used to access SPI chips on platforms
embedding this OMAP3 McSPI IP core.
-endmenu # menu "SPI Support"
+endif # menu "SPI Support"
#include <spi.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
#include "atmel_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_SPI
static int spi_has_wdrbt(struct atmel_spi_slave *slave)
return 0;
}
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
void spi_init(void)
{
cfspi_init();
* in the beginning of new transfer.
*/
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
- !(val & SR_TF_EMPT) || (val & SR_BUSY),
+ (val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
ret = -ETIMEDOUT;
}
/* Nothing to do */
}
-void spi_init_f(void)
-{
- /* Nothing to do */
-}
-
-void spi_init_r(void)
-{
- /* Nothing to do */
-}
-
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
#include <dm/pinctrl.h>
#include "rk_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
#include <asm/state.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SPI_IDLE_VAL
# define CONFIG_SPI_IDLE_VAL 0xFF
#endif
#include <spi.h>
#include "tegra_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* COMMAND1 */
#define SPI_CMD1_GO BIT(31)
#define SPI_CMD1_M_S BIT(30)
#include <asm/gpio.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define EMUL_GPIO_PID_START 0xC0
#define EMUL_GPIO_PID_END 0xC3
#include <spmi/spmi.h>
#include <linux/ctype.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
{
const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
#include <asm/state.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_warm_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
#include <timer.h>
#include <linux/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Timer Control Register
*/
#include <timer.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* control register */
#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
#define ALTERA_TIMER_START BIT(2) /* Start timer */
#include <asm/io.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define AST_TICK_TIMER 1
#define AST_TMC_RELOAD_VAL 0xffffffff
#include <timer.h>
#include <linux/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
/*
#include <asm/io.h>
#include <asm/arch/clock.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timer register bits */
#define TCLR_START BIT(0) /* Start=1 */
#define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
};
static const struct udevice_id rockchip_timer_ids[] = {
+ { .compatible = "rockchip,rk3188-timer" },
+ { .compatible = "rockchip,rk3288-timer" },
{ .compatible = "rockchip,rk3368-timer" },
{}
};
#include "tpm_tis.h"
#include "tpm_internal.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum i2c_chip_type {
SLB9635,
SLB9645,
#include <scsi.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver emulates a flash stick using the UFI command specification and
* the BBB (bulk/bulk/bulk) protocol. It supports only a single logical unit
#include <usb.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* We only support up to 8 */
#define SANDBOX_NUM_PORTS 4
#include <scsi.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver emulates a USB keyboard using the USB HID specification (boot
* protocol)
#include <usb.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int copy_to_unicode(char *buff, int length, const char *str)
{
int ptr;
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
+ if (!cdev->config)
+ goto done;
+
/*
* functions always handle their interfaces and endpoints...
* punt other recipients (other, WUSB, ...) to the current
value = f->setup(f, ctrl);
else {
c = cdev->config;
- if (c && c->setup)
+ if (c->setup)
value = c->setup(c, ctrl);
}
#include "dwc2.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Use only HC channel 0. */
#define DWC2_HC_CHANNEL 0
#include <reset.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dwc3_of_simple {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
#include "ehci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
#include "ehci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define USB1_ADDR_MASK 0xFFFF0000
#define HOSTPC1_DEVLC 0x84
#include <usb.h>
#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_usb_ctrl {
int rootdev;
};
#include <dm/lists.h>
#include <dm/uclass-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern bool usb_started; /* flag for the started/stopped USB status */
static bool asynch_allowed;
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct xhci_dwc3_platdata {
struct phy *usb_phys;
int num_phys;
}
#ifdef CONFIG_DM_USB
-static int xhci_dwc3_setup_phy(struct udevice *dev, int count)
+static int xhci_dwc3_setup_phy(struct udevice *dev)
{
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
- int i, ret;
+ int i, ret, count;
- if (!count)
+ /* Return if no phy declared */
+ if (!dev_read_prop(dev, "phys", NULL))
return 0;
+ count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
+ if (count <= 0)
+ return count;
+
plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
- GFP_KERNEL);
+ GFP_KERNEL);
if (!plat->usb_phys)
return -ENOMEM;
++plat->num_phys;
}
-
+
for (i = 0; i < plat->num_phys; i++) {
ret = generic_phy_init(&plat->usb_phys[i]);
if (ret) {
goto phys_init_err;
}
}
-
+
for (i = 0; i < plat->num_phys; i++) {
ret = generic_phy_power_on(&plat->usb_phys[i]);
if (ret) {
return 0;
-
phys_poweron_err:
for (; i >= 0; i--)
generic_phy_power_off(&plat->usb_phys[i]);
ret |= generic_phy_exit(&plat->usb_phys[i]);
if (ret) {
pr_err("Can't shutdown USB PHY%d for %s\n",
- i, dev->name);
+ i, dev->name);
}
}
hcor = (struct xhci_hcor *)((uintptr_t)hccr +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
- ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args(
- dev, "phys", "#phy-cells"));
+ ret = xhci_dwc3_setup_phy(dev);
if (ret)
return ret;
#include <dm.h>
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_USB
static struct fsl_xhci fsl_xhci;
unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
#include "xhci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct mvebu_xhci_platdata {
fdt_addr_t hcd_base;
};
#include "xhci.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
static struct omap_xhci omap;
static int omap_xhci_core_init(struct omap_xhci *omap)
#include "xhci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct rockchip_xhci_platdata {
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
#include "xhci.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
/* Default to the ZYNQMP XHCI defines */
#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
config USB_MUSB_HOST
bool "MUSB host mode support"
+ select SPL_SPRINTF if SPL
+ select TPL_SPRINTF if TPL
help
Enables the MUSB USB dual-role controller in host mode.
config USB_MUSB_GADGET
bool "MUSB gadget mode support"
select USB_GADGET_DUALSPEED
+ select SPL_SPRINTF if SPL
+ select TPL_SPRINTF if TPL
help
Enables the MUSB USB dual-role controller in gadget mode.
#include <backlight.h>
#include <asm/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct gpio_backlight_priv {
struct gpio_desc gpio;
bool def_value;
#define DP_MAX_LANE_COUNT 0x002
#define DP_MAX_LANE_COUNT_MASK 0x1f
-DECLARE_GLOBAL_DATA_PTR;
-
struct anx6345_priv {
u8 edid[EDID_SIZE];
};
#include "exynos_dp_lowlevel.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
unsigned int enable)
{
struct chan_param_mem_interleaved ip;
};
-DECLARE_GLOBAL_DATA_PTR;
-
/* graphics setup */
static GraphicDevice panel;
static struct ctfb_res_modes *mode;
#include <asm/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pwm_backlight_priv {
struct udevice *reg;
struct gpio_desc enable;
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/rockchip_mipi_dsi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MHz 1000000
/* Select mipi dsi source, big or little vop */
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/rockchip_mipi_dsi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Select mipi dsi source, big or little vop */
static int rk_mipi_dsi_source_select(struct udevice *dev)
{
#include <asm/arch/grf_rk3288.h>
#include <dt-bindings/clock/rk3288-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
#define DP_LINK_STATUS_SIZE 6
#include <asm/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct simple_panel_priv {
struct udevice *reg;
struct udevice *backlight;
#include <dm/uclass-internal.h>
#include "displayport.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* return in 1000ths of a Hertz */
static int tegra_dc_calc_refresh(const struct display_timing *timing)
{
#include "sor.h"
#include "displayport.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DO_FAST_LINK_TRAINING 1
struct tegra_dp_plat {
#include "displayport.h"
#include "sor.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG_SOR 0
#define APBDEV_PMC_DPD_SAMPLE 0x20
#define WDT_AST2500 2500
#define WDT_AST2400 2400
-DECLARE_GLOBAL_DATA_PTR;
-
struct ast_wdt_priv {
struct ast_wdt *regs;
};
#include <asm/cpm_8xx.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void hw_watchdog_reset(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
#include <wdt.h>
#include <asm/state.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
struct sandbox_state *state = state_get_current();
#define WDG_32KHZ_CLK (0x2)
#define WDG_EXT_CLK (0x3)
-DECLARE_GLOBAL_DATA_PTR;
-
void hw_watchdog_set_timeout(u16 val)
{
/* setting timeout value */
#include <dm/device-internal.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
#include <ext4fs.h>
#include <mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_CMD_SAVEENV
static int env_ext4_save(void)
{
# endif
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CMD_SAVEENV
static int env_fat_save(void)
{
#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
__weak int sata_get_env_dev(void)
{
return CONFIG_SYS_SATA_ENV_DEV;
#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
#endif
-/*
- * Set this up regardless of board
- * type, to prevent errors.
- */
-#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
-# define CONFIG_SYS_DEF_EEPROM_ADDR 0
-#else
-#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
#endif
-#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
-#if defined(CONFIG_SPI)
+#if defined(CONFIG_MPC8XX_SPI)
extern void spi_init_f (void);
extern void spi_init_r (void);
extern ssize_t spi_read (uchar *, int, uchar *, int);
#define CONFIG_SYS_MAXARGS 16
#endif
-#ifndef CONFIG_FIT_SIGNATURE
-#define CONFIG_IMAGE_FORMAT_LEGACY
-#endif
-
-#ifdef CONFIG_DISABLE_IMAGE_LEGACY
-#undef CONFIG_IMAGE_FORMAT_LEGACY
-#endif
-
#ifdef CONFIG_DM_I2C
# ifdef CONFIG_SYS_I2C
# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
#include "rcar-gen2-common.h"
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SCIF */
-
/* FLASH */
-#define CONFIG_SPI
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xee200000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF2 */
-#define CONFIG_SMSTP7_ENA 0x00080000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __ALT_H */
/* FLASH */
#if !defined(CONFIG_MTD_NOR_FLASH)
-#define CONFIG_SPI
#define CONFIG_SH_QSPI_BASE 0xE6B10000
#else
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPI_BOOT)
/* McSPI IP block */
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* SPI Flash support */
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_EXTRA_ENV_SETTINGS
#endif
-/* SPI */
-#define CONFIG_SPI
-
/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE 0x40000000
#include <configs/ti_am335x_common.h>
-#undef CONFIG_SPI
-
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
#endif
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SPI
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_DM9000_NO_SROM 1
#undef CONFIG_DM9000_DEBUG
-/* SPI */
-#undef CONFIG_SPI
-
-/* I2C */
-
/* TWL4030 */
#define CONFIG_TWL4030_LED 1
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
-#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
-#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0" \
- "preboot=usb start\0"
+ "stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
-#endif
-
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
- (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE 0x40000000
-#define RCAR_GEN2_SDRAM_SIZE 0x40000000
-#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
-
-/* SCIF */
-
-/* FLASH */
-#define CONFIG_SPI
+#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_SYS_TMU_CLK_DIV 4
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
+#define CONFIG_SYS_TMU_CLK_DIV 4
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __GOSE_H */
/* UBI Support */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_IMAGE_FORMAT_LEGACY
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_SP_OFFSET)
-/* FIT */
-#ifdef CONFIG_FIT
-# define CONFIG_IMAGE_FORMAT_LEGACY
-#endif
-
/* UART */
#ifdef CONFIG_MXC_UART
# ifdef CONFIG_MX6UL
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SCIF */
-
-/* FLASH */
-#define CONFIG_SPI
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SCIF */
-
-/* SPI */
-#define CONFIG_SPI
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_RCAR
-#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
-#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
-#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
-#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SYS_TMU_CLK_DIV 4
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* MMC */
-#define CONFIG_SH_MMCIF_ADDR 0xEE220000
-#define CONFIG_SH_MMCIF_CLK 97500000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __LAGER_H */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_NET_MULTI
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#ifdef SPIFLASH
# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
-# define CONFIG_SPI 1
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
-#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SF Configs */
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* SCIF */
-
/* FLASH */
-#define CONFIG_SPI
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
#define CONFIG_SYS_MALLOC_LEN SZ_16M
-/* QEMU implements a 62.5MHz architected timer */
-/* FIXME: can we rely on CNTFREQ instead of hardcoding this fact here? */
-#define CONFIG_SYS_ARCH_TIMER
+/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_HZ_CLOCK 62500000
/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 6
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10088000
-#define CONFIG_SPL_TEXT_BASE 0x10081004
+#define CONFIG_SPL_TEXT_BASE 0x10081000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
-
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#endif
#define SDRAM_MAX_SIZE 0xfe000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x0fffffff\0" \
"initrd_high=0x0fffffff\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VIDEO_BMP_LOGO
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
-#define CONFIG_SPI
-
#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
#define CONFIG_FORMIKE
#define DISPL_PLL_SPREAD_SPECTRUM
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
#include <asm/arch/imx-regs.h>
#define CONFIG_S32V234
-#define CONFIG_DM
/* Config GIC */
#define CONFIG_GICV2
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#endif
-#define CONFIG_DM_SERIAL
-#define CONFIG_FSL_LINFLEXUART
#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR
#define CONFIG_DEBUG_UART_LINFLEXUART
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_SPI
#define CONFIG_MTD_DEVICE
#define CONFIG_SF_DEFAULT_SPEED (75000000)
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SCIF */
-
/* FLASH */
-#define CONFIG_SPI
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_ARCH_TIMER
/*
* malloc() pool size
#define CONFIG_SCIF_A
/* SPI */
-#define CONFIG_SPI
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
#endif
/* SPI EEPROM */
-#define CONFIG_SPI
#define TAURUS_SPI_MASK (1 << 4)
#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
#define CONFIG_DM_I2C_COMPAT
#endif
-/* McSPI IP block */
-#define CONFIG_SPI
-
-/* GPIO block */
-
/*
* The following are general good-enough settings for U-Boot. We set a
* large malloc pool as we generally have a lot of DDR, and we opt for
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#define CONFIG_IMAGE_FORMAT_LEGACY
-
/* general purpose I/O */
#define CONFIG_AT91_GPIO
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-/*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_SPI
-
/*-----------------------------------------------------------------------
* Environment configuration
*/
GENERATED_GBL_DATA_SIZE)
-/* FIT support */
-#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
-
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
config LIB_UUID
bool
+config PRINTF
+ bool
+ default y
+
+config SPL_PRINTF
+ bool
+ select SPL_SPRINTF
+ select SPL_STRTO if !USE_TINY_PRINTF
+
+config TPL_PRINTF
+ bool
+ select TPL_SPRINTF
+ select TPL_STRTO if !USE_TINY_PRINTF
+
+config SPRINTF
+ bool
+ default y
+
+config SPL_SPRINTF
+ bool
+
+config TPL_SPRINTF
+ bool
+
+config STRTO
+ bool
+ default y
+
+config SPL_STRTO
+ bool
+
+config TPL_STRTO
+ bool
+
config USE_PRIVATE_LIBGCC
bool "Use private libgcc"
depends on HAVE_PRIVATE_LIBGCC
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_LIB_UUID) += uuid.o
obj-$(CONFIG_LIB_RAND) += rand.o
+obj-y += panic.o
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_TPL_BUILD
-SERIAL_SUPPORT := $(CONFIG_TPL_SERIAL_SUPPORT)
-else
-SERIAL_SUPPORT := $(CONFIG_SPL_SERIAL_SUPPORT)
-endif
+ifeq ($(CONFIG_$(SPL_TPL_)BUILD),y)
# SPL U-Boot may use full-printf, tiny-printf or none at all
ifdef CONFIG_USE_TINY_PRINTF
-obj-$(SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
+obj-$(CONFIG_$(SPL_TPL_)SPRINTF) += tiny-printf.o
else
-obj-$(SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
+obj-$(CONFIG_$(SPL_TPL_)SPRINTF) += vsprintf.o strmhz.o
endif
+obj-$(CONFIG_$(SPL_TPL_)STRTO) += strto.o
else
# Main U-Boot always uses the full printf support
-obj-y += vsprintf.o panic.o strto.o strmhz.o
+obj-y += vsprintf.o strto.o strmhz.o
endif
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
#include <efi.h>
#include <efi_api.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Unfortunately we cannot access any code outside what is built especially
* for the stub. lib/string.c is already being built for the U-Boot payload
#include <linux/err.h>
#include <linux/types.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_X86
/*
* Problem areas:
#include <pe.h>
#include <asm/global_data.h>
-DECLARE_GLOBAL_DATA_PTR;
-
const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
const efi_guid_t efi_guid_device_path = DEVICE_PATH_GUID;
const efi_guid_t efi_guid_loaded_image = LOADED_IMAGE_GUID;
#include <lcd.h>
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
static struct efi_pxe_packet *dhcp_ack;
#include <dm/of_access.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static void *unflatten_dt_alloc(void **mem, unsigned long size,
unsigned long align)
{
void panic(const char *fmt, ...)
{
+#if CONFIG_IS_ENABLED(PRINTF)
va_list args;
va_start(args, fmt);
vprintf(fmt, args);
va_end(args);
+#endif
panic_finish();
}
+
+void __assert_fail(const char *assertion, const char *file, unsigned int line,
+ const char *function)
+{
+ /* This will not return */
+ panic("%s:%u: %s: Assertion `%s' failed.", file, line, function,
+ assertion);
+}
option. The software based modular exponentiation is built into
mkimage irrespective of this option.
+if RSA
+
config SPL_RSA
bool "Use RSA Library within SPL"
- depends on RSA
-if RSA
config RSA_SOFTWARE_EXP
bool "Enable driver for RSA Modular Exponentiation in software"
- depends on DM && RSA
+ depends on DM
help
Enables driver for modular exponentiation in software. This is a RSA
algorithm used in FIT image verification. It required RSA Key as
config RSA_FREESCALE_EXP
bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
- depends on DM && RSA && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
help
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
#include <dm/uclass-internal.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* smbios_add_string() - add a string to the string area
*
void (*putc)(struct printf_info *info, char ch);
};
-static void putc_normal(struct printf_info *info, char ch)
-{
- putc(ch);
-}
-
static void out(struct printf_info *info, char c)
{
*info->bf++ = c;
return 0;
}
+#if CONFIG_IS_ENABLED(PRINTF)
+static void putc_normal(struct printf_info *info, char ch)
+{
+ putc(ch);
+}
+
int vprintf(const char *fmt, va_list va)
{
struct printf_info info;
return ret;
}
+#endif
static void putc_outstr(struct printf_info *info, char ch)
{
return ret;
}
-
-void __assert_fail(const char *assertion, const char *file, unsigned line,
- const char *function)
-{
- /* This will not return */
- printf("%s:%u: %s: Assertion `%s' failed.", file, line, function,
- assertion);
- hang();
-}
return i;
}
+#if CONFIG_IS_ENABLED(PRINTF)
int printf(const char *fmt, ...)
{
va_list args;
puts(printbuffer);
return i;
}
-
-
-void __assert_fail(const char *assertion, const char *file, unsigned line,
- const char *function)
-{
- /* This will not return */
- panic("%s:%u: %s: Assertion `%s' failed.", file, line, function,
- assertion);
-}
+#endif
char *simple_itoa(ulong i)
{
#include "sntp.h"
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/** BOOTP EXTENTIONS **/
/* Our subnet mask (0=unknown) */
extern int cpu_post_test_string (void);
extern int cpu_post_test_complex (void);
-DECLARE_GLOBAL_DATA_PTR;
-
ulong cpu_post_makecr (long v)
{
ulong cr = 0;
CONFIG_DIMM_SLOTS_PER_CTLR
CONFIG_DIRECT_NOR_BOOT
CONFIG_DISABLE_CONSOLE
-CONFIG_DISABLE_IMAGE_LEGACY
CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
-CONFIG_FSL_LINFLEXUART
CONFIG_FSL_MC9SDZ60
CONFIG_FSL_MEMAC
CONFIG_FSL_NGPIXIS
CONFIG_IDT8T49N222A
CONFIG_ID_EEPROM
CONFIG_IMA
-CONFIG_IMAGE_FORMAT_LEGACY
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_MPC85XX_PCI2
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MPLL_FREQ
-CONFIG_MP_CLK_FREQ
CONFIG_MSHC_FREQ
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_PLATINUM_BOARD
CONFIG_PLATINUM_CPU
CONFIG_PLATINUM_PROJECT
-CONFIG_PLL1_CLK_FREQ
-CONFIG_PLL1_DIV2_CLK_FREQ
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
CONFIG_PXA_STD_I2C
CONFIG_PXA_VGA
CONFIG_PXA_VIDEO
-CONFIG_P_CLK_FREQ
CONFIG_QBMAN_CLK_DIV
CONFIG_QE
CONFIG_QEMU_MIPS
CONFIG_SPEAR_UARTCLKMSK
CONFIG_SPEAR_USBBOOT
CONFIG_SPEAR_USBTTY
-CONFIG_SPI
CONFIG_SPI_ADDR
CONFIG_SPI_BOOTING
CONFIG_SPI_CS_IS_VALID
CONFIG_SYS_APP1_SIZE
CONFIG_SYS_APP2_BASE
CONFIG_SYS_APP2_SIZE
-CONFIG_SYS_ARCH_TIMER
CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
CONFIG_SYS_I2C_PINMUX_CLR
CONFIG_SYS_I2C_PINMUX_REG
CONFIG_SYS_I2C_PINMUX_SET
-CONFIG_SYS_I2C_POWERIC_ADDR
CONFIG_SYS_I2C_PXA
CONFIG_SYS_I2C_QIXIS_ADDR
-CONFIG_SYS_I2C_RCAR
CONFIG_SYS_I2C_RTC_ADDR
CONFIG_SYS_I2C_S3C24X0_SLAVE
CONFIG_SYS_I2C_S3C24X0_SPEED
CONFIG_USB_EHCI_MX5
CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
-CONFIG_USB_EHCI_RMOBILE
CONFIG_USB_EHCI_SPEAR
CONFIG_USB_EHCI_SUNXI
CONFIG_USB_EHCI_TEGRA
#include <sandbox-adc.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int dm_test_adc_bind(struct unit_test_state *uts)
{
struct udevice *dev;
#include <asm/eth.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DM_TEST_ETH_NUM 4
static int dm_test_eth(struct unit_test_state *uts)
#include <asm/gpio.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test that sandbox GPIOs work correctly */
static int dm_test_gpio(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of the led uclass */
static int dm_test_led_base(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Basic test of the mmc uclass. We could expand this by implementing an MMC
* stack for sandbox, or at least implementing the basic operation.
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of the phy uclass */
static int dm_test_phy_base(struct unit_test_state *uts)
{
#include <power/sandbox_pmic.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test PMIC get method */
static int dm_test_power_pmic_get(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Basic test of the pwm uclass */
static int dm_test_pwm_base(struct unit_test_state *uts)
{
/*
* Copyright (C) 2015 Google, Inc
-2 *
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of register maps */
static int dm_test_regmap_base(struct unit_test_state *uts)
{
#include <power/sandbox_pmic.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
BUCK1,
BUCK2,
#include <asm/gpio.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test if bus childs got probed propperly*/
static int dm_test_spmi_probe(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of system controllers */
static int dm_test_syscon_base(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Basic test of the timer uclass.
*/
#include <dm/uclass-internal.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test that sandbox USB works correctly */
static int dm_test_usb_base(struct unit_test_state *uts)
{
* in sandbox_sdl_sync() would also need to change to handle the different
* surface depth.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
/* Basic test of the video uclass */
static int dm_test_video_base(struct unit_test_state *uts)
{
txt_fd = STDIN_FILENO;
do {
- filebuf = realloc(filebuf, readlen);
+ filebuf = realloc(filebuf, filesize + readlen);
if (!filebuf) {
fprintf(stderr, "Can't realloc memory for the input file buffer\n");
return EXIT_FAILURE;
}
readbytes = read(txt_fd, filebuf + filesize, readlen);
- if (errno) {
+ if (readbytes < 0) {
fprintf(stderr, "Error while reading stdin: %s\n",
strerror(errno));
return EXIT_FAILURE;
else if (!params.datafile)
usage("Missing data file for auto-FIT (use -d)");
} else if (type != IH_TYPE_INVALID) {
+ if (type == IH_TYPE_SCRIPT && !params.datafile)
+ usage("Missing data file for script (use -d)");
params.type = type;
}
projects / u-boot / commitdiff