ARM: tegra: pinmux: partially handle varying register layouts

Tegra210 moves some bits around in the pinmux registers. Update the code
to handle this.

This doesn't attempt to address the issues with the group-to-group varying
drive group register layout mentioned earlier. This patch handles the
SoC-to-SoC differences in the mux register layout.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 843c688200b3b1d9ceb7e83103790161086d542e..1730d20312b0778048e0e299466611d8d54fc267 100644 (file)
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -101,11 +101,23 @@
 
 #define DRV_REG(group) _R(0x868 + ((group) * 4))
 
+/*
+ * We could force arch-tegraNN/pinmux.h to define all of these. However,
+ * that's a lot of defines, and for now it's manageable to just put a
+ * special case here. It's possible this decision will change with future
+ * SoCs.
+ */
+#ifdef CONFIG_TEGRA210
+#define IO_SHIFT       6
+#define LOCK_SHIFT     7
+#define OD_SHIFT       11
+#else
 #define IO_SHIFT       5
 #define OD_SHIFT       6
 #define LOCK_SHIFT     7
 #define IO_RESET_SHIFT 8
 #define RCV_SEL_SHIFT  9
+#endif
 
 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 /* This register/field only exists on Tegra114 and later */