sdhci0 = "/sdhci@c8000600";
};
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+ };
+
usb@c5000000 {
dr_mode = "otg";
};
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
+
+ lcd_panel: panel {
+ clock = <25175000>;
+ xres = <640>;
+ yres = <480>;
+ left-margin = <48>; /* horizontal back porch */
+ right-margin = <16>; /* horizontal front porch */
+ hsync-len = <96>;
+ lower-margin = <11>; /* vertical front porch */
+ upper-margin = <31>; /* vertical back porch */
+ vsync-len = <2>;
+ hsync-active-high;
+ vsync-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 0>;
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+ nvidia,panel-timings = <0 0 0 0>;
+ };
};
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif
+
+#ifdef CONFIG_VIDEO_TEGRA
+/*
+ * Routine: pin_mux_display
+ * Description: setup the pin muxes/tristate values for the LCD interface)
+ */
+void pin_mux_display(void)
+{
+ /*
+ * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
+ * device-tree
+ */
+ pinmux_tristate_disable(PMUX_PINGRP_DTA);
+
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
+#endif
/* General networking support */
#define CONFIG_CMD_DHCP
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+#define CONFIG_CMD_BMP
+#define CONFIG_LCD_LOGO
+
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND