Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, gd->timer_rate_hz);
+       do_div(tick, gd->arch.timer_rate_hz);
 
        return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-       usec *= gd->timer_rate_hz;
+       usec *= gd->arch.timer_rate_hz;
        do_div(usec, 1000000);
 
        return usec;
        cr |= FTTMR010_TM3_ENABLE;
        writel(cr, &tmr->cr);
 
-       gd->timer_rate_hz = TIMER_CLOCK;
+       gd->arch.timer_rate_hz = TIMER_CLOCK;
        gd->tbu = gd->tbl = 0;
 
        return 0;
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
 
                 * @33.25MHz and 15625 @ 50 MHz
                 */
                gd->tbu = get_PCLK() / (2 * 16 * 100);
-               gd->timer_rate_hz = get_PCLK() / (2 * 16);
+               gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
        }
        /* load value for 10 ms timeout */
        writel(gd->tbu, &timers->tcntb4);
 {
        ulong tmr = get_ticks();
 
-       return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
+       return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 }
 
 void udelay_masked(unsigned long usec)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, gd->timer_rate_hz);
+       do_div(tick, gd->arch.timer_rate_hz);
 
        return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-       usec *= gd->timer_rate_hz;
+       usec *= gd->arch.timer_rate_hz;
        do_div(usec, 1000000);
 
        return usec;
        /* Enable PITC */
        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-       gd->timer_rate_hz = gd->arch.mck_rate_hz / 16;
+       gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
        gd->tbu = gd->tbl = 0;
 
        return 0;
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
 
        writel(0x0, &timer->tim34);
        writel(TIMER_LOAD_VAL, &timer->prd34);
        writel(2 << 22, &timer->tcr);
-       gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
        gd->timer_reset_value = 0;
 
        return(0);
 
        timer_diff = get_ticks() - gd->timer_reset_value;
 
-       return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+       return lldiv(timer_diff,
+                    (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
 }
 
 void __udelay(unsigned long usec)
 {
        unsigned long long endtime;
 
-       endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
+       endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
                        1000000UL);
        endtime += get_ticks();
 
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
 
 #ifdef CONFIG_HW_WATCHDOG
 
        unsigned long   pllb_rate_hz;
        unsigned long   at91_pllb_usb_init;
 #endif
+       /* "static data" needed by most of timer.c on ARM platforms */
+       unsigned long timer_rate_hz;
 };
 
 /*
 #endif
 #ifdef CONFIG_ARM
        /* "static data" needed by most of timer.c on ARM platforms */
-       unsigned long   timer_rate_hz;
        unsigned long   tbl;
        unsigned long   tbu;
        unsigned long long      timer_reset_value;