<file>\r
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>\r
</file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_adc.c</name>\r
- </file>\r
<file>\r
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>\r
</file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>\r
- </file>\r
<file>\r
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>\r
</file>\r
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_tim.c</name>\r
</file>\r
</group>\r
- <group>\r
- <name>TouchSensingDriver</name>\r
- <excluded>\r
- <configuration>Debug</configuration>\r
- </excluded>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_acq.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_acq_stm32l1xx_sw.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_dxs.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_ecs.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_filter.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_globals.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_linrot.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_object.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time_stm32l1xx.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_touchkey.c</name>\r
- </file>\r
- </group>\r
</group>\r
<group>\r
<name>Standard Demo Tasks</name>\r
<name>$PROJ_DIR$\System\system_stm32l1xx.c</name>\r
</file>\r
</group>\r
- <file>\r
- <name>$PROJ_DIR$\discover_functions.c</name>\r
- </file>\r
<file>\r
<name>$PROJ_DIR$\include\FreeRTOSConfig.h</name>\r
</file>\r
- <file>\r
- <name>$PROJ_DIR$\icc_measure.c</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\icc_measure_Ram.c</name>\r
- </file>\r
<file>\r
<name>$PROJ_DIR$\main.c</name>\r
</file>\r
<file>\r
<name>$PROJ_DIR$\STM32L_low_power_tick_management.c</name>\r
</file>\r
- <file>\r
- <name>$PROJ_DIR$\tsl_user.c</name>\r
- </file>\r
</project>\r
\r
\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_adc.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the ADC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_ADC_H\r
-#define __STM32L1xx_ADC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup ADC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief ADC Init structure definition \r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
- This parameter can be a value of @ref ADC_Resolution */\r
- \r
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
- Scan (multichannel) or Single (one channel) mode.\r
- This parameter can be set to ENABLE or DISABLE */\r
- \r
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
- Continuous or Single mode.\r
- This parameter can be set to ENABLE or DISABLE. */\r
- \r
- uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
- trigger of a regular group. This parameter can be a value\r
- of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
- \r
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
- to digital conversion of regular channels. This parameter\r
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
- \r
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
- This parameter can be a value of @ref ADC_data_align */\r
- \r
- uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
- using the sequencer for regular channel group.\r
- This parameter must range from 1 to 27. */\r
-}ADC_InitTypeDef;\r
-\r
-typedef struct \r
-{ \r
- uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
- This parameter can be a value \r
- of @ref ADC_Prescaler */\r
-}ADC_CommonInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup ADC_Exported_Constants\r
- * @{\r
- */ \r
-#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
-#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
-\r
-/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
- * @{\r
- */ \r
-#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
-#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
-#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
-\r
-#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
- ((DWON) == ADC_PowerDown_Idle) || \\r
- ((DWON) == ADC_PowerDown_Idle_Delay))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_Prescaler \r
- * @{\r
- */ \r
-#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
-#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
-#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
-\r
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
- ((PRESCALER) == ADC_Prescaler_Div2) || \\r
- ((PRESCALER) == ADC_Prescaler_Div4))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-\r
-/** @defgroup ADC_Resolution \r
- * @{\r
- */ \r
-#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
-#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
-#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
-#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
-\r
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
- ((RESOLUTION) == ADC_Resolution_10b) || \\r
- ((RESOLUTION) == ADC_Resolution_8b) || \\r
- ((RESOLUTION) == ADC_Resolution_6b))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
- * @{\r
- */ \r
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
-#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
-\r
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
- * @{\r
- */ \r
-\r
-/* TIM2 */\r
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
-#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
-\r
-/* TIM3 */\r
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
-#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
-\r
-/* TIM4 */\r
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
-#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
-\r
-/* TIM6 */\r
-#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
-\r
-/* TIM9 */\r
-#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
-\r
-/* EXTI */\r
-#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
-\r
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_data_align \r
- * @{\r
- */ \r
- \r
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
-\r
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
- ((ALIGN) == ADC_DataAlign_Left))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_channels \r
- * @{\r
- */ \r
-/* ADC Bank A Channels -------------------------------------------------------*/ \r
-#define ADC_Channel_0 ((uint8_t)0x00)\r
-#define ADC_Channel_1 ((uint8_t)0x01)\r
-#define ADC_Channel_2 ((uint8_t)0x02)\r
-#define ADC_Channel_3 ((uint8_t)0x03)\r
-\r
-#define ADC_Channel_6 ((uint8_t)0x06)\r
-#define ADC_Channel_7 ((uint8_t)0x07)\r
-#define ADC_Channel_8 ((uint8_t)0x08)\r
-#define ADC_Channel_9 ((uint8_t)0x09)\r
-#define ADC_Channel_10 ((uint8_t)0x0A)\r
-#define ADC_Channel_11 ((uint8_t)0x0B)\r
-#define ADC_Channel_12 ((uint8_t)0x0C)\r
-\r
-\r
-/* ADC Bank B Channels -------------------------------------------------------*/ \r
-#define ADC_Channel_0b ADC_Channel_0\r
-#define ADC_Channel_1b ADC_Channel_1\r
-#define ADC_Channel_2b ADC_Channel_2\r
-#define ADC_Channel_3b ADC_Channel_3\r
-\r
-#define ADC_Channel_6b ADC_Channel_6\r
-#define ADC_Channel_7b ADC_Channel_7\r
-#define ADC_Channel_8b ADC_Channel_8\r
-#define ADC_Channel_9b ADC_Channel_9\r
-#define ADC_Channel_10b ADC_Channel_10\r
-#define ADC_Channel_11b ADC_Channel_11\r
-#define ADC_Channel_12b ADC_Channel_12\r
-\r
-/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/\r
-#define ADC_Channel_4 ((uint8_t)0x04)\r
-#define ADC_Channel_5 ((uint8_t)0x05)\r
-\r
-#define ADC_Channel_13 ((uint8_t)0x0D)\r
-#define ADC_Channel_14 ((uint8_t)0x0E)\r
-#define ADC_Channel_15 ((uint8_t)0x0F)\r
-#define ADC_Channel_16 ((uint8_t)0x10)\r
-#define ADC_Channel_17 ((uint8_t)0x11)\r
-#define ADC_Channel_18 ((uint8_t)0x12)\r
-#define ADC_Channel_19 ((uint8_t)0x13)\r
-#define ADC_Channel_20 ((uint8_t)0x14)\r
-#define ADC_Channel_21 ((uint8_t)0x15)\r
-#define ADC_Channel_22 ((uint8_t)0x16)\r
-#define ADC_Channel_23 ((uint8_t)0x17)\r
-#define ADC_Channel_24 ((uint8_t)0x18)\r
-#define ADC_Channel_25 ((uint8_t)0x19)\r
-\r
-#define ADC_Channel_27 ((uint8_t)0x1B)\r
-#define ADC_Channel_28 ((uint8_t)0x1C)\r
-#define ADC_Channel_29 ((uint8_t)0x1D)\r
-#define ADC_Channel_30 ((uint8_t)0x1E)\r
-#define ADC_Channel_31 ((uint8_t)0x1F)\r
-\r
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
-\r
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
- ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
- ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
- ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
- ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
- ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
- ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
- ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
- ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
- ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
- ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
- ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
- ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \\r
- ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \\r
- ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \\r
- ((CHANNEL) == ADC_Channel_31))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_sampling_times \r
- * @{\r
- */ \r
-\r
-#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
-#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
-#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
-#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
-#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
-#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
-#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
-#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
-\r
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
- ((TIME) == ADC_SampleTime_9Cycles) || \\r
- ((TIME) == ADC_SampleTime_16Cycles) || \\r
- ((TIME) == ADC_SampleTime_24Cycles) || \\r
- ((TIME) == ADC_SampleTime_48Cycles) || \\r
- ((TIME) == ADC_SampleTime_96Cycles) || \\r
- ((TIME) == ADC_SampleTime_192Cycles) || \\r
- ((TIME) == ADC_SampleTime_384Cycles))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_Delay_length \r
- * @{\r
- */ \r
-\r
-#define ADC_DelayLength_None ((uint8_t)0x00)\r
-#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
-#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
-#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
-#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
-#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
-#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
-#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
-\r
-#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
- ((LENGTH) == ADC_DelayLength_Freeze) || \\r
- ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
- ((LENGTH) == ADC_DelayLength_255Cycles))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
- * @{\r
- */ \r
-#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
-#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
- * @{\r
- */ \r
-\r
-\r
-/* TIM2 */\r
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
-\r
-/* TIM3 */\r
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
-\r
-/* TIM4 */\r
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
-\r
-/* TIM7 */\r
-#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
-\r
-/* TIM9 */\r
-#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
-#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
-\r
-/* TIM10 */\r
-#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
-\r
-/* EXTI */\r
-#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_channel_selection \r
- * @{\r
- */ \r
-#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
-#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
-#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
-#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
-\r
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
- ((CHANNEL) == ADC_InjectedChannel_2) || \\r
- ((CHANNEL) == ADC_InjectedChannel_3) || \\r
- ((CHANNEL) == ADC_InjectedChannel_4))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_analog_watchdog_selection \r
- * @{\r
- */ \r
- \r
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
-\r
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define ADC_IT_AWD ((uint16_t)0x0106) \r
-#define ADC_IT_EOC ((uint16_t)0x0205) \r
-#define ADC_IT_JEOC ((uint16_t)0x0407) \r
-#define ADC_IT_OVR ((uint16_t)0x201A) \r
- \r
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
-#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
-#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
-#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
-#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
-#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
-#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
-#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
-#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
- \r
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
- \r
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
- ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
- ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
- ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
- ((FLAG) == ADC_FLAG_JCNR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_thresholds \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_offset \r
- * @{\r
- */\r
- \r
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_length \r
- * @{\r
- */\r
- \r
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_injected_rank \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_length \r
- * @{\r
- */\r
- \r
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_rank \r
- * @{\r
- */ \r
- \r
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_regular_discontinuous_mode_number \r
- * @{\r
- */\r
- \r
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup ADC_Bank_Selection \r
- * @{\r
- */ \r
-#define ADC_Bank_A ((uint8_t)0x00)\r
-#define ADC_Bank_B ((uint8_t)0x01) \r
-#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the ADC configuration to the default reset state *****/ \r
-void ADC_DeInit(ADC_TypeDef* ADCx); \r
-\r
-/* Initialization and Configuration functions *********************************/ \r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);\r
-\r
-/* Power saving functions *****************************************************/\r
-void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
-void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
-\r
-/* Analog Watchdog configuration functions ************************************/\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
-\r
-/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
-\r
-/* Regular Channels Configuration functions ***********************************/\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
-\r
-/* Regular Channels DMA Configuration functions *******************************/\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-\r
-/* Injected channels Configuration functions **********************************/\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_ADC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_aes.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the AES firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_AES_H\r
-#define __STM32L1xx_AES_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup AES\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/**\r
- * @brief AES Init structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t AES_Operation; /*!< Specifies the AES mode of operation.\r
- This parameter can be a value of @ref AES_possible_Operation_modes */\r
- uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.\r
- This parameter can be a value of @ref AES_possible_chaining_modes */\r
- uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.\r
- This parameter can be a value of @ref AES_Data_Types */\r
-}AES_InitTypeDef;\r
-\r
-/** \r
- * @brief AES Key(s) structure definition\r
- */ \r
-typedef struct\r
-{\r
- uint32_t AES_Key0; /*!< Key[31:0] */\r
- uint32_t AES_Key1; /*!< Key[63:32] */\r
- uint32_t AES_Key2; /*!< Key[95:64] */\r
- uint32_t AES_Key3; /*!< Key[127:96] */\r
-}AES_KeyInitTypeDef;\r
-\r
-/** \r
- * @brief AES Initialization Vectors (IV) structure definition\r
- */ \r
-typedef struct\r
-{\r
- uint32_t AES_IV0; /*!< Init Vector IV[31:0] */\r
- uint32_t AES_IV1; /*!< Init Vector IV[63:32] */\r
- uint32_t AES_IV2; /*!< Init Vector IV[95:64] */\r
- uint32_t AES_IV3; /*!< Init Vector IV[127:96] */\r
-}AES_IVInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup AES_Exported_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup AES_possible_Operation_modes\r
- * @{\r
- */ \r
-#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */\r
-#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */\r
-#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */\r
-#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */\r
-\r
-#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \\r
- ((OPERATION) == AES_Operation_KeyDeriv) || \\r
- ((OPERATION) == AES_Operation_Decryp) || \\r
- ((OPERATION) == AES_Operation_KeyDerivAndDecryp))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup AES_possible_chaining_modes\r
- * @{\r
- */ \r
-#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */\r
-#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */\r
-#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */\r
-\r
-#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \\r
- ((CHAINING) == AES_Chaining_CBC) || \\r
- ((CHAINING) == AES_Chaining_CTR))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Data_Types\r
- * @{\r
- */ \r
-#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */\r
-#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */\r
-#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */\r
-#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */\r
-\r
-#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \\r
- ((DATATYPE) == AES_DataType_16b)|| \\r
- ((DATATYPE) == AES_DataType_8b) || \\r
- ((DATATYPE) == AES_DataType_1b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Flags\r
- * @{\r
- */ \r
-#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */\r
-#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */\r
-#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */\r
-\r
-#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \\r
- ((FLAG) == AES_FLAG_RDERR) || \\r
- ((FLAG) == AES_FLAG_WRERR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup AES_Interrupts\r
- * @{\r
- */ \r
-#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */\r
-#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */\r
-\r
-#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))\r
-#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_DMA_Transfer_modes\r
- * @{\r
- */ \r
-#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */\r
-#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */\r
-#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */\r
-\r
-#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \\r
- ((TRANSFER) == AES_DMATransfer_Out) || \\r
- ((TRANSFER) == AES_DMATransfer_InOut))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Initialization and configuration functions *********************************/\r
-void AES_DeInit(void);\r
-void AES_Init(AES_InitTypeDef* AES_InitStruct);\r
-void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
-void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);\r
-void AES_Cmd(FunctionalState NewState);\r
-\r
-/* Structures initialization functions ****************************************/\r
-void AES_StructInit(AES_InitTypeDef* AES_InitStruct);\r
-void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
-void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);\r
-\r
-/* AES Read and Write functions **********************************************/ \r
-void AES_WriteSubData(uint32_t Data);\r
-uint32_t AES_ReadSubData(void);\r
-void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
-void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);\r
-\r
-/* DMA transfers management function ******************************************/\r
-void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);\r
-FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);\r
-void AES_ClearFlag(uint32_t AES_FLAG);\r
-ITStatus AES_GetITStatus(uint32_t AES_IT);\r
-void AES_ClearITPendingBit(uint32_t AES_IT);\r
-\r
-/* High Level AES functions **************************************************/\r
-ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_AES_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_comp.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the COMP firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_COMP_H\r
-#define __STM32L1xx_COMP_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup COMP\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief COMP Init structure definition \r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.\r
- This parameter can be a value of @ref COMP_Speed */\r
- uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.\r
- This parameter can be a value of @ref COMP_InvertingInput */\r
- uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.\r
- This parameter can be a value of @ref COMP_OutputSelect */\r
- \r
-}COMP_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
- \r
-/** @defgroup COMP_Exported_Constants\r
- * @{\r
- */ \r
-\r
-#define COMP_OutputLevel_High ((uint32_t)0x00000001)\r
-#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
-\r
-/** @defgroup COMP_Selection\r
- * @{\r
- */\r
-\r
-#define COMP_Selection_COMP1 ((uint32_t)0x00000001)\r
-#define COMP_Selection_COMP2 ((uint32_t)0x00000002)\r
-\r
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
- ((PERIPH) == COMP_Selection_COMP2))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup COMP_InvertingInput\r
- * @{\r
- */\r
-\r
-#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */\r
-#define COMP_InvertingInput_IO ((uint32_t)0x00040000)\r
-#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)\r
-#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)\r
-#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)\r
-#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)\r
-#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)\r
-#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)\r
-\r
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \\r
- ((INPUT) == COMP_InvertingInput_IO) || \\r
- ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
- ((INPUT) == COMP_InvertingInput_DAC1) || \\r
- ((INPUT) == COMP_InvertingInput_DAC2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup COMP_OutputSelect\r
- * @{\r
- */\r
-\r
-#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)\r
-#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)\r
-#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)\r
-#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)\r
-#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)\r
-#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)\r
-#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)\r
-#define COMP_OutputSelect_None ((uint32_t)0x00E00000)\r
-\r
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \\r
- ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \\r
- ((OUTPUT) == COMP_OutputSelect_None))\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup COMP_Speed\r
- * @{\r
- */\r
-\r
-#define COMP_Speed_Slow ((uint32_t)0x00000000)\r
-#define COMP_Speed_Fast ((uint32_t)0x00001000)\r
-\r
-#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \\r
- ((SPEED) == COMP_Speed_Fast))\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the COMP configuration to the default reset state ****/\r
-void COMP_DeInit(void);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);\r
-void COMP_Cmd(FunctionalState NewState);\r
-uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
-void COMP_SW1SwitchConfig(FunctionalState NewState);\r
-\r
-/* Window mode control function ***********************************************/\r
-void COMP_WindowCmd(FunctionalState NewState);\r
-\r
-/* Internal Reference Voltage (VREFINT) output function ***********************/\r
-void COMP_VrefintOutputCmd(FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_COMP_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_crc.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the CRC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_CRC_H\r
-#define __STM32L1xx_CRC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CRC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup CRC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-void CRC_ResetDR(void);\r
-uint32_t CRC_CalcCRC(uint32_t Data);\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
-uint32_t CRC_GetCRC(void);\r
-void CRC_SetIDRegister(uint8_t IDValue);\r
-uint8_t CRC_GetIDRegister(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_CRC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dac.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the DAC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DAC_H\r
-#define __STM32L1xx_DAC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
- \r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DAC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief DAC Init structure definition\r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
- This parameter can be a value of @ref DAC_trigger_selection */\r
-\r
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
- are generated, or whether no wave is generated.\r
- This parameter can be a value of @ref DAC_wave_generation */\r
-\r
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
- the maximum amplitude triangle generation for the DAC channel. \r
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
-\r
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
- This parameter can be a value of @ref DAC_output_buffer */\r
-}DAC_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DAC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_trigger_selection \r
- * @{\r
- */\r
- \r
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
- has been loaded, and not by external trigger */\r
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
-\r
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T9_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
- ((TRIGGER) == DAC_Trigger_Software))\r
- \r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
- ((WAVE) == DAC_WaveGeneration_Noise) || \\r
- ((WAVE) == DAC_WaveGeneration_Triangle))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_lfsrunmask_triangleamplitude\r
- * @{\r
- */\r
-\r
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
-\r
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1) || \\r
- ((VALUE) == DAC_TriangleAmplitude_3) || \\r
- ((VALUE) == DAC_TriangleAmplitude_7) || \\r
- ((VALUE) == DAC_TriangleAmplitude_15) || \\r
- ((VALUE) == DAC_TriangleAmplitude_31) || \\r
- ((VALUE) == DAC_TriangleAmplitude_63) || \\r
- ((VALUE) == DAC_TriangleAmplitude_127) || \\r
- ((VALUE) == DAC_TriangleAmplitude_255) || \\r
- ((VALUE) == DAC_TriangleAmplitude_511) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
- ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
- ((VALUE) == DAC_TriangleAmplitude_4095))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_output_buffer \r
- * @{\r
- */\r
-\r
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
- ((STATE) == DAC_OutputBuffer_Disable))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup DAC_Channel_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Channel_1 ((uint32_t)0x00000000)\r
-#define DAC_Channel_2 ((uint32_t)0x00000010)\r
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
- ((CHANNEL) == DAC_Channel_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data_alignment \r
- * @{\r
- */\r
-\r
-#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
-#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
-#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
- ((ALIGN) == DAC_Align_12b_L) || \\r
- ((ALIGN) == DAC_Align_8b_R))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
- ((WAVE) == DAC_Wave_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data \r
- * @{\r
- */\r
-\r
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup DAC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
- \r
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the DAC configuration to the default reset state *****/ \r
-void DAC_DeInit(void);\r
-\r
-/* DAC channels configuration: trigger, output buffer, data format functions */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
-\r
-/* DMA management functions ***************************************************/\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_DAC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dbgmcu.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the DBGMCU \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DBGMCU_H\r
-#define __STM32L1xx_DBGMCU_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DBGMCU\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
-#define DBGMCU_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)\r
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
-#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)\r
-#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)\r
-#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)\r
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-uint32_t DBGMCU_GetREVID(void);\r
-uint32_t DBGMCU_GetDEVID(void);\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_DBGMCU_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dma.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the DMA firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_DMA_H\r
-#define __STM32L1xx_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief DMA Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
- This parameter can be a value of @ref DMA_data_transfer_direction */\r
-\r
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
- The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
- or DMA_MemoryDataSize members depending in the transfer direction. */\r
-\r
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
-\r
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
- This parameter can be a value of @ref DMA_memory_incremented_mode */\r
-\r
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
- This parameter can be a value of @ref DMA_peripheral_data_size */\r
-\r
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
- This parameter can be a value of @ref DMA_memory_data_size */\r
-\r
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_circular_normal_mode\r
- @note: The circular buffer mode cannot be used if the memory-to-memory\r
- data transfer is configured on the selected Channel */\r
-\r
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_priority_level */\r
-\r
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
- This parameter can be a value of @ref DMA_memory_to_memory */\r
-}DMA_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
- ((PERIPH) == DMA1_Channel2) || \\r
- ((PERIPH) == DMA1_Channel3) || \\r
- ((PERIPH) == DMA1_Channel4) || \\r
- ((PERIPH) == DMA1_Channel5) || \\r
- ((PERIPH) == DMA1_Channel6) || \\r
- ((PERIPH) == DMA1_Channel7) || \\r
- ((PERIPH) == DMA2_Channel1) || \\r
- ((PERIPH) == DMA2_Channel2) || \\r
- ((PERIPH) == DMA2_Channel3) || \\r
- ((PERIPH) == DMA2_Channel4) || \\r
- ((PERIPH) == DMA2_Channel5))\r
-\r
-/** @defgroup DMA_data_transfer_direction \r
- * @{\r
- */\r
-\r
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
- ((DIR) == DMA_DIR_PeripheralSRC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
- ((STATE) == DMA_PeripheralInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
- ((STATE) == DMA_MemoryInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
- ((SIZE) == DMA_PeripheralDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
- ((SIZE) == DMA_MemoryDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_circular_normal_mode \r
- * @{\r
- */\r
-\r
-#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
-#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_priority_level \r
- * @{\r
- */\r
-\r
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
-#define DMA_Priority_High ((uint32_t)0x00002000)\r
-#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
-#define DMA_Priority_Low ((uint32_t)0x00000000)\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
- ((PRIORITY) == DMA_Priority_High) || \\r
- ((PRIORITY) == DMA_Priority_Medium) || \\r
- ((PRIORITY) == DMA_Priority_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_to_memory \r
- * @{\r
- */\r
-\r
-#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
-#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define DMA_IT_TC ((uint32_t)0x00000002)\r
-#define DMA_IT_HT ((uint32_t)0x00000004)\r
-#define DMA_IT_TE ((uint32_t)0x00000008)\r
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
-\r
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
-\r
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
- ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
- ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
- ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
- ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
- ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
- ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
- ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
- ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
- ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
- ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_flags_definition \r
- * @{\r
- */\r
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
-\r
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
- ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
- ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
- ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
- ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
- ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
- ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
- ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
- ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
- ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
- ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Buffer_Size \r
- * @{\r
- */\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the DMA configuration to the default reset state *****/ \r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
-\r
-/* Data Counter functions *****************************************************/\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);\r
-void DMA_ClearFlag(uint32_t DMAy_FLAG);\r
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT);\r
-void DMA_ClearITPendingBit(uint32_t DMAy_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_DMA_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the FLASH \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_FLASH_H\r
-#define __STM32L1xx_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief FLASH Status \r
- */ \r
-typedef enum\r
-{ \r
- FLASH_BUSY = 1,\r
- FLASH_ERROR_WRP,\r
- FLASH_ERROR_PROGRAM,\r
- FLASH_COMPLETE,\r
- FLASH_TIMEOUT\r
-}FLASH_Status;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup FLASH_Latency \r
- * @{\r
- */ \r
-#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */\r
-#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */\r
-\r
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
- ((LATENCY) == FLASH_Latency_1))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Interrupts \r
- * @{\r
- */\r
- \r
-#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
-#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Address \r
- * @{\r
- */\r
- \r
-#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Option_Bytes_Write_Protection \r
- * @{\r
- */\r
- \r
-#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */\r
-#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */\r
-#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */\r
-#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */\r
-#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */\r
-#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */\r
-#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */\r
-#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */\r
-#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */\r
-#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */\r
-#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */\r
-#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */\r
-#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */\r
-#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */\r
-#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */\r
-#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */\r
-#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */\r
-#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */\r
-#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */\r
-#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */\r
-#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */\r
-#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */\r
-#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */\r
-#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */\r
-#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */\r
-#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */\r
-#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */\r
-#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */\r
-#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */\r
-#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */\r
-#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */\r
-#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */\r
-\r
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
-\r
-#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */\r
-#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */\r
-#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */\r
-#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */\r
-#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */\r
-#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */\r
-#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */\r
-#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */\r
-#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */\r
-#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */\r
-#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */\r
-#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */\r
-#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */\r
-#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */\r
-#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */\r
-#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */\r
-#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */\r
-#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */\r
-#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */\r
-#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */\r
-#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */\r
-#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */\r
-#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */\r
-#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */\r
-#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */\r
-#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */\r
-#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */\r
-#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */\r
-#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */\r
-#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */\r
-#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */\r
-#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */\r
-\r
-#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
-\r
-#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */\r
-#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */\r
-#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */\r
-#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */\r
-#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */\r
-#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */\r
-#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */\r
-#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */\r
-#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */\r
-#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */\r
-#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */\r
-#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */\r
-#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */\r
-#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */\r
-#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */\r
-#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */\r
-#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */\r
-#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */\r
-#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */\r
-#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */\r
-#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */\r
-#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */\r
-#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */\r
-#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */\r
-#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */\r
-#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */\r
-#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */\r
-#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */\r
-#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */\r
-#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */\r
-#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */\r
-#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */\r
-\r
-#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
-\r
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_Read_Protection \r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Read Protection Level \r
- */ \r
-#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
-#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
- it's no more possible to go back to level 1 or 0 */\r
-\r
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
- ((LEVEL) == OB_RDP_Level_1))/*||\\r
- ((LEVEL) == OB_RDP_Level_2))*/\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Option_Bytes_IWatchdog \r
- * @{\r
- */\r
-\r
-#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */\r
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */\r
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STOP \r
- * @{\r
- */\r
-\r
-#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */\r
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STDBY \r
- * @{\r
- */\r
-\r
-#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */\r
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_BOOT\r
- * @{\r
- */\r
-\r
-#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank 2 \r
- or Bank 1, depending on the activation of the bank */\r
-#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank1(Default) */\r
-#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_BOR_Level \r
- * @{\r
- */\r
-\r
-#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
- power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
-#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
-#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
-#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
-#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
-#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
-\r
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \\r
- ((LEVEL) == OB_BOR_LEVEL1) || \\r
- ((LEVEL) == OB_BOR_LEVEL2) || \\r
- ((LEVEL) == OB_BOR_LEVEL3) || \\r
- ((LEVEL) == OB_BOR_LEVEL4) || \\r
- ((LEVEL) == OB_BOR_LEVEL5))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASH_Flags \r
- * @{\r
- */ \r
-\r
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
-#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */\r
-#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
-#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
-#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
-#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))\r
-\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \\r
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \\r
- ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \\r
- ((FLAG) == FLASH_FLAG_OPTVERRUSR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Keys \r
- * @{\r
- */ \r
-\r
-#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */\r
-#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
- to unlock the RUN_PD bit in FLASH_ACR */\r
-\r
-#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */\r
-#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2\r
- to unlock the write access to the FLASH_PECR register and\r
- data EEPROM */\r
-\r
-#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */\r
-#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
- to unlock the program memory */\r
-\r
-#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */\r
-#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
- unlock the write access to the option byte block */\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup Timeout_definition \r
- * @{\r
- */ \r
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup CMSIS_Legacy \r
- * @{\r
- */\r
-#if defined ( __ICCARM__ ) \r
-#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk\r
-#endif\r
-/**\r
- * @}\r
- */ \r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
- \r
-/** \r
- * @brief FLASH memory functions that can be executed from FLASH. \r
- */ \r
-/* FLASH Interface configuration functions ************************************/ \r
-void FLASH_SetLatency(uint32_t FLASH_Latency);\r
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
-void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
-void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
-\r
-/* FLASH Memory Programming functions *****************************************/ \r
-void FLASH_Unlock(void);\r
-void FLASH_Lock(void);\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
-FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
-\r
-/* DATA EEPROM Programming functions ******************************************/ \r
-void DATA_EEPROM_Unlock(void);\r
-void DATA_EEPROM_Lock(void);\r
-void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);\r
-FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);\r
-FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);\r
-FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
-FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
-FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
-\r
-/* Option Bytes Programming functions *****************************************/\r
-void FLASH_OB_Unlock(void);\r
-void FLASH_OB_Lock(void);\r
-void FLASH_OB_Launch(void);\r
-FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
-FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);\r
-FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);\r
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
-FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
-FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);\r
-uint8_t FLASH_OB_GetUser(void);\r
-uint32_t FLASH_OB_GetWRP(void);\r
-uint32_t FLASH_OB_GetWRP1(void);\r
-uint32_t FLASH_OB_GetWRP2(void);\r
-FlagStatus FLASH_OB_GetRDP(void);\r
-uint8_t FLASH_OB_GetBOR(void);\r
-\r
-/* Interrupts and flags management functions **********************************/ \r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
-FLASH_Status FLASH_GetStatus(void);\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
-\r
-/** \r
- * @brief FLASH memory functions that should be executed from internal SRAM.\r
- * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"\r
- * file.\r
- */ \r
-__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
-__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);\r
-__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);\r
-__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);\r
-__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);\r
-__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_FLASH_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_fsmc.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the FSMC firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_FSMC_H\r
-#define __STM32L1xx_FSMC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FSMC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief Timing parameters For NOR/SRAM Banks \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address setup time. \r
- This parameter can be a value between 0 and 0xF.\r
- @note It is not used with synchronous NOR Flash memories. */\r
-\r
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address hold time.\r
- This parameter can be a value between 0 and 0xF. \r
- @note It is not used with synchronous NOR Flash memories.*/\r
-\r
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the data setup time.\r
- This parameter can be a value between 0 and 0xFF.\r
- @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the bus turnaround.\r
- This parameter can be a value between 0 and 0xF.\r
- @note It is only used for multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
- This parameter can be a value between 1 and 0xF.\r
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
-\r
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
- to the memory before getting the first data.\r
- The parameter value depends on the memory type as shown below:\r
- - It must be set to 0 in case of a CRAM\r
- - It is don't care in asynchronous NOR, SRAM or ROM accesses\r
- - It may assume a value between 0 and 0xF in NOR Flash memories\r
- with synchronous burst mode enable */\r
-\r
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
- This parameter can be a value of @ref FSMC_Access_Mode */\r
-}FSMC_NORSRAMTimingInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC NOR/SRAM Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
-\r
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
- multiplexed on the databus or not. \r
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
-\r
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
- the corresponding memory bank.\r
- This parameter can be a value of @ref FSMC_Memory_Type */\r
-\r
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
- This parameter can be a value of @ref FSMC_Data_Width */\r
-\r
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
- valid only with synchronous burst Flash memories.\r
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
- \r
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
- valid only with asynchronous Flash memories.\r
- This parameter can be a value of @ref FSMC_AsynchronousWait */\r
-\r
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
- the Flash memory in burst mode.\r
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
-\r
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
- memory, valid only when accessing Flash memories in burst mode.\r
- This parameter can be a value of @ref FSMC_Wrap_Mode */\r
-\r
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
- clock cycle before the wait state or during the wait state,\r
- valid only when accessing memories in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Timing */\r
-\r
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
- This parameter can be a value of @ref FSMC_Write_Operation */\r
-\r
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
- signal, valid for Flash memory access in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Signal */\r
-\r
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
- This parameter can be a value of @ref FSMC_Extended_Mode */\r
-\r
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
- This parameter can be a value of @ref FSMC_Write_Burst */ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
-}FSMC_NORSRAMInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup FSMC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_NORSRAM_Bank \r
- * @{\r
- */\r
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
-\r
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup NOR_SRAM_Controller \r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
- * @{\r
- */\r
-\r
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
- ((MUX) == FSMC_DataAddressMux_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Memory_Type \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
- ((MEMORY) == FSMC_MemoryType_NOR))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Width \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
- ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Burst_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
- ((STATE) == FSMC_BurstAccessMode_Enable))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FSMC_AsynchronousWait \r
- * @{\r
- */\r
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
- ((STATE) == FSMC_AsynchronousWait_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FSMC_Wait_Signal_Polarity \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
- ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wrap_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
- ((MODE) == FSMC_WrapMode_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Timing \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Operation \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
- ((OPERATION) == FSMC_WriteOperation_Enable))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Signal \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
- ((SIGNAL) == FSMC_WaitSignal_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Extended_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
-\r
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
- ((MODE) == FSMC_ExtendedMode_Enable)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Burst \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
- ((BURST) == FSMC_WriteBurst_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Hold_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Bus_Turn_around_Duration \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_CLK_Division \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Latency \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
-#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
- ((MODE) == FSMC_AccessMode_B) || \\r
- ((MODE) == FSMC_AccessMode_C) || \\r
- ((MODE) == FSMC_AccessMode_D)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-/* NOR/SRAM Controller functions **********************************************/\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_FSMC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_i2c.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the I2C firmware \r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_I2C_H\r
-#define __STM32L1xx_I2C_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup I2C\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief I2C Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
- This parameter must be set to a value lower than 400kHz */\r
-\r
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
- This parameter can be a value of @ref I2C_mode */\r
-\r
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
-\r
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
- This parameter can be a 7-bit or 10-bit address. */\r
-\r
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
- This parameter can be a value of @ref I2C_acknowledgement */\r
-\r
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
- This parameter can be a value of @ref I2C_acknowledged_address */\r
-}I2C_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup I2C_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
- ((PERIPH) == I2C2))\r
-/** @defgroup I2C_mode \r
- * @{\r
- */\r
-\r
-#define I2C_Mode_I2C ((uint16_t)0x0000)\r
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
- ((MODE) == I2C_Mode_SMBusDevice) || \\r
- ((MODE) == I2C_Mode_SMBusHost))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_duty_cycle_in_fast_mode \r
- * @{\r
- */\r
-\r
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
- ((CYCLE) == I2C_DutyCycle_2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_acknowledgement\r
- * @{\r
- */\r
-\r
-#define I2C_Ack_Enable ((uint16_t)0x0400)\r
-#define I2C_Ack_Disable ((uint16_t)0x0000)\r
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
- ((STATE) == I2C_Ack_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_transfer_direction \r
- * @{\r
- */\r
-\r
-#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
-#define I2C_Direction_Receiver ((uint8_t)0x01)\r
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
- ((DIRECTION) == I2C_Direction_Receiver))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_acknowledged_address \r
- * @{\r
- */\r
-\r
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_registers \r
- * @{\r
- */\r
-\r
-#define I2C_Register_CR1 ((uint8_t)0x00)\r
-#define I2C_Register_CR2 ((uint8_t)0x04)\r
-#define I2C_Register_OAR1 ((uint8_t)0x08)\r
-#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
-#define I2C_Register_DR ((uint8_t)0x10)\r
-#define I2C_Register_SR1 ((uint8_t)0x14)\r
-#define I2C_Register_SR2 ((uint8_t)0x18)\r
-#define I2C_Register_CCR ((uint8_t)0x1C)\r
-#define I2C_Register_TRISE ((uint8_t)0x20)\r
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
- ((REGISTER) == I2C_Register_CR2) || \\r
- ((REGISTER) == I2C_Register_OAR1) || \\r
- ((REGISTER) == I2C_Register_OAR2) || \\r
- ((REGISTER) == I2C_Register_DR) || \\r
- ((REGISTER) == I2C_Register_SR1) || \\r
- ((REGISTER) == I2C_Register_SR2) || \\r
- ((REGISTER) == I2C_Register_CCR) || \\r
- ((REGISTER) == I2C_Register_TRISE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_SMBus_alert_pin_level \r
- * @{\r
- */\r
-\r
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
- ((ALERT) == I2C_SMBusAlert_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_PEC_position \r
- * @{\r
- */\r
-\r
-#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
- ((POSITION) == I2C_PECPosition_Current))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_NACK_position \r
- * @{\r
- */\r
-\r
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)\r
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)\r
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \\r
- ((POSITION) == I2C_NACKPosition_Current))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_BUF ((uint16_t)0x0400)\r
-#define I2C_IT_EVT ((uint16_t)0x0200)\r
-#define I2C_IT_ERR ((uint16_t)0x0100)\r
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
-#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
-#define I2C_IT_OVR ((uint32_t)0x01000800)\r
-#define I2C_IT_AF ((uint32_t)0x01000400)\r
-#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
-#define I2C_IT_BERR ((uint32_t)0x01000100)\r
-#define I2C_IT_TXE ((uint32_t)0x06000080)\r
-#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
-#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
-#define I2C_IT_BTF ((uint32_t)0x02000004)\r
-#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
-#define I2C_IT_SB ((uint32_t)0x02000001)\r
-\r
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_flags_definition \r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SR2 register flags \r
- */\r
-\r
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
-\r
-/** \r
- * @brief SR1 register flags \r
- */\r
-\r
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
-#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
-#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
-\r
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
- ((FLAG) == I2C_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Events \r
- * @{\r
- */\r
-\r
-/**\r
- ===============================================================================\r
- I2C Master Events (Events grouped in order of communication)\r
- ===============================================================================\r
- */\r
-\r
-/** \r
- * @brief Communication start\r
- * \r
- * After sending the START condition (I2C_GenerateSTART() function) the master \r
- * has to wait for this event. It means that the Start condition has been correctly \r
- * released on the I2C bus (the bus is free, no other devices is communicating).\r
- * \r
- */\r
-/* --EV5 */\r
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
-\r
-/** \r
- * @brief Address Acknowledge\r
- * \r
- * After checking on EV5 (start condition correctly released on the bus), the \r
- * master sends the address of the slave(s) with which it will communicate \r
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
- * his address. If an acknowledge is sent on the bus, one of the following events will \r
- * be set:\r
- * \r
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
- * event is set.\r
- * \r
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
- * is set\r
- * \r
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
- * function). Then master should wait on EV9. It means that the 10-bit addressing \r
- * header has been correctly sent on the bus. Then master should send the second part of \r
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
- * should wait for event EV6. \r
- * \r
- */\r
-\r
-/* --EV6 */\r
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
-/* --EV9 */\r
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * If a communication is established (START condition generated and slave address \r
- * acknowledged) then the master has to check on one of the following events for \r
- * communication procedures:\r
- * \r
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
- * the data received from the slave (I2C_ReceiveData() function).\r
- * \r
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
- * function) then to wait on event EV8 or EV8_2.\r
- * These two events are similar: \r
- * - EV8 means that the data has been written in the data register and is \r
- * being shifted out.\r
- * - EV8_2 means that the data has been physically shifted out and output \r
- * on the bus.\r
- * In most cases, using EV8 is sufficient for the application.\r
- * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
- * (before Stop condition generation).\r
- * \r
- * @note In case the user software does not guarantee that this event EV7 is \r
- * managed before the current byte end of transfer, then user may check on EV7 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- * \r
- */\r
-\r
-/* Master RECEIVER mode -----------------------------*/ \r
-/* --EV7 */\r
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
-\r
-/* Master TRANSMITTER mode --------------------------*/\r
-/* --EV8 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
-/* --EV8_2 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
-\r
-\r
-/**\r
- ===============================================================================\r
- I2C Slave Events (Events grouped in order of communication)\r
- ===============================================================================\r
- */\r
-\r
-\r
-/** \r
- * @brief Communication start events\r
- * \r
- * Wait on one of these events at the start of the communication. It means that \r
- * the I2C peripheral detected a Start condition on the bus (generated by master \r
- * device) followed by the peripheral address. The peripheral generates an ACK \r
- * condition on the bus (if the acknowledge feature is enabled through function \r
- * I2C_AcknowledgeConfig()) and the events listed above are set :\r
- * \r
- * 1) In normal case (only one address managed by the slave), when the address \r
- * sent by the master matches the own address of the peripheral (configured by \r
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
- * (where XXX could be TRANSMITTER or RECEIVER).\r
- * \r
- * 2) In case the address sent by the master matches the second address of the \r
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
- * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
- * \r
- * 3) In case the address sent by the master is General Call (address 0x00) and \r
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
- * \r
- */\r
-\r
-/* --EV1 (all the events below are variants of EV1) */ \r
-/* 1) Case of One Single Address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
-\r
-/* 2) Case of Dual address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
-\r
-/* 3) Case of General Call enabled for the slave */\r
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * Wait on one of these events when EV1 has already been checked and: \r
- * \r
- * - Slave RECEIVER mode:\r
- * - EV2: When the application is expecting a data byte to be received. \r
- * - EV4: When the application is expecting the end of the communication: master \r
- * sends a stop condition and data transmission is stopped.\r
- * \r
- * - Slave Transmitter mode:\r
- * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
- * used when the user software doesn't guarantee the EV3 is managed before the\r
- * current byte end of transfer.\r
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
- * shall end (before sending the STOP condition). In this case slave has to stop sending \r
- * data bytes and expect a Stop condition on the bus.\r
- * \r
- * @note In case the user software does not guarantee that the event EV2 is \r
- * managed before the current byte end of transfer, then user may check on EV2 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- *\r
- */\r
-\r
-/* Slave RECEIVER mode --------------------------*/ \r
-/* --EV2 */\r
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
-/* --EV4 */\r
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
-\r
-/* Slave TRANSMITTER mode -----------------------*/\r
-/* --EV3 */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
-/* --EV3_2 */\r
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
-\r
-/*\r
- ===============================================================================\r
- End of Events Description\r
- ===============================================================================\r
- */\r
-\r
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_own_address1 \r
- * @{\r
- */\r
-\r
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_clock_speed \r
- * @{\r
- */\r
-\r
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the I2C configuration to the default reset state *****/\r
-void I2C_DeInit(I2C_TypeDef* I2Cx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);\r
-\r
-/* PEC management functions ***************************************************/ \r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-\r
-\r
-/* Interrupts, events and flags management functions **************************/\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
-\r
-/*\r
-\r
- ===============================================================================\r
- I2C State Monitoring Functions\r
- ===============================================================================\r
- This I2C driver provides three different ways for I2C state monitoring\r
- depending on the application requirements and constraints:\r
- \r
- \r
- 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
- -----------------------------------------------------------\r
- It compares the status registers (SR1 and SR2) content to a given event\r
- (can be the combination of one or more flags).\r
- It returns SUCCESS if the current status includes the given flags \r
- and returns ERROR if one or more flags are missing in the current status.\r
-\r
- - When to use\r
- - This function is suitable for most applications as well as for startup \r
- activity since the events are fully described in the product reference \r
- manual (RM0038).\r
- - It is also suitable for users who need to define their own events.\r
-\r
- - Limitations\r
- - If an error occurs (ie. error flags are set besides to the monitored \r
- flags), the I2C_CheckEvent() function may return SUCCESS despite \r
- the communication hold or corrupted real state. \r
- In this case, it is advised to use error interrupts to monitor \r
- the error events and handle them in the interrupt IRQ handler.\r
- \r
- Note\r
- For error management, it is advised to use the following functions:\r
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
- Where x is the peripheral instance (I2C1, I2C2 ...)\r
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
- and/or I2C_GenerateStop() in order to clear the error flag and source \r
- and return to correct communciation status.\r
- \r
- \r
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
- -------------------------------------------------------------------- \r
- Using the function I2C_GetLastEvent() which returns the image of both status \r
- registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- by 16 bits and concatenated to Status Register 1).\r
-\r
- - When to use\r
- - This function is suitable for the same applications above but it \r
- allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
- function.\r
- - The returned value could be compared to events already defined in \r
- the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
- This function is suitable when multiple flags are monitored at the \r
- same time.\r
- - At the opposite of I2C_CheckEvent() function, this function allows \r
- user to choose when an event is accepted (when all events flags are \r
- set and no other flags are set or just when the needed flags are set \r
- like I2C_CheckEvent() function.\r
-\r
- - Limitations\r
- - User may need to define his own events.\r
- - Same remark concerning the error management is applicable for this \r
- function if user decides to check only regular communication flags \r
- (and ignores error flags).\r
- \r
- \r
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
- -----------------------------------------------------------------------\r
- \r
- Using the function I2C_GetFlagStatus() which simply returns the status of \r
- one single flag (ie. I2C_FLAG_RXNE ...). \r
-\r
- - When to use\r
- - This function could be used for specific applications or in debug \r
- phase.\r
- - It is suitable when only one flag checking is needed (most I2C \r
- events are monitored through multiple flags).\r
- - Limitations: \r
- - When calling this function, the Status register is accessed. \r
- Some flags are cleared when the status register is accessed. \r
- So checking the status of one Flag, may clear other ones.\r
- - Function may need to be called twice or more in order to monitor \r
- one single event.\r
-\r
- For detailed description of Events, please refer to section I2C_Events in \r
- stm32l1xx_i2c.h file.\r
-\r
-*/\r
-\r
-/*\r
- ===============================================================================\r
- 1. Basic state monitoring\r
- ===============================================================================\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
-/*\r
- ===============================================================================\r
- 2. Advanced state monitoring\r
- ===============================================================================\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
-/*\r
- ===============================================================================\r
- 3. Flag-based state monitoring\r
- ===============================================================================\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-\r
-\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_I2C_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_iwdg.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the IWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_IWDG_H\r
-#define __STM32L1xx_IWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup IWDG\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup IWDG_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_WriteAccess\r
- * @{\r
- */\r
-\r
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
- ((ACCESS) == IWDG_WriteAccess_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_prescaler \r
- * @{\r
- */\r
-\r
-#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
-#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
-#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
-#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
-#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
-#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
-#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
- ((PRESCALER) == IWDG_Prescaler_8) || \\r
- ((PRESCALER) == IWDG_Prescaler_16) || \\r
- ((PRESCALER) == IWDG_Prescaler_32) || \\r
- ((PRESCALER) == IWDG_Prescaler_64) || \\r
- ((PRESCALER) == IWDG_Prescaler_128)|| \\r
- ((PRESCALER) == IWDG_Prescaler_256))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Flag \r
- * @{\r
- */\r
-\r
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Prescaler and Counter configuration functions ******************************/\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
-void IWDG_SetReload(uint16_t Reload);\r
-void IWDG_ReloadCounter(void);\r
-\r
-/* IWDG activation function ***************************************************/\r
-void IWDG_Enable(void);\r
-\r
-/* Flag management function ***************************************************/\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_IWDG_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_opamp.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the operational\r
- * amplifiers (opamp) firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_OPAMP_H\r
-#define __STM32L1xx_OPAMP_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup OPAMP\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup OPAMP_Exported_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup OPAMP_Selection\r
- * @{\r
- */\r
-\r
-#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD\r
-#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD\r
-#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD\r
-\r
-#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \\r
- ((PERIPH) == OPAMP_Selection_OPAMP2) || \\r
- ((PERIPH) == OPAMP_Selection_OPAMP3))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OPAMP_Switches\r
- * @{\r
- */\r
-\r
-/* OPAMP1 Switches */\r
-#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */\r
-#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */\r
-#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */\r
-#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */\r
-#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */\r
-\r
-/* OPAMP2 Switches */\r
-#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */\r
-#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */\r
-#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */\r
-#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */\r
-#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */\r
-#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */\r
-\r
-/* OPAMP3 Switches */\r
-#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */\r
-#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */\r
-#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */\r
-#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */\r
-#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */\r
-\r
-#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OPAMP_Trimming\r
- * @{\r
- */\r
-\r
-#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */\r
-#define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */\r
-\r
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \\r
- ((TRIMMING) == OPAMP_Trimming_User))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OPAMP_Input\r
- * @{\r
- */\r
-\r
-#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */\r
-#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */\r
-\r
-#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \\r
- ((INPUT) == OPAMP_Input_PMOS))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OPAMP_TrimValue\r
- * @{\r
- */\r
-\r
-#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup OPAMP_PowerRange\r
- * @{\r
- */\r
-\r
-#define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */\r
-#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */\r
-\r
-#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \\r
- ((RANGE) == OPAMP_PowerRange_High))\r
-\r
-/**\r
- * @}\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-/* Initialization and Configuration functions *********************************/\r
-void OPAMP_DeInit(void);\r
-void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);\r
-void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);\r
-void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);\r
-void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);\r
-\r
-/* Calibration functions ******************************************************/\r
-void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);\r
-void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);\r
-void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);\r
-FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_OPAMP_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_sdio.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the SDIO firmware\r
- * library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_SDIO_H\r
-#define __STM32L1xx_SDIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SDIO\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref SDIO_Clock_Edge */\r
-\r
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
- enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Clock_Bypass */\r
-\r
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
- disabled when the bus is idle.\r
- This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
-\r
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
- This parameter can be a value of @ref SDIO_Bus_Wide */\r
-\r
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
-\r
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
- This parameter can be a value between 0x00 and 0xFF. */\r
-\r
-} SDIO_InitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
- to a card as part of a command message. If a command\r
- contains an argument, it must be loaded into this register\r
- before writing the command to the command register */\r
-\r
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
-\r
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
- This parameter can be a value of @ref SDIO_Response_Type */\r
-\r
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
-\r
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_CPSM_State */\r
-} SDIO_CmdInitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
-\r
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
- \r
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
- This parameter can be a value of @ref SDIO_Data_Block_Size */\r
- \r
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
- is a read or write.\r
- This parameter can be a value of @ref SDIO_Transfer_Direction */\r
- \r
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
- This parameter can be a value of @ref SDIO_Transfer_Type */\r
- \r
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_DPSM_State */\r
-} SDIO_DataInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup SDIO_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Edge \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
- ((EDGE) == SDIO_ClockEdge_Falling))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Bypass \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
- ((BYPASS) == SDIO_ClockBypass_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Clock_Power_Save \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
- ((SAVE) == SDIO_ClockPowerSave_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Bus_Wide \r
- * @{\r
- */\r
-\r
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
- ((WIDE) == SDIO_BusWide_8b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Hardware_Flow_Control \r
- * @{\r
- */\r
-\r
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Power_State \r
- * @{\r
- */\r
-\r
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup SDIO_Interrupt_soucres \r
- * @{\r
- */\r
-\r
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Command_Index\r
- * @{\r
- */\r
-\r
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Response_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_Response_No ((uint32_t)0x00000000)\r
-#define SDIO_Response_Short ((uint32_t)0x00000040)\r
-#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
- ((RESPONSE) == SDIO_Response_Short) || \\r
- ((RESPONSE) == SDIO_Response_Long))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Wait_Interrupt_State \r
- * @{\r
- */\r
-\r
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
- ((WAIT) == SDIO_Wait_Pend))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_CPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Response_Registers \r
- * @{\r
- */\r
-\r
-#define SDIO_RESP1 ((uint32_t)0x00000000)\r
-#define SDIO_RESP2 ((uint32_t)0x00000004)\r
-#define SDIO_RESP3 ((uint32_t)0x00000008)\r
-#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Length \r
- * @{\r
- */\r
-\r
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Block_Size \r
- * @{\r
- */\r
-\r
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16b) || \\r
- ((SIZE) == SDIO_DataBlockSize_32b) || \\r
- ((SIZE) == SDIO_DataBlockSize_64b) || \\r
- ((SIZE) == SDIO_DataBlockSize_128b) || \\r
- ((SIZE) == SDIO_DataBlockSize_256b) || \\r
- ((SIZE) == SDIO_DataBlockSize_512b) || \\r
- ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16384b)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Direction \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
- ((DIR) == SDIO_TransferDir_ToSDIO))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
- ((MODE) == SDIO_TransferMode_Block))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_DPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Flags \r
- * @{\r
- */\r
-\r
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
- ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
- ((FLAG) == SDIO_FLAG_CMDREND) || \\r
- ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
- ((FLAG) == SDIO_FLAG_DATAEND) || \\r
- ((FLAG) == SDIO_FLAG_STBITERR) || \\r
- ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
- ((FLAG) == SDIO_FLAG_CMDACT) || \\r
- ((FLAG) == SDIO_FLAG_TXACT) || \\r
- ((FLAG) == SDIO_FLAG_RXACT) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
- ((FLAG) == SDIO_FLAG_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
-\r
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
- ((IT) == SDIO_IT_DCRCFAIL) || \\r
- ((IT) == SDIO_IT_CTIMEOUT) || \\r
- ((IT) == SDIO_IT_DTIMEOUT) || \\r
- ((IT) == SDIO_IT_TXUNDERR) || \\r
- ((IT) == SDIO_IT_RXOVERR) || \\r
- ((IT) == SDIO_IT_CMDREND) || \\r
- ((IT) == SDIO_IT_CMDSENT) || \\r
- ((IT) == SDIO_IT_DATAEND) || \\r
- ((IT) == SDIO_IT_STBITERR) || \\r
- ((IT) == SDIO_IT_DBCKEND) || \\r
- ((IT) == SDIO_IT_CMDACT) || \\r
- ((IT) == SDIO_IT_TXACT) || \\r
- ((IT) == SDIO_IT_RXACT) || \\r
- ((IT) == SDIO_IT_TXFIFOHE) || \\r
- ((IT) == SDIO_IT_RXFIFOHF) || \\r
- ((IT) == SDIO_IT_TXFIFOF) || \\r
- ((IT) == SDIO_IT_RXFIFOF) || \\r
- ((IT) == SDIO_IT_TXFIFOE) || \\r
- ((IT) == SDIO_IT_RXFIFOE) || \\r
- ((IT) == SDIO_IT_TXDAVL) || \\r
- ((IT) == SDIO_IT_RXDAVL) || \\r
- ((IT) == SDIO_IT_SDIOIT) || \\r
- ((IT) == SDIO_IT_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Read_Wait_Mode \r
- * @{\r
- */\r
-\r
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
- ((MODE) == SDIO_ReadWaitMode_DATA2))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-/* Function used to set the SDIO configuration to the default reset state ****/\r
-void SDIO_DeInit(void);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_ClockCmd(FunctionalState NewState);\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
-uint32_t SDIO_GetPowerState(void);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void SDIO_DMACmd(FunctionalState NewState);\r
-\r
-/* Command path state machine (CPSM) management functions *********************/\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
-uint8_t SDIO_GetCommandResponse(void);\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
-\r
-/* Data path state machine (DPSM) management functions ************************/\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-uint32_t SDIO_GetDataCounter(void);\r
-uint32_t SDIO_ReadData(void);\r
-void SDIO_WriteData(uint32_t Data);\r
-uint32_t SDIO_GetFIFOCount(void);\r
-\r
-/* SDIO IO Cards mode management functions ************************************/\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
-void SDIO_SetSDIOOperation(FunctionalState NewState);\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
-\r
-/* CE-ATA mode management functions *******************************************/\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
-void SDIO_CEATAITCmd(FunctionalState NewState);\r
-void SDIO_SendCEATACmd(FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_SDIO_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_spi.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the SPI \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_SPI_H\r
-#define __STM32L1xx_SPI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SPI\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** \r
- * @brief SPI Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
- This parameter can be a value of @ref SPI_data_direction */\r
-\r
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
- This parameter can be a value of @ref SPI_mode */\r
-\r
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
- This parameter can be a value of @ref SPI_data_size */\r
-\r
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
- This parameter can be a value of @ref SPI_Clock_Polarity */\r
-\r
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
- This parameter can be a value of @ref SPI_Clock_Phase */\r
-\r
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
- hardware (NSS pin) or by software using the SSI bit.\r
- This parameter can be a value of @ref SPI_Slave_Select_management */\r
- \r
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
- used to configure the transmit and receive SCK clock.\r
- This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
- @note The communication clock is derived from the master\r
- clock. The slave clock does not need to be set. */\r
-\r
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
-\r
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
-}SPI_InitTypeDef;\r
-\r
-/** \r
- * @brief I2S Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
- This parameter can be a value of @ref SPI_I2S_Mode */\r
-\r
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
- This parameter can be a value of @ref SPI_I2S_Standard */\r
-\r
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
- This parameter can be a value of @ref SPI_I2S_Data_Format */\r
-\r
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
- This parameter can be a value of @ref SPI_I2S_MCLK_Output */\r
-\r
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
- This parameter can be a value of @ref SPI_I2S_Audio_Frequency */\r
-\r
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
- This parameter can be a value of @ref SPI_I2S_Clock_Polarity */\r
-}I2S_InitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup SPI_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
- ((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-\r
-/** @defgroup SPI_data_direction \r
- * @{\r
- */\r
- \r
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
- ((MODE) == SPI_Direction_1Line_Rx) || \\r
- ((MODE) == SPI_Direction_1Line_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_mode \r
- * @{\r
- */\r
-\r
-#define SPI_Mode_Master ((uint16_t)0x0104)\r
-#define SPI_Mode_Slave ((uint16_t)0x0000)\r
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
- ((MODE) == SPI_Mode_Slave))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_data_size \r
- * @{\r
- */\r
-\r
-#define SPI_DataSize_16b ((uint16_t)0x0800)\r
-#define SPI_DataSize_8b ((uint16_t)0x0000)\r
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
- ((DATASIZE) == SPI_DataSize_8b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define SPI_CPOL_Low ((uint16_t)0x0000)\r
-#define SPI_CPOL_High ((uint16_t)0x0002)\r
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
- ((CPOL) == SPI_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Clock_Phase \r
- * @{\r
- */\r
-\r
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
- ((CPHA) == SPI_CPHA_2Edge))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Slave_Select_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSS_Soft ((uint16_t)0x0200)\r
-#define SPI_NSS_Hard ((uint16_t)0x0000)\r
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
- ((NSS) == SPI_NSS_Hard))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_BaudRate_Prescaler \r
- * @{\r
- */\r
-\r
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_MSB_LSB_transmission \r
- * @{\r
- */\r
-\r
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
- ((BIT) == SPI_FirstBit_LSB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_Mode \r
- * @{\r
- */\r
-\r
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
- ((MODE) == I2S_Mode_SlaveRx) || \\r
- ((MODE) == I2S_Mode_MasterTx)|| \\r
- ((MODE) == I2S_Mode_MasterRx))\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-/** @defgroup SPI_I2S_Standard \r
- * @{\r
- */\r
-\r
-#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
-#define I2S_Standard_MSB ((uint16_t)0x0010)\r
-#define I2S_Standard_LSB ((uint16_t)0x0020)\r
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
- ((STANDARD) == I2S_Standard_MSB) || \\r
- ((STANDARD) == I2S_Standard_LSB) || \\r
- ((STANDARD) == I2S_Standard_PCMShort) || \\r
- ((STANDARD) == I2S_Standard_PCMLong))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup SPI_I2S_Data_Format \r
- * @{\r
- */\r
-\r
-#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
-#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
-#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
- ((FORMAT) == I2S_DataFormat_16bextended) || \\r
- ((FORMAT) == I2S_DataFormat_24b) || \\r
- ((FORMAT) == I2S_DataFormat_32b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_MCLK_Output \r
- * @{\r
- */\r
-\r
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
- ((OUTPUT) == I2S_MCLKOutput_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_Audio_Frequency \r
- * @{\r
- */\r
-\r
-#define I2S_AudioFreq_192k ((uint32_t)192000)\r
-#define I2S_AudioFreq_96k ((uint32_t)96000)\r
-#define I2S_AudioFreq_48k ((uint32_t)48000)\r
-#define I2S_AudioFreq_44k ((uint32_t)44100)\r
-#define I2S_AudioFreq_32k ((uint32_t)32000)\r
-#define I2S_AudioFreq_22k ((uint32_t)22050)\r
-#define I2S_AudioFreq_16k ((uint32_t)16000)\r
-#define I2S_AudioFreq_11k ((uint32_t)11025)\r
-#define I2S_AudioFreq_8k ((uint32_t)8000)\r
-#define I2S_AudioFreq_Default ((uint32_t)2)\r
-\r
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
- ((FREQ) <= I2S_AudioFreq_192k)) || \\r
- ((FREQ) == I2S_AudioFreq_Default))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup SPI_I2S_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define I2S_CPOL_Low ((uint16_t)0x0000)\r
-#define I2S_CPOL_High ((uint16_t)0x0008)\r
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
- ((CPOL) == I2S_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_DMA_transfer_requests \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_NSS_internal_software_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_Transmit_Receive \r
- * @{\r
- */\r
-\r
-#define SPI_CRC_Tx ((uint8_t)0x00)\r
-#define SPI_CRC_Rx ((uint8_t)0x01)\r
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_direction_transmit_receive \r
- * @{\r
- */\r
-\r
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
-#define SPI_Direction_Tx ((uint16_t)0x4000)\r
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
- ((DIRECTION) == SPI_Direction_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
-#define I2S_IT_UDR ((uint8_t)0x53)\r
-#define SPI_I2S_IT_FRE ((uint8_t)0x58)\r
-\r
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_I2S_IT_RXNE) || \\r
- ((IT) == SPI_I2S_IT_ERR))\r
-\r
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
-#define SPI_IT_MODF ((uint8_t)0x55)\r
-#define SPI_IT_CRCERR ((uint8_t)0x54)\r
-\r
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
-\r
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\\r
- ((IT) == SPI_I2S_IT_FRE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_flags_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
-#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
-#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
-#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)\r
-\r
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \\r
- ((FLAG) == SPI_I2S_FLAG_FRE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_polynomial \r
- * @{\r
- */\r
-\r
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_Legacy \r
- * @{\r
- */\r
-\r
-#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
-#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
-#define SPI_IT_TXE SPI_I2S_IT_TXE\r
-#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
-#define SPI_IT_ERR SPI_I2S_IT_ERR\r
-#define SPI_IT_OVR SPI_I2S_IT_OVR\r
-#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
-#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
-#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
-#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
-#define SPI_DeInit SPI_I2S_DeInit\r
-#define SPI_ITConfig SPI_I2S_ITConfig\r
-#define SPI_DMACmd SPI_I2S_DMACmd\r
-#define SPI_SendData SPI_I2S_SendData\r
-#define SPI_ReceiveData SPI_I2S_ReceiveData\r
-#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
-#define SPI_ClearFlag SPI_I2S_ClearFlag\r
-#define SPI_GetITStatus SPI_I2S_GetITStatus\r
-#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-/* Function used to set the SPI configuration to the default reset state *****/ \r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
-\r
-/* Hardware CRC Calculation functions *****************************************/\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32L1xx_SPI_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_usart.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the USART \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_USART_H\r
-#define __STM32L1xx_USART_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup USART\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-\r
-/** \r
- * @brief USART Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
- The baud rate is computed using the following formula:\r
- - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))\r
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 \r
- Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */\r
-\r
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
- This parameter can be a value of @ref USART_Word_Length */\r
-\r
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
- This parameter can be a value of @ref USART_Stop_Bits */\r
-\r
- uint16_t USART_Parity; /*!< Specifies the parity mode.\r
- This parameter can be a value of @ref USART_Parity\r
- @note When parity is enabled, the computed parity is inserted\r
- at the MSB position of the transmitted data (9th bit when\r
- the word length is set to 9 data bits; 8th bit when the\r
- word length is set to 8 data bits). */\r
- \r
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
- This parameter can be a value of @ref USART_Mode */\r
-\r
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
- or disabled.\r
- This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
-} USART_InitTypeDef;\r
-\r
-/** \r
- * @brief USART Clock Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
-\r
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
- This parameter can be a value of @ref USART_Clock */\r
-\r
- uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.\r
- This parameter can be a value of @ref USART_Clock_Polarity */\r
-\r
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref USART_Clock_Phase */\r
-\r
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
- This parameter can be a value of @ref USART_Last_Bit */\r
-} USART_ClockInitTypeDef;\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup USART_Exported_Constants\r
- * @{\r
- */ \r
- \r
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3) || \\r
- ((PERIPH) == UART4) || \\r
- ((PERIPH) == UART5))\r
-\r
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3))\r
-\r
-/** @defgroup USART_Word_Length \r
- * @{\r
- */ \r
- \r
-#define USART_WordLength_8b ((uint16_t)0x0000)\r
-#define USART_WordLength_9b ((uint16_t)0x1000)\r
- \r
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
- ((LENGTH) == USART_WordLength_9b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Stop_Bits \r
- * @{\r
- */ \r
- \r
-#define USART_StopBits_1 ((uint16_t)0x0000)\r
-#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
-#define USART_StopBits_2 ((uint16_t)0x2000)\r
-#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
- ((STOPBITS) == USART_StopBits_0_5) || \\r
- ((STOPBITS) == USART_StopBits_2) || \\r
- ((STOPBITS) == USART_StopBits_1_5))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Parity \r
- * @{\r
- */ \r
- \r
-#define USART_Parity_No ((uint16_t)0x0000)\r
-#define USART_Parity_Even ((uint16_t)0x0400)\r
-#define USART_Parity_Odd ((uint16_t)0x0600) \r
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
- ((PARITY) == USART_Parity_Even) || \\r
- ((PARITY) == USART_Parity_Odd))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Mode \r
- * @{\r
- */ \r
- \r
-#define USART_Mode_Rx ((uint16_t)0x0004)\r
-#define USART_Mode_Tx ((uint16_t)0x0008)\r
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Hardware_Flow_Control \r
- * @{\r
- */ \r
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
- (((CONTROL) == USART_HardwareFlowControl_None) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock \r
- * @{\r
- */ \r
-#define USART_Clock_Disable ((uint16_t)0x0000)\r
-#define USART_Clock_Enable ((uint16_t)0x0800)\r
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
- ((CLOCK) == USART_Clock_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Polarity \r
- * @{\r
- */\r
- \r
-#define USART_CPOL_Low ((uint16_t)0x0000)\r
-#define USART_CPOL_High ((uint16_t)0x0400)\r
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Phase\r
- * @{\r
- */\r
-\r
-#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
-#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Last_Bit\r
- * @{\r
- */\r
-\r
-#define USART_LastBit_Disable ((uint16_t)0x0000)\r
-#define USART_LastBit_Enable ((uint16_t)0x0100)\r
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
- ((LASTBIT) == USART_LastBit_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Interrupt_definition \r
- * @{\r
- */\r
- \r
-#define USART_IT_PE ((uint16_t)0x0028)\r
-#define USART_IT_TXE ((uint16_t)0x0727)\r
-#define USART_IT_TC ((uint16_t)0x0626)\r
-#define USART_IT_RXNE ((uint16_t)0x0525)\r
-#define USART_IT_IDLE ((uint16_t)0x0424)\r
-#define USART_IT_LBD ((uint16_t)0x0846)\r
-#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */\r
-#define USART_IT_CTS ((uint16_t)0x096A)\r
-#define USART_IT_ERR ((uint16_t)0x0060)\r
-#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */\r
-#define USART_IT_NE ((uint16_t)0x0260)\r
-#define USART_IT_FE ((uint16_t)0x0160)\r
-\r
-/** @defgroup USART_Legacy \r
- * @{\r
- */\r
-#define USART_IT_ORE USART_IT_ORE_ER \r
-/**\r
- * @}\r
- */\r
-\r
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \\r
- ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \\r
- ((IT) == USART_IT_FE))\r
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_DMA_Requests \r
- * @{\r
- */\r
-\r
-#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
-#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_WakeUp_methods\r
- * @{\r
- */\r
-\r
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
- ((WAKEUP) == USART_WakeUp_AddressMark))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_LIN_Break_Detection_Length \r
- * @{\r
- */\r
- \r
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
- ((LENGTH) == USART_LINBreakDetectLength_11b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_IrDA_Low_Power \r
- * @{\r
- */\r
-\r
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
- ((MODE) == USART_IrDAMode_Normal))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Flags \r
- * @{\r
- */\r
-\r
-#define USART_FLAG_CTS ((uint16_t)0x0200)\r
-#define USART_FLAG_LBD ((uint16_t)0x0100)\r
-#define USART_FLAG_TXE ((uint16_t)0x0080)\r
-#define USART_FLAG_TC ((uint16_t)0x0040)\r
-#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
-#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
-#define USART_FLAG_ORE ((uint16_t)0x0008)\r
-#define USART_FLAG_NE ((uint16_t)0x0004)\r
-#define USART_FLAG_FE ((uint16_t)0x0002)\r
-#define USART_FLAG_PE ((uint16_t)0x0001)\r
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
- \r
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */ \r
-\r
-/* Function used to set the USART configuration to the default reset state ***/ \r
-void USART_DeInit(USART_TypeDef* USARTx);\r
-\r
-/* Initialization and Configuration functions *********************************/\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* Data transfers functions ***************************************************/ \r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
-\r
-/* Multi-Processor Communication functions ************************************/\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* LIN mode functions *********************************************************/\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SendBreak(USART_TypeDef* USARTx);\r
-\r
-/* Half-duplex mode function **************************************************/\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* Smartcard mode functions ***************************************************/\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
-\r
-/* IrDA mode functions ********************************************************/\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-\r
-/* DMA transfers management functions *****************************************/\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_USART_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_wwdg.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file contains all the functions prototypes for the WWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L1xx_WWDG_H\r
-#define __STM32L1xx_WWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup WWDG\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup WWDG_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup WWDG_Prescaler \r
- * @{\r
- */ \r
- \r
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
- ((PRESCALER) == WWDG_Prescaler_2) || \\r
- ((PRESCALER) == WWDG_Prescaler_4) || \\r
- ((PRESCALER) == WWDG_Prescaler_8))\r
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-/* Function used to set the WWDG configuration to the default reset state ****/ \r
-void WWDG_DeInit(void);\r
-\r
-/* Prescaler, Refresh window and Counter configuration functions **************/\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
-void WWDG_SetWindowValue(uint8_t WindowValue);\r
-void WWDG_EnableIT(void);\r
-void WWDG_SetCounter(uint8_t Counter);\r
-\r
-/* WWDG activation functions **************************************************/\r
-void WWDG_Enable(uint8_t Counter);\r
-\r
-/* Interrupts and flags management functions **********************************/\r
-FlagStatus WWDG_GetFlagStatus(void);\r
-void WWDG_ClearFlag(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L1xx_WWDG_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_adc.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
- * + Initialization and Configuration\r
- * + Power saving\r
- * + Analog Watchdog configuration\r
- * + Temperature Sensor & Vrefint (Voltage Reference internal) management \r
- * + Regular Channels Configuration\r
- * + Regular Channels DMA Configuration\r
- * + Injected channels Configuration\r
- * + Interrupts and flags management\r
- * \r
- * @verbatim\r
-================================================================================\r
- ##### How to use this driver #####\r
-================================================================================\r
- [..]\r
- (#) Configure the ADC Prescaler, conversion resolution and data alignment \r
- using the ADC_Init() function.\r
- (#) Activate the ADC peripheral using ADC_Cmd() function.\r
- \r
- *** Regular channels group configuration ***\r
- ============================================\r
- [..]\r
- (+) To configure the ADC regular channels group features, use \r
- ADC_Init() and ADC_RegularChannelConfig() functions.\r
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()\r
- function.\r
- (+) To configurate and activate the Discontinuous mode, use the \r
- ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.\r
- (+) To read the ADC converted values, use the ADC_GetConversionValue()\r
- function.\r
- \r
- *** DMA for Regular channels group features configuration ***\r
- =============================================================\r
- [..]\r
- (+) To enable the DMA mode for regular channels group, use the \r
- ADC_DMACmd() function.\r
- (+) To enable the generation of DMA requests continuously at the end\r
- of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
- function.\r
- \r
- *** Injected channels group configuration ***\r
- =============================================\r
- [..]\r
- (+) To configure the ADC Injected channels group features, use \r
- ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
- functions.\r
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()\r
- function.\r
- (+) To activate the Injected Discontinuous mode, use the \r
- ADC_InjectedDiscModeCmd() function.\r
- (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
- function.\r
- (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
- function.\r
-\r
- @endverbatim\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
- \r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_adc.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC \r
- * @brief ADC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* ADC DISCNUM mask */\r
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
- \r
-/* ADC AWDCH mask */\r
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
- \r
-/* ADC Analog watchdog enable mode mask */\r
-#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
- \r
-/* CR1 register Mask */\r
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
- \r
-/* ADC DELAY mask */ \r
-#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
- \r
-/* ADC JEXTEN mask */\r
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
- \r
-/* ADC JEXTSEL mask */\r
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
- \r
-/* CR2 register Mask */\r
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
-\r
-/* ADC SQx mask */\r
-#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
-\r
-/* ADC L Mask */\r
-#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
-\r
-/* ADC JSQx mask */\r
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
- \r
-/* ADC JL mask */\r
-#define JSQR_JL_SET ((uint32_t)0x00300000) \r
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
-\r
-/* ADC SMPx mask */\r
-#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
-#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
-#define SMPR0_SMP_SET ((uint32_t)0x00000007)\r
-\r
-/* ADC JDRx registers offset */\r
-#define JDR_OFFSET ((uint8_t)0x30) \r
- \r
-/* ADC CCR register Mask */\r
-#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup ADC_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions.\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to:\r
- (+) Initialize and configure the ADC Prescaler.\r
- (+) ADC Conversion Resolution (12bit..6bit).\r
- (+) Scan Conversion Mode (multichannel or one channel) for regular group.\r
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for \r
- regular group.\r
- (+) External trigger Edge and source of regular group.\r
- (+) Converted data alignment (left or right).\r
- (+) The number of ADC conversions that will be done using the sequencer \r
- for regular channel group.\r
- (+) Enable or disable the ADC peripheral.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void ADC_DeInit(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- if(ADCx == ADC1)\r
- {\r
- /* Enable ADC1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
- /* Release ADC1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCx peripheral according to the specified parameters\r
- * in the ADC_InitStruct.\r
- * @note This function is used to configure the global features of the ADC ( \r
- * Resolution and Data Alignment), however, the rest of the configuration\r
- * parameters are specific to the regular channels group (scan mode \r
- * activation, continuous mode activation, External trigger source and \r
- * edge, number of conversion in the regular channels group sequencer).\r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
- * the configuration information for the specified ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint8_t tmpreg2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
- \r
- /*---------------------------- ADCx CR1 Configuration -----------------*/\r
- /* Get the ADCx CR1 value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear RES and SCAN bits */ \r
- tmpreg1 &= CR1_CLEAR_MASK;\r
- /* Configure ADCx: scan conversion mode and resolution */\r
- /* Set SCAN bit according to ADC_ScanConvMode value */\r
- /* Set RES bit according to ADC_Resolution value */ \r
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
- /* Write to ADCx CR1 */\r
- ADCx->CR1 = tmpreg1;\r
- \r
- /*---------------------------- ADCx CR2 Configuration -----------------*/\r
- /* Get the ADCx CR2 value */\r
- tmpreg1 = ADCx->CR2;\r
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
- tmpreg1 &= CR2_CLEAR_MASK;\r
- /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
- /* Set ALIGN bit according to ADC_DataAlign value */\r
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
- /* Set CONT bit according to ADC_ContinuousConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
- ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
- /* Write to ADCx CR2 */\r
- ADCx->CR2 = tmpreg1;\r
- \r
- /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
- /* Get the ADCx SQR1 value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Clear L bits */\r
- tmpreg1 &= SQR1_L_RESET;\r
- /* Configure ADCx: regular channel sequence length */\r
- /* Set L bits according to ADC_NbrOfConversion value */ \r
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
- /* Write to ADCx SQR1 */\r
- ADCx->SQR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_InitStruct member with its default value.\r
- * @note This function is used to initialize the global features of the ADC ( \r
- * Resolution and Data Alignment), however, the rest of the configuration\r
- * parameters are specific to the regular channels group (scan mode \r
- * activation, continuous mode activation, External trigger source and \r
- * edge, number of conversion in the regular channels group sequencer).\r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Resolution member */\r
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
-\r
- /* Initialize the ADC_ScanConvMode member */\r
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
-\r
- /* Initialize the ADC_ContinuousConvMode member */\r
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
-\r
- /* Initialize the ADC_ExternalTrigConvEdge member */\r
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
-\r
- /* Initialize the ADC_ExternalTrigConv member */\r
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
-\r
- /* Initialize the ADC_DataAlign member */\r
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
-\r
- /* Initialize the ADC_NbrOfConversion member */\r
- ADC_InitStruct->ADC_NbrOfConversion = 1;\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCs peripherals according to the specified parameters\r
- * in the ADC_CommonInitStruct.\r
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
- * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
-\r
- /*---------------------------- ADC CCR Configuration -----------------*/\r
- /* Get the ADC CCR value */\r
- tmpreg = ADC->CCR;\r
-\r
- /* Clear ADCPRE bit */ \r
- tmpreg &= CR_CLEAR_MASK;\r
- \r
- /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
- tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
- \r
- /* Write to ADC CCR */\r
- ADC->CCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_CommonInitStruct member with its default value.\r
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Prescaler member */\r
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC peripheral.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the ADCx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ADON bit to wake up the ADC from power down mode */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC peripheral */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified ADC Channels Bank.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_Bank: ADC Channels Bank.\r
- * @arg ADC_Bank_A: ADC Channels Bank A.\r
- * @arg ADC_Bank_B: ADC Channels Bank B.\r
- * @retval None\r
- */\r
-void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_BANK(ADC_Bank));\r
-\r
- if (ADC_Bank != ADC_Bank_A)\r
- {\r
- /* Set the ADC_CFG bit to select the ADC Bank B channels */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_CFG;\r
- }\r
- else\r
- {\r
- /* Reset the ADC_CFG bit to select the ADC Bank A channels */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CFG);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group2 Power saving functions\r
- * @brief Power saving functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Power saving functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to reduce power consumption.\r
- [..] The two function must be combined to get the maximal benefits:\r
- When the ADC frequency is higher than the CPU one, it is recommended to:\r
- (#) Insert a freeze delay :\r
- ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze).\r
- (#) Enable the power down in Idle and Delay phases :\r
- ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
- * @note ADC power-on and power-off can be managed by hardware to cut the \r
- * consumption when the ADC is not converting.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_PowerDown: The ADC power down configuration.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase.\r
- * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase.\r
- * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.\r
- * @note The ADC can be powered down:\r
- * @note During the hardware delay insertion (using the ADC_PowerDown_Delay\r
- * parameter).\r
- * => The ADC is powered up again at the end of the delay.\r
- * @note During the ADC is waiting for a trigger event ( using the \r
- * ADC_PowerDown_Idle parameter).\r
- * => The ADC is powered up at the next trigger event.\r
- * @note During the hardware delay insertion or the ADC is waiting for a \r
- * trigger event (using the ADC_PowerDown_Idle_Delay parameter).\r
- * => The ADC is powered up only at the end of the delay and at the\r
- * next trigger event.\r
- * @param NewState: new state of the ADCx power down.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the ADC power-down during Delay and/or Idle phase */\r
- ADCx->CR1 |= ADC_PowerDown;\r
- }\r
- else\r
- {\r
- /* Disable The ADC power-down during Delay and/or Idle phase */\r
- ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Defines the length of the delay which is applied after a conversion \r
- * or a sequence of conversion.\r
- * @note When the CPU clock is not fast enough to manage the data rate, a \r
- * Hardware delay can be introduced between ADC conversions to reduce \r
- * this data rate.\r
- * @note The Hardware delay is inserted after :\r
- * - each regular conversion.\r
- * - after each sequence of injected conversions.\r
- * @note No Hardware delay is inserted between conversions of different groups.\r
- * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
- * selected and a new conversion can start only if all the previous data \r
- * of the same group have been treated:\r
- * - for a regular conversion: once the ADC conversion data register has \r
- * been read (using ADC_GetConversionValue() function) or if the EOC \r
- * Flag has been cleared (using ADC_ClearFlag() function).\r
- * - for an injected conversion: when the JEOC bit has been cleared \r
- * (using ADC_ClearFlag() function).\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_DelayLength: The length of delay which is applied after a \r
- * conversion or a sequence of conversion. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_DelayLength_None: No delay.\r
- * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
- * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.\r
- * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
- * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
- * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
- * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
- * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
- * @retval None\r
- */\r
-void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
-\r
- /* Get the old register value */ \r
- tmpreg = ADCx->CR2;\r
- /* Clear the old delay length */\r
- tmpreg &= CR2_DELS_RESET;\r
- /* Set the delay length */\r
- tmpreg |= ADC_DelayLength;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
- * @brief Analog Watchdog configuration functions. \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Analog Watchdog configuration functions #####\r
- =============================================================================== \r
- [..] This section provides functions allowing to configure the Analog Watchdog\r
- (AWD) feature in the ADC.\r
- [..] A typical configuration Analog Watchdog is done following these steps :\r
- (#) the ADC guarded channel(s) is (are) selected using the \r
- ADC_AnalogWatchdogSingleChannelConfig() function.\r
- (#) The Analog watchdog lower and higher threshold are configured using \r
- the ADC_AnalogWatchdogThresholdsConfig() function.\r
- (#) The Analog watchdog is enabled and configured to enable the check, \r
- on one or more channels, using the ADC_AnalogWatchdogCmd() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the analog watchdog on single/all regular\r
- * or injected channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
- * regular channel.\r
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
- * injected channel.\r
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
- * single regular or injected channel.\r
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
- * channel.\r
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
- * channel.\r
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
- * regular and injected channels.\r
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.\r
- * @retval None \r
- */\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
- tmpreg &= CR1_AWDMODE_RESET;\r
- /* Set the analog watchdog enable mode */\r
- tmpreg |= ADC_AnalogWatchdog;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the high and low thresholds of the analog watchdog.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param HighThreshold: the ADC analog watchdog High threshold value.\r
- * This parameter must be a 12bit value.\r
- * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
- uint16_t LowThreshold)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
- assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
-\r
- /* Set the ADCx high threshold */\r
- ADCx->HTR = HighThreshold;\r
- /* Set the ADCx low threshold */\r
- ADCx->LTR = LowThreshold;\r
-}\r
-\r
-/**\r
- * @brief Configures the analog watchdog guarded single channel.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected\r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @arg ADC_Channel_27: ADC Channel27 selected\r
- * @arg ADC_Channel_28: ADC Channel28 selected\r
- * @arg ADC_Channel_29: ADC Channel29 selected\r
- * @arg ADC_Channel_30: ADC Channel30 selected\r
- * @arg ADC_Channel_31: ADC Channel31 selected\r
- * @arg ADC_Channel_0b: ADC Channel0b selected\r
- * @arg ADC_Channel_1b: ADC Channel1b selected\r
- * @arg ADC_Channel_2b: ADC Channel2b selected\r
- * @arg ADC_Channel_3b: ADC Channel3b selected\r
- * @arg ADC_Channel_6b: ADC Channel6b selected\r
- * @arg ADC_Channel_7b: ADC Channel7b selected\r
- * @arg ADC_Channel_8b: ADC Channel8b selected\r
- * @arg ADC_Channel_9b: ADC Channel9b selected\r
- * @arg ADC_Channel_10b: ADC Channel10b selected\r
- * @arg ADC_Channel_11b: ADC Channel11b selected\r
- * @arg ADC_Channel_12b: ADC Channel12b selected\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear the Analog watchdog channel select bits */\r
- tmpreg &= CR1_AWDCH_RESET;\r
- /* Set the Analog watchdog channel */\r
- tmpreg |= ADC_Channel;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
- * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function.\r
- *\r
-@verbatim \r
- =========================================================================================\r
- ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####\r
- =========================================================================================\r
- [..] This section provides a function allowing to enable/ disable the internal \r
- connections between the ADC and the Temperature Sensor and the Vrefint \r
- source.\r
- [..] A typical configuration to get the Temperature sensor and Vrefint channels \r
- voltages is done following these steps :\r
- (#) Enable the internal connection of Temperature sensor and Vrefint sources \r
- with the ADC channels using ADC_TempSensorVrefintCmd() function.\r
- (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions.\r
- (#) Get the voltage values, using ADC_GetConversionValue() or \r
- ADC_GetInjectedConversionValue().\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the temperature sensor and Vrefint channel.\r
- * @param NewState: new state of the temperature sensor and Vref int channels.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the temperature sensor and Vrefint channel*/\r
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
- }\r
- else\r
- {\r
- /* Disable the temperature sensor and Vrefint channel*/\r
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
- * @brief Regular Channels Configuration functions.\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Regular Channels Configuration functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to manage the ADC regular channels,\r
- it is composed of 2 sub sections :\r
- (#) Configuration and management functions for regular channels: This \r
- subsection provides functions allowing to configure the ADC regular \r
- channels :\r
- (++) Configure the rank in the regular group sequencer for each channel.\r
- (++) Configure the sampling time for each channel.\r
- (++) select the conversion Trigger for regular channels.\r
- (++) select the desired EOC event behavior configuration.\r
- (++) Activate the continuous Mode (*).\r
- (++) Activate the Discontinuous Mode.\r
- -@@- Please Note that the following features for regular channels are \r
- configurated using the ADC_Init() function : \r
- (+@@) scan mode activation.\r
- (+@@) continuous mode activation (**).\r
- (+@@) External trigger source.\r
- (+@@) External trigger edge.\r
- (+@@) number of conversion in the regular channels group sequencer.\r
- -@@- (*) and (**) are performing the same configuration.\r
- (#) Get the conversion data: This subsection provides an important function \r
- in the ADC peripheral since it returns the converted data of the current \r
- regular channel. When the Conversion value is read, the EOC Flag is \r
- automatically cleared.\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures for the selected ADC regular channel its corresponding\r
- * rank in the sequencer and its sampling time.\r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected \r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @arg ADC_Channel_27: ADC Channel27 selected\r
- * @arg ADC_Channel_28: ADC Channel28 selected\r
- * @arg ADC_Channel_29: ADC Channel29 selected\r
- * @arg ADC_Channel_30: ADC Channel30 selected\r
- * @arg ADC_Channel_31: ADC Channel31 selected \r
- * @arg ADC_Channel_0b: ADC Channel0b selected\r
- * @arg ADC_Channel_1b: ADC Channel1b selected\r
- * @arg ADC_Channel_2b: ADC Channel2b selected\r
- * @arg ADC_Channel_3b: ADC Channel3b selected\r
- * @arg ADC_Channel_6b: ADC Channel6b selected\r
- * @arg ADC_Channel_7b: ADC Channel7b selected\r
- * @arg ADC_Channel_8b: ADC Channel8b selected\r
- * @arg ADC_Channel_9b: ADC Channel9b selected\r
- * @arg ADC_Channel_10b: ADC Channel10b selected\r
- * @arg ADC_Channel_11b: ADC Channel11b selected\r
- * @arg ADC_Channel_12b: ADC Channel12b selected \r
- * @param Rank: The rank in the regular group sequencer. This parameter\r
- * must be between 1 to 28.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected \r
- * channel.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles\r
- * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
- * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
- * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
- * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
- * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
- * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
- * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
- * @retval None\r
- */\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_REGULAR_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
-\r
- /* If ADC_Channel_30 or ADC_Channel_31 is selected */\r
- if (ADC_Channel > ADC_Channel_29)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR0;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR0 = tmpreg1;\r
- }\r
- /* If ADC_Channel_20 ... ADC_Channel_29 is selected */\r
- else if (ADC_Channel > ADC_Channel_19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- /* If ADC_Channel_10 ... ADC_Channel_19 is selected */\r
- else if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR3 = tmpreg1;\r
- }\r
- /* For Rank 1 to 6 */\r
- if (Rank < 7)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR5;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR5 = tmpreg1;\r
- }\r
- /* For Rank 7 to 12 */\r
- else if (Rank < 13)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR4;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR4 = tmpreg1;\r
- } \r
- /* For Rank 13 to 18 */\r
- else if (Rank < 19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR3 = tmpreg1;\r
- }\r
- \r
- /* For Rank 19 to 24 */\r
- else if (Rank < 25)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR2 = tmpreg1;\r
- } \r
- \r
- /* For Rank 25 to 28 */\r
- else\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR1 = tmpreg1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables the selected ADC software start conversion of the regular channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Enable the selected ADC conversion for regular group */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start regular conversion Status.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The new state of ADC software start conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Check the status of SWSTART bit */\r
- if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
- {\r
- /* SWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the EOC on each regular channel conversion.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC EOC flag rising\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC EOC rising on each regular channel conversion */\r
- ADCx->CR2 |= ADC_CR2_EOCS;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC EOC rising on each regular channel conversion */\r
- ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADC continuous conversion mode.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC continuous conversion mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC continuous conversion mode */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC continuous conversion mode */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the discontinuous mode for the selected ADC regular\r
- * group channel.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param Number: specifies the discontinuous mode regular channel count value.\r
- * This number must be between 1 and 8.\r
- * @retval None\r
- */\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
-\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear the old discontinuous mode channel count */\r
- tmpreg1 &= CR1_DISCNUM_RESET;\r
- /* Set the discontinuous mode channel count */\r
- tmpreg2 = Number - 1;\r
- tmpreg1 |= tmpreg2 << 13;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode on regular group\r
- * channel for the specified ADC.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode on regular \r
- * group channel.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADCx conversion result data for regular channel.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Return the selected ADC conversion value */\r
- return (uint16_t) ADCx->DR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
- * @brief Regular Channels DMA Configuration functions.\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Regular Channels DMA Configuration functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to configure the DMA for ADC regular \r
- channels.Since converted regular channel values are stored into a unique \r
- data register, it is useful to use DMA for conversion of more than one \r
- regular channel. This avoids the loss of the data already stored in the \r
- ADC Data register.\r
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
- conversion of a regular channel, a DMA request is generated.\r
- [..] Depending on the "DMA disable selection" configuration (using the \r
- ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
- transfer, two possibilities are allowed:\r
- (+) No new DMA request is issued to the DMA controller (feature DISABLED).\r
- (+) Requests can continue to be generated (feature ENABLED).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC DMA request.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request */\r
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode).\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC EOC flag rising\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request after last transfer */\r
- ADCx->CR2 |= ADC_CR2_DDS;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request after last transfer */\r
- ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group7 Injected channels Configuration functions\r
- * @brief Injected channels Configuration functions.\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Injected channels Configuration functions #####\r
- ===============================================================================\r
- [..] This section provide functions allowing to configure the ADC Injected channels,\r
- it is composed of 2 sub sections : \r
- (#) Configuration functions for Injected channels: This subsection provides \r
- functions allowing to configure the ADC injected channels :\r
- (++) Configure the rank in the injected group sequencer for each channel.\r
- (++) Configure the sampling time for each channel.\r
- (++) Activate the Auto injected Mode.\r
- (++) Activate the Discontinuous Mode.\r
- (++) scan mode activation.\r
- (++) External/software trigger source.\r
- (++) External trigger edge.\r
- (++) injected channels sequencer.\r
- \r
- (#) Get the Specified Injected channel conversion data: This subsection \r
- provides an important function in the ADC peripheral since it returns \r
- the converted data of the specific injected channel.\r
-\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Configures for the selected ADC injected channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_Channel: the ADC channel to configure.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @arg ADC_Channel_18: ADC Channel18 selected \r
- * @arg ADC_Channel_19: ADC Channel19 selected\r
- * @arg ADC_Channel_20: ADC Channel20 selected\r
- * @arg ADC_Channel_21: ADC Channel21 selected\r
- * @arg ADC_Channel_22: ADC Channel22 selected\r
- * @arg ADC_Channel_23: ADC Channel23 selected\r
- * @arg ADC_Channel_24: ADC Channel24 selected\r
- * @arg ADC_Channel_25: ADC Channel25 selected\r
- * @arg ADC_Channel_27: ADC Channel27 selected\r
- * @arg ADC_Channel_28: ADC Channel28 selected\r
- * @arg ADC_Channel_29: ADC Channel29 selected\r
- * @arg ADC_Channel_30: ADC Channel30 selected\r
- * @arg ADC_Channel_31: ADC Channel31 selected \r
- * @arg ADC_Channel_0b: ADC Channel0b selected\r
- * @arg ADC_Channel_1b: ADC Channel1b selected\r
- * @arg ADC_Channel_2b: ADC Channel2b selected\r
- * @arg ADC_Channel_3b: ADC Channel3b selected\r
- * @arg ADC_Channel_6b: ADC Channel6b selected\r
- * @arg ADC_Channel_7b: ADC Channel7b selected\r
- * @arg ADC_Channel_8b: ADC Channel8b selected\r
- * @arg ADC_Channel_9b: ADC Channel9b selected\r
- * @arg ADC_Channel_10b: ADC Channel10b selected\r
- * @arg ADC_Channel_11b: ADC Channel11b selected\r
- * @arg ADC_Channel_12b: ADC Channel12b selected \r
- * @param Rank: The rank in the injected group sequencer. This parameter\r
- * must be between 1 to 4.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected \r
- * channel. This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles\r
- * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
- * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
- * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
- * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
- * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
- * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
- * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
- * @retval None\r
- */\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_INJECTED_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- \r
- /* If ADC_Channel_30 or ADC_Channel_31 is selected */\r
- if (ADC_Channel > ADC_Channel_29)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR0;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR0 = tmpreg1;\r
- }\r
- /* If ADC_Channel_20 ... ADC_Channel_29 is selected */\r
- else if (ADC_Channel > ADC_Channel_19)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- } \r
- /* If ADC_Channel_10 ... ADC_Channel_19 is selected */\r
- else if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
- /* Clear the old sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR3 = tmpreg1;\r
- }\r
- \r
- /* Rank configuration */\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Get JL value: Number = JL+1 */\r
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
- /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
- tmpreg2 = (uint32_t)(JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));\r
- /* Clear the old JSQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
- tmpreg2 = (uint32_t)(((uint32_t)(ADC_Channel)) << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));\r
- /* Set the JSQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Configures the sequencer length for injected channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param Length: The sequencer length.\r
- * This parameter must be a number between 1 to 4.\r
- * @retval None\r
- */\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
- \r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Clear the old injected sequence length JL bits */\r
- tmpreg1 &= JSQR_JL_RESET;\r
- /* Set the injected sequence length JL bits */\r
- tmpreg2 = Length - 1; \r
- tmpreg1 |= tmpreg2 << 20;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Set the injected channels conversion value offset.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected.\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected.\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected.\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected.\r
- * @param Offset: the offset value for the selected ADC injected channel\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
- assert_param(IS_ADC_OFFSET(Offset)); \r
- \r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel;\r
- \r
- /* Set the selected injected channel data offset */\r
- *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger for injected channels conversion.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
- * conversion. This parameter can be one of the following values:\r
- * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
- * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected\r
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected\r
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected\r
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected\r
- * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
- * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected\r
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external event selection for injected group */\r
- tmpreg &= CR2_JEXTSEL_RESET;\r
- /* Set the external event selection for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConv;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
- * edge to start injected conversion.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
- * injected conversion.\r
- * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
- * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
- * @arg ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
- * both rising and falling edge\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
-\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external trigger edge for injected group */\r
- tmpreg &= CR2_JEXTEN_RESET;\r
- /* Set the new external trigger edge for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the selected ADC software start conversion of the injected \r
- * channels.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Enable the selected ADC conversion for injected group */\r
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start injected conversion Status.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @retval The new state of ADC software start injected conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
-\r
- /* Check the status of JSWSTART bit */\r
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
- {\r
- /* JSWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* JSWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the JSWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC automatic injected group\r
- * conversion after regular one.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC auto injected\r
- * conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode for injected group\r
- * channel for the specified ADC.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the ADC injected channel conversion result.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_InjectedChannel: the converted ADC injected channel.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
-\r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel + JDR_OFFSET;\r
- \r
- /* Returns the selected injected channel conversion data value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp); \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Group8 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions.\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to configure the ADC Interrupts \r
- and get the status and clear flags and Interrupts pending bits.\r
- \r
- [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into \r
- 3 groups:\r
- *** Flags and Interrupts for ADC regular channels ***\r
- =====================================================\r
- [..]\r
- (+)Flags :\r
- (##) ADC_FLAG_OVR : Overrun detection when regular converted data are \r
- lost.\r
- (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate \r
- (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )\r
- the end of :\r
- (+++) a regular CHANNEL conversion.\r
- (+++) sequence of regular GROUP conversions.\r
-\r
-\r
- (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular \r
- CHANNEL conversion starts.\r
- (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new \r
- regular conversion can be launched.\r
- (+)Interrupts :\r
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection \r
- event.\r
- (##) ADC_IT_EOC : specifies the interrupt source for Regular channel \r
- end of conversion event.\r
- \r
- *** Flags and Interrupts for ADC Injected channels ***\r
- ======================================================\r
- (+)Flags :\r
- (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
- the end of injected GROUP conversion.\r
- (##) ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
- injected GROUP conversion starts.\r
- (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
- injected conversion can be launched.\r
- (+)Interrupts \r
- (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel \r
- end of conversion event.\r
- *** General Flags and Interrupts for the ADC ***\r
- ================================================\r
- (+)Flags :\r
- (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
- crosses the programmed thresholds values.\r
- (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready \r
- to convert.\r
- (+)Interrupts :\r
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog \r
- event.\r
- \r
- [..] The user should identify which mode will be used in his application to \r
- manage the ADC controller events: Polling mode or Interrupt mode.\r
- \r
- [..] In the Polling Mode it is advised to use the following functions:\r
- (+) ADC_GetFlagStatus() : to check if flags events occur.\r
- (+) ADC_ClearFlag() : to clear the flags events.\r
- \r
- [..] In the Interrupt Mode it is advised to use the following functions:\r
- (+) ADC_ITConfig() : to enable or disable the interrupt source.\r
- (+) ADC_GetITStatus() : to check if Interrupt occurs.\r
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit \r
- (corresponding Flag).\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Enables or disables the specified ADC interrupts.\r
- * @param ADCx: where x can be 1 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
- * @arg ADC_IT_OVR: overrun interrupt\r
- * @param NewState: new state of the specified ADC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
-{\r
- uint32_t itmask = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_IT(ADC_IT)); \r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)ADC_IT;\r
- itmask = (uint32_t)0x01 << itmask; \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC interrupts */\r
- ADCx->CR1 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC interrupts */\r
- ADCx->CR1 &= (~(uint32_t)itmask);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC flag is set or not.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @arg ADC_FLAG_OVR: Overrun flag\r
- * @arg ADC_FLAG_ADONS: ADC ON status\r
- * @arg ADC_FLAG_RCNR: Regular channel not ready\r
- * @arg ADC_FLAG_JCNR: Injected channel not ready\r
- * @retval The new state of ADC_FLAG (SET or RESET).\r
- */\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
-\r
- /* Check the status of the specified ADC flag */\r
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
- {\r
- /* ADC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx's pending flags.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @arg ADC_FLAG_OVR: overrun flag\r
- * @retval None\r
- */\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
-\r
- /* Clear the selected ADC flags */\r
- ADCx->SR = ~(uint32_t)ADC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC interrupt has occurred or not.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
- * @arg ADC_IT_OVR: Overrun interrupt\r
- * @retval The new state of ADC_IT (SET or RESET).\r
- */\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
-\r
- /* Get the ADC_IT enable bit status */\r
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
-\r
- /* Check the status of the specified ADC interrupt */\r
- if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
- { \r
- /* ADC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx's interrupt pending bits.\r
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
- * @arg ADC_IT_OVR: Overrun interrupt\r
- * @retval None\r
- */\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- uint8_t itmask = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT)); \r
-\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)(ADC_IT >> 8);\r
-\r
- /* Clear the selected ADC interrupt pending bits */\r
- ADCx->SR = ~(uint32_t)itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_aes.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the AES peripheral: \r
- * + Configuration\r
- * + Read/Write operations\r
- * + DMA transfers management \r
- * + Interrupts and flags management\r
- * \r
- * @verbatim\r
- ===============================================================================\r
- ##### AES Peripheral features #####\r
- ===============================================================================\r
-....[..]\r
- (#) The Advanced Encryption Standard hardware accelerator (AES) can be used\r
- to both encipher and decipher data using AES algorithm.\r
- (#) The AES supports 4 operation modes:\r
- (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block\r
- (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block\r
- (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block\r
- (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk\r
- (#) Moreover 3 chaining modes are supported:\r
- (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately\r
- (++) Cipher block chaining (CBC): Each block is XORed with the previous block\r
- (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the\r
- plain text to give the cipher text\r
- (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.\r
- (#) The AES peripheral supports write/read error handling with interrupt capability.\r
- (#) Automatic data flow control with support of direct memory access (DMA) using\r
- 2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data\r
- (DMA2 Channel3).\r
-\r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..]\r
- (#) AES AHB clock must be enabled to get write access to AES registers \r
- using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).\r
- (#) Initialize the key using AES_KeyInit().\r
- (#) Configure the AES operation mode using AES_Init().\r
- (#) If required, enable interrupt source using AES_ITConfig() and\r
- enable the AES interrupt vector using NVIC_Init().\r
- (#) If required, when using the DMA mode.\r
- (##) Configure the DMA using DMA_Init().\r
- (##) Enable DMA requests using AES_DMAConfig().\r
- (#) Enable the AES peripheral using AES_Cmd().\r
- @endverbatim\r
- \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_aes.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup AES \r
- * @brief AES driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup AES_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup AES_Group1 Initialization and configuration\r
- * @brief Initialization and configuration.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and configuration #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
- /**\r
- * @brief Deinitializes AES peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void AES_DeInit(void)\r
-{\r
- /* Enable AES reset state */\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);\r
- /* Release AES from reset state */\r
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the AES peripheral according to the specified parameters\r
- * in the AES_InitStruct:\r
- * - AES_Operation: specifies the operation mode (encryption, decryption...).\r
- * - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).\r
- * - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.\r
- * @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new \r
- * configuration (When AES is enabled, setting configuration is forbidden).\r
- * @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains \r
- * the configuration information for AES peripheral.\r
- * @retval None\r
- */\r
-void AES_Init(AES_InitTypeDef* AES_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));\r
- assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));\r
- assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));\r
-\r
- /* Get AES CR register value */\r
- tmpreg = AES->CR;\r
- \r
- /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */\r
- tmpreg &= (uint32_t)CR_CLEAR_MASK;\r
- \r
- tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);\r
-\r
- AES->CR = (uint32_t) tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.\r
- * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that\r
- * contains the configuration information for the specified AES Keys.\r
- * @note This function must be called while the AES is disabled.\r
- * @note In encryption, key derivation and key derivation + decryption modes,\r
- * AES_KeyInitStruct must contain the encryption key.\r
- * In decryption mode, AES_KeyInitStruct must contain the decryption key.\r
- * @retval None\r
- */\r
-void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
-{\r
- AES->KEYR0 = AES_KeyInitStruct->AES_Key0;\r
- AES->KEYR1 = AES_KeyInitStruct->AES_Key1;\r
- AES->KEYR2 = AES_KeyInitStruct->AES_Key2;\r
- AES->KEYR3 = AES_KeyInitStruct->AES_Key3;\r
-}\r
-\r
-/**\r
- * @brief Initializes the AES Initialization Vector IV according to \r
- * the specified parameters in the AES_IVInitStruct.\r
- * @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that\r
- * contains the configuration information for the specified AES IV.\r
- * @note When ECB chaining mode is selected, Initialization Vector IV has no\r
- * meaning.\r
- * When CTR chaining mode is selected, AES_IV0 contains the CTR value.\r
- * AES_IV1, AES_IV2 and AES_IV3 contains nonce value.\r
- * @retval None\r
- */\r
-void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)\r
-{\r
- AES->IVR0 = AES_IVInitStruct->AES_IV0;\r
- AES->IVR1 = AES_IVInitStruct->AES_IV1;\r
- AES->IVR2 = AES_IVInitStruct->AES_IV2;\r
- AES->IVR3 = AES_IVInitStruct->AES_IV3;\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the AES peripheral.\r
- * @param NewState: new state of the AES peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note The key must be written while AES is disabled.\r
- * @retval None\r
- */\r
-void AES_Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the AES peripheral */\r
- AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */\r
- }\r
- else\r
- {\r
- /* Disable the AES peripheral */\r
- AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Group2 Structures initialization functions\r
- * @brief Structures initialization.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Structures initialization functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Fills each AES_InitStruct member with its default value.\r
- * @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void AES_StructInit(AES_InitTypeDef* AES_InitStruct)\r
-{\r
- AES_InitStruct->AES_Operation = AES_Operation_Encryp;\r
- AES_InitStruct->AES_Chaining = AES_Chaining_ECB;\r
- AES_InitStruct->AES_DataType = AES_DataType_32b;\r
-}\r
-\r
-/**\r
- * @brief Fills each AES_KeyInitStruct member with its default value.\r
- * @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which \r
- * will be initialized.\r
- * @retval None\r
- */\r
-void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
-{\r
- AES_KeyInitStruct->AES_Key0 = 0x00000000;\r
- AES_KeyInitStruct->AES_Key1 = 0x00000000;\r
- AES_KeyInitStruct->AES_Key2 = 0x00000000;\r
- AES_KeyInitStruct->AES_Key3 = 0x00000000;\r
-}\r
-\r
-/**\r
- * @brief Fills each AES_IVInitStruct member with its default value.\r
- * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)\r
-{\r
- AES_IVInitStruct->AES_IV0 = 0x00000000;\r
- AES_IVInitStruct->AES_IV1 = 0x00000000;\r
- AES_IVInitStruct->AES_IV2 = 0x00000000;\r
- AES_IVInitStruct->AES_IV3 = 0x00000000;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Group3 AES Read and Write\r
- * @brief AES Read and Write.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### AES Read and Write functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Write data in DINR register to be processed by AES peripheral.\r
- * @note To process 128-bit data (4 * 32-bit), this function must be called\r
- * four times to write the 128-bit data in the 32-bit register DINR.\r
- * @note When an unexpected write to DOUTR register is detected, WRERR flag is\r
- * set.\r
- * @param Data: The data to be processed.\r
- * @retval None\r
- */\r
-void AES_WriteSubData(uint32_t Data)\r
-{\r
- /* Write Data */\r
- AES->DINR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the data in DOUTR register processed by AES peripheral.\r
- * @note This function must be called four times to get the 128-bit data.\r
- * @note When an unexpected read of DINR register is detected, RDERR flag is\r
- * set.\r
- * @retval The processed data.\r
- */\r
-uint32_t AES_ReadSubData(void)\r
-{\r
- /* Read Data */\r
- return AES->DOUTR;\r
-}\r
-\r
-/**\r
- * @brief Read the Key value.\r
- * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which\r
- * will contain the key.\r
- * @note When the key derivation mode is selected, AES must be disabled\r
- * (AES_Cmd(DISABLE)) before reading the decryption key.\r
- * Reading the key while the AES is enabled will return unpredictable\r
- * value.\r
- * @retval None\r
- */\r
-void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
-{\r
- AES_KeyInitStruct->AES_Key0 = AES->KEYR0;\r
- AES_KeyInitStruct->AES_Key1 = AES->KEYR1;\r
- AES_KeyInitStruct->AES_Key2 = AES->KEYR2;\r
- AES_KeyInitStruct->AES_Key3 = AES->KEYR3;\r
-}\r
-\r
-/**\r
- * @brief Read the Initialization Vector IV value.\r
- * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which\r
- * will contain the Initialization Vector IV.\r
- * @note When the AES is enabled Reading the Initialization Vector IV value\r
- * will return 0. The AES must be disabled using AES_Cmd(DISABLE)\r
- * to get the right value.\r
- * @note When ECB chaining mode is selected, Initialization Vector IV has no\r
- * meaning.\r
- * When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.\r
- * AES_IV1, AES_IV2 and AES_IV3 contains nonce value.\r
- * @retval None\r
- */\r
-void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)\r
-{\r
- AES_IVInitStruct->AES_IV0 = AES->IVR0;\r
- AES_IVInitStruct->AES_IV1 = AES->IVR1;\r
- AES_IVInitStruct->AES_IV2 = AES->IVR2;\r
- AES_IVInitStruct->AES_IV3 = AES->IVR3;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Group4 DMA transfers management functions\r
- * @brief DMA transfers management function.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DMA transfers management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the AES DMA interface.\r
- * @param AES_DMATransfer: Specifies the AES DMA transfer.\r
- * This parameter can be one of the following values:\r
- * @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.\r
- * @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.\r
- * @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.\r
- * @param NewState Indicates the new state of the AES DMA interface.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note The DMA has no action in key derivation mode.\r
- * @retval None\r
- */\r
-void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA transfer */\r
- AES->CR |= (uint32_t) AES_DMATransfer;\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer */\r
- AES->CR &= (uint32_t)(~AES_DMATransfer);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup AES_Group5 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions.\r
- *\r
-@verbatim\r
-\r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified AES interrupt.\r
- * @param AES_IT: Specifies the AES interrupt source to enable/disable.\r
- * This parameter can be any combinations of the following values:\r
- * @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF \r
- * flag is set an interrupt is generated.\r
- * @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error\r
- * flags (RDERR) or write error flag (WRERR) is set,\r
- * an interrupt is generated.\r
- * @param NewState: The new state of the AES interrupt source.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_AES_IT(AES_IT));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */\r
- }\r
- else\r
- {\r
- AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified AES flag is set or not.\r
- * @param AES_FLAG specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when\r
- * he computation phase is completed.\r
- * @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read\r
- * operation of DOUTR register is detected.\r
- * @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write\r
- * operation in DINR is detected.\r
- * @retval FlagStatus (SET or RESET)\r
- */\r
-FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check parameters */\r
- assert_param(IS_AES_FLAG(AES_FLAG));\r
-\r
- if ((AES->SR & AES_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the AES_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the AES flags.\r
- * @param AES_FLAG: specifies the flag to clear.\r
- * This parameter can be:\r
- * @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC\r
- * bit in CR register.\r
- * @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in \r
- * CR register.\r
- * @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in\r
- * CR register.\r
- * @retval None\r
- */\r
-void AES_ClearFlag(uint32_t AES_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_AES_FLAG(AES_FLAG));\r
-\r
- /* Check if AES_FLAG is AES_FLAG_CCF */\r
- if (AES_FLAG == AES_FLAG_CCF)\r
- {\r
- /* Clear CCF flag by setting CCFC bit */\r
- AES->CR |= (uint32_t) AES_CR_CCFC;\r
- }\r
- else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */\r
- {\r
- /* Clear RDERR and WRERR flags by setting ERRC bit */\r
- AES->CR |= (uint32_t) AES_CR_ERRC;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified AES interrupt has occurred or not.\r
- * @param AES_IT: Specifies the AES interrupt pending bit to check.\r
- * This parameter can be:\r
- * @arg AES_IT_CC: Computation Complete Interrupt.\r
- * @arg AES_IT_ERR: Error Interrupt.\r
- * @retval ITStatus The new state of AES_IT (SET or RESET).\r
- */\r
-ITStatus AES_GetITStatus(uint32_t AES_IT)\r
-{\r
- ITStatus itstatus = RESET;\r
- uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;\r
-\r
- /* Check parameters */\r
- assert_param(IS_AES_GET_IT(AES_IT));\r
-\r
- cciebitstatus = AES->CR & AES_CR_CCIE;\r
- ccfbitstatus = AES->SR & AES_SR_CCF;\r
-\r
- /* Check if AES_IT is AES_IT_CC */\r
- if (AES_IT == AES_IT_CC)\r
- {\r
- /* Check the status of the specified AES interrupt */\r
- if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))\r
- {\r
- /* Interrupt occurred */\r
- itstatus = SET;\r
- }\r
- else\r
- {\r
- /* Interrupt didn't occur */\r
- itstatus = RESET;\r
- }\r
- }\r
- else /* AES_IT is AES_IT_ERR */\r
- {\r
- /* Check the status of the specified AES interrupt */\r
- if ((AES->CR & AES_CR_ERRIE) != RESET)\r
- {\r
- /* Check if WRERR or RDERR flags are set */\r
- if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)\r
- {\r
- /* Interrupt occurred */\r
- itstatus = SET;\r
- }\r
- else\r
- {\r
- /* Interrupt didn't occur */\r
- itstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- /* Interrupt didn't occur */\r
- itstatus = (ITStatus) RESET;\r
- }\r
- }\r
-\r
- /* Return the AES_IT status */\r
- return itstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the AES's interrupt pending bits.\r
- * @param AES_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combinations of the following values:\r
- * @arg AES_IT_CC: Computation Complete Interrupt.\r
- * @arg AES_IT_ERR: Error Interrupt.\r
- * @retval None\r
- */\r
-void AES_ClearITPendingBit(uint32_t AES_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_AES_IT(AES_IT));\r
-\r
- /* Clear the interrupt pending bit */\r
- AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_aes_util.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides high level functions to encrypt and decrypt an \r
- * input message using AES in ECB/CBC/CTR modes.\r
- *\r
- * @verbatim\r
-\r
-================================================================================\r
- ##### How to use this driver #####\r
-================================================================================\r
- [..]\r
- (#) Enable The AES controller clock using \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.\r
-\r
- (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.\r
- (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.\r
-\r
- (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.\r
- (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.\r
-\r
- (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.\r
- (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.\r
-\r
- * @endverbatim\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_aes.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup AES \r
- * @brief AES driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup AES_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup AES_Group6 High Level AES functions\r
- * @brief High Level AES functions \r
- *\r
-@verbatim\r
-================================================================================\r
- ##### High Level AES functions #####\r
-================================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Encrypt using AES in ECB Mode\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
-\r
- /* AES Key initialisation */\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_ECB;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
- \r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
- \r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Decrypt using AES in ECB Mode\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
-\r
- /* AES Key initialisation */\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_ECB;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
- \r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
-\r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
-\r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Encrypt using AES in CBC Mode\r
- * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- AES_IVInitTypeDef AES_IVInitStructure;\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- uint32_t ivaddr = (uint32_t)InitVectors;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
-\r
- /* AES Key initialisation*/\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES Initialization Vectors */\r
- AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
- AES_IVInit(&AES_IVInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_CBC;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
- \r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
-\r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
-\r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Decrypt using AES in CBC Mode\r
- * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- AES_IVInitTypeDef AES_IVInitStructure;\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- uint32_t ivaddr = (uint32_t)InitVectors;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
- \r
- /* AES Key initialisation*/\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES Initialization Vectors */\r
- AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
- AES_IVInit(&AES_IVInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_CBC;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
-\r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
-\r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
-\r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Encrypt using AES in CTR Mode\r
- * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- AES_IVInitTypeDef AES_IVInitStructure;\r
-\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- uint32_t ivaddr = (uint32_t)InitVectors;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
-\r
- /* AES key initialisation*/\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES Initialization Vectors */\r
- AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));\r
- AES_IVInit(&AES_IVInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_CTR;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
-\r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
-\r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
-\r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Decrypt using AES in CTR Mode\r
- * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
- * @param Key: Key used for AES algorithm.\r
- * @param Input: pointer to the Input buffer.\r
- * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
- * @param Output: pointer to the returned buffer.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Operation done\r
- * - ERROR: Operation failed\r
- */\r
-ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
-{\r
- AES_InitTypeDef AES_InitStructure;\r
- AES_KeyInitTypeDef AES_KeyInitStructure;\r
- AES_IVInitTypeDef AES_IVInitStructure;\r
-\r
- ErrorStatus status = SUCCESS;\r
- uint32_t keyaddr = (uint32_t)Key;\r
- uint32_t inputaddr = (uint32_t)Input;\r
- uint32_t outputaddr = (uint32_t)Output;\r
- uint32_t ivaddr = (uint32_t)InitVectors;\r
- __IO uint32_t counter = 0;\r
- uint32_t ccstatus = 0;\r
- uint32_t i = 0;\r
-\r
- /* AES Key initialisation*/\r
- AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
- keyaddr += 4;\r
- AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
- AES_KeyInit(&AES_KeyInitStructure);\r
-\r
- /* AES Initialization Vectors */\r
- AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
- ivaddr += 4;\r
- AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
- AES_IVInit(&AES_IVInitStructure);\r
-\r
- /* AES configuration */\r
- AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
- AES_InitStructure.AES_Chaining = AES_Chaining_CTR;\r
- AES_InitStructure.AES_DataType = AES_DataType_8b;\r
- AES_Init(&AES_InitStructure);\r
-\r
- /* Enable AES */\r
- AES_Cmd(ENABLE);\r
-\r
- for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
- {\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- AES_WriteSubData(*(uint32_t*)(inputaddr));\r
- inputaddr += 4;\r
- \r
- /* Wait for CCF flag to be set */\r
- counter = 0;\r
- do\r
- {\r
- ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
- counter++;\r
- }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
-\r
- if (ccstatus == RESET)\r
- {\r
- status = ERROR;\r
- }\r
- else\r
- {\r
- /* Clear CCF flag */\r
- AES_ClearFlag(AES_FLAG_CCF);\r
- \r
- /* Read cipher text */\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
- outputaddr += 4;\r
- }\r
- }\r
-\r
- /* Disable AES before starting new processing */\r
- AES_Cmd(DISABLE);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_comp.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
- * + Comparators configuration\r
- * + Window mode control\r
- * + Internal Reference Voltage (VREFINT) output\r
- *\r
- * @verbatim\r
- ===============================================================================\r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..] The device integrates two analog comparators COMP1 and COMP2:\r
- (+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting\r
- input with the ADC channels.\r
- (+) COMP2 is a rail-to-rail comparator whose the inverting input can be \r
- selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4 \r
- VREFINT, VREFINT, PB3 and whose the output can be redirected to \r
- embedded timers: TIM2, TIM3, TIM4, TIM10.\r
- \r
- (+) The two comparators COMP1 and COMP2 can be combined in window mode.\r
-\r
- -@-\r
- (#@) Comparator APB clock must be enabled to get write access\r
- to comparator register using\r
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).\r
- \r
- (#@) COMP1 comparator and ADC can't be used at the same time since\r
- they share the same ADC switch matrix (analog switches).\r
- \r
- (#@) When an I/O is used as comparator input, the corresponding GPIO \r
- registers should be configured in analog mode.\r
- \r
- (#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on\r
- GPIO pin. They are only internal.\r
- To get the comparator output level, use COMP_GetOutputLevel().\r
- \r
- (#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
- and EXTI Line 22 respectively.\r
- Interrupts can be used by configuring the EXTI Line using the \r
- EXTI peripheral driver.\r
- \r
- (#@) After enabling the comparator (COMP1 or COMP2), user should wait\r
- for start-up time (tSTART) to get right output levels.\r
- Please refer to product datasheet for more information on tSTART.\r
- \r
- (#@) Comparators cannot be used to exit the device from Sleep or Stop \r
- mode when the internal reference voltage is switched off using \r
- the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).\r
- \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_comp.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup COMP \r
- * @brief COMP driver modules.\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup COMP_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup COMP_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes COMP peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void COMP_DeInit(void)\r
-{\r
- COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */\r
-}\r
-\r
-/**\r
- * @brief Initializes the COMP2 peripheral according to the specified parameters\r
- * in the COMP_InitStruct.\r
- * @note This function configures only COMP2.\r
- * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are \r
- * different from "000".\r
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
- * the configuration information for the specified COMP peripheral. \r
- * @retval None\r
- */\r
-void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
- assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));\r
- assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));\r
-\r
- /*!< Get the COMP CSR value */\r
- tmpreg = COMP->CSR;\r
-\r
- /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ \r
- tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));\r
- \r
- /*!< Configure COMP: speed, inversion input selection and output redirection */\r
- /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */\r
- /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ \r
- /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ \r
- tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput \r
- | COMP_InitStruct->COMP_OutputSelect));\r
-\r
- /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are \r
- different from "000" */\r
- /*!< Write to COMP_CSR register */\r
- COMP->CSR = tmpreg; \r
-}\r
-\r
-/**\r
- * @brief Enable or disable the COMP1 peripheral.\r
- * @note After enabling COMP1, the following functions should be called to \r
- * connect the selected GPIO input to COMP1 non inverting input:\r
- * @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd()\r
- * @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig()\r
- * @note Close the I/O switch number n corresponding to the I/O \r
- * using SYSCFG_RIIOSwitchConfig()\r
- * @param NewState: new state of the COMP1 peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note This function enables/disables only the COMP1.\r
- * @retval None\r
- */\r
-void COMP_Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the COMP1 */\r
- COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;\r
- }\r
- else\r
- {\r
- /* Disable the COMP1 */\r
- COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Return the output level (high or low) of the selected comparator.\r
- * @note Comparator output is low when the noninverting input is at a lower\r
- * voltage than the inverting input.\r
- * @note Comparator output is high when the noninverting input is at a higher\r
- * voltage than the inverting input.\r
- * @note Comparators outputs aren't available on GPIO (outputs levels are \r
- * only internal). The COMP1 and COMP2 outputs are connected internally \r
- * to the EXTI Line 21 and Line 22 respectively.\r
- * @param COMP_Selection: the selected comparator.\r
- * This parameter can be one of the following values:\r
- * @arg COMP_Selection_COMP1: COMP1 selected\r
- * @arg COMP_Selection_COMP2: COMP2 selected\r
- * @retval Returns the selected comparator output level.\r
- */\r
-uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
-{\r
- uint8_t compout = 0x0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
-\r
- /* Check if Comparator 1 is selected */\r
- if(COMP_Selection == COMP_Selection_COMP1)\r
- {\r
- /* Check if comparator 1 output level is high */\r
- if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)\r
- {\r
- /* Get Comparator 1 output level */\r
- compout = (uint8_t) COMP_OutputLevel_High;\r
- }\r
- /* comparator 1 output level is low */\r
- else\r
- {\r
- /* Get Comparator 1 output level */\r
- compout = (uint8_t) COMP_OutputLevel_Low;\r
- }\r
- }\r
- /* Comparator 2 is selected */\r
- else\r
- {\r
- /* Check if comparator 2 output level is high */\r
- if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)\r
- {\r
- /* Get Comparator output level */\r
- compout = (uint8_t) COMP_OutputLevel_High;\r
- }\r
- /* comparator 2 output level is low */\r
- else\r
- {\r
- /* Get Comparator 2 output level */\r
- compout = (uint8_t) COMP_OutputLevel_Low;\r
- }\r
- }\r
- /* Return the comparator output level */\r
- return (uint8_t)(compout);\r
-}\r
-\r
-/**\r
- * @brief Close or Open the SW1 switch.\r
- * @param NewState: new state of the SW1 switch.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note ENABLE to close the SW1 switch\r
- * @note DISABLE to open the SW1 switch\r
- * @retval None.\r
- */\r
-void COMP_SW1SwitchConfig(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Close SW1 switch */\r
- COMP->CSR |= (uint32_t) COMP_CSR_SW1;\r
- }\r
- else\r
- {\r
- /* Open SW1 switch */\r
- COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup COMP_Group2 Window mode control function\r
- * @brief Window mode control function.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Window mode control function #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the window mode.\r
- * In window mode:\r
- * @note COMP1 inverting input is fixed to VREFINT defining the first\r
- * threshold.\r
- * @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT\r
- * sub-multiples, PB3) defining the second threshold.\r
- * @note COMP1 and COMP2 non inverting inputs are connected together.\r
- * @note In window mode, only the Group 6 (PB4 or PB5) can be used as\r
- * noninverting inputs.\r
- * @param NewState: new state of the window mode. \r
- * This parameter can be ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void COMP_WindowCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the window mode */\r
- COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;\r
- }\r
- else\r
- {\r
- /* Disable the window mode */\r
- COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup COMP_Group3 Internal Reference Voltage output function\r
- * @brief Internal Reference Voltage (VREFINT) output function.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Internal Reference Voltage (VREFINT) output function #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the output of internal reference voltage (VREFINT).\r
- * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or\r
- * CH9 (PB1).\r
- * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function\r
- * should be called after.\r
- * @param NewState: new state of the Vrefint output.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void COMP_VrefintOutputCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the output of internal reference voltage */\r
- COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;\r
- }\r
- else\r
- {\r
- /* Disable the output of internal reference voltage */\r
- COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_crc.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides all the CRC firmware functions.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_crc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC \r
- * @brief CRC driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup CRC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the CRC Data register (DR).\r
- * @param None\r
- * @retval None\r
- */\r
-void CRC_ResetDR(void)\r
-{\r
- /* Reset CRC generator */\r
- CRC->CR = CRC_CR_RESET;\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
- * @param Data: data word(32-bit) to compute its CRC.\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcCRC(uint32_t Data)\r
-{\r
- CRC->DR = Data;\r
- \r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
- * @param pBuffer: pointer to the buffer containing the data to be computed.\r
- * @param BufferLength: length of the buffer to be computed \r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
-{\r
- uint32_t index = 0;\r
- \r
- for(index = 0; index < BufferLength; index++)\r
- {\r
- CRC->DR = pBuffer[index];\r
- }\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Returns the current CRC value.\r
- * @param None\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_GetCRC(void)\r
-{\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
- * @param IDValue: 8-bit value to be stored in the ID register \r
- * @retval None\r
- */\r
-void CRC_SetIDRegister(uint8_t IDValue)\r
-{\r
- CRC->IDR = IDValue;\r
-}\r
-\r
-/**\r
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r
- * @param None\r
- * @retval 8-bit value of the ID register \r
- */\r
-uint8_t CRC_GetIDRegister(void)\r
-{\r
- return (CRC->IDR);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dac.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral: \r
- * + DAC channels configuration: trigger, output buffer, data format\r
- * + DMA management \r
- * + Interrupts and flags management\r
-\r
- * @verbatim \r
- * \r
- ===============================================================================\r
- ##### DAC Peripheral features #####\r
- ===============================================================================\r
- [..] The device integrates two 12-bit Digital Analog Converters that can \r
- be used independently or simultaneously (dual mode):\r
- (#) DAC channel1 with DAC_OUT1 (PA4) as output.\r
- (#) DAC channel2 with DAC_OUT2 (PA5) as output.\r
- \r
- [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
- and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using \r
- DAC_SetChannel1Data()/DAC_SetChannel2Data.\r
- \r
- [..] Digital to Analog conversion can be triggered by:\r
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
- The used pin (GPIOx_Pin9) must be configured in input mode.\r
- (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 \r
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).\r
- The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
- (#) Software using DAC_Trigger_Software.\r
- \r
- [..] Each DAC channel integrates an output buffer that can be used to \r
- reduce the output impedance, and to drive external loads directly\r
- without having to add an external operational amplifier.\r
- To enable, the output buffer use \r
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
- \r
- [..] Refer to the device datasheet for more details about output impedance\r
- value with and without output buffer.\r
- \r
- [..] Both DAC channels can be used to generate:\r
- (#) Noise wave using DAC_WaveGeneration_Noise\r
- (#) Triangle wave using DAC_WaveGeneration_Triangle\r
- \r
- [..] Wave generation can be disabled using DAC_WaveGeneration_None.\r
- \r
- [..] The DAC data format can be:\r
- (#) 8-bit right alignment using DAC_Align_8b_R\r
- (#) 12-bit left alignment using DAC_Align_12b_L\r
- (#) 12-bit right alignment using DAC_Align_12b_R\r
- \r
- [..] The analog output voltage on each DAC channel pin is determined\r
- by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
- with DOR is the Data Output Register.\r
- VEF+ is the input voltage reference (refer to the device datasheet)\r
- e.g. To set DAC_OUT1 to 0.7V, use\r
- DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
- Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.\r
- \r
- [..] A DMA1 request can be generated when an external trigger (but not\r
- a software trigger) occurs if DMA1 requests are enabled using\r
- DAC_DMACmd()\r
- [..] DMA1 requests are mapped as following:\r
- (#) DAC channel1 is mapped on DMA1 channel3 which must be already \r
- configured.\r
- (#) DAC channel2 is mapped on DMA1 channel4 which must be already \r
- configured.\r
- \r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..]\r
- (+) DAC APB clock must be enabled to get write access to DAC registers using\r
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
- (+) Configure the DAC channel using DAC_Init()\r
- (+) Enable the DAC channel using DAC_Cmd()\r
-\r
- @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dac.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC \r
- * @brief DAC driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* CR register Mask */\r
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
-\r
-/* DAC Dual Channels SWTRIG masks */\r
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
-\r
-/* DHR registers offsets */\r
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
-\r
-/* DOR register offset */\r
-#define DOR_OFFSET ((uint32_t)0x0000002C)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DAC_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup DAC_Group1 DAC channels configuration\r
- * @brief DAC channels configuration: trigger, output buffer, data format.\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DAC channels configuration: trigger, output buffer, data format #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void DAC_DeInit(void)\r
-{\r
- /* Enable DAC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
- /* Release DAC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the DAC peripheral according to the specified \r
- * parameters in the DAC_InitStruct.\r
- * @param DAC_Channel: the selected DAC channel.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected.\r
- * @arg DAC_Channel_2: DAC Channel2 selected.\r
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
- * contains the configuration information for the specified DAC channel.\r
- * @retval None\r
- */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
-\r
- /* Check the DAC parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
-\r
-/*---------------------------- DAC CR Configuration --------------------------*/\r
- /* Get the DAC CR value */\r
- tmpreg1 = DAC->CR;\r
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
- /* Configure for the selected DAC channel: buffer output, trigger, wave generation,\r
- mask/amplitude for wave generation */\r
- /* Set TSELx and TENx bits according to DAC_Trigger value */\r
- /* Set WAVEx bits according to DAC_WaveGeneration value */\r
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
- /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
- /* Calculate CR register value depending on DAC_Channel */\r
- tmpreg1 |= tmpreg2 << DAC_Channel;\r
- /* Write to DAC CR */\r
- DAC->CR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each DAC_InitStruct member with its default value.\r
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will \r
- * be initialized.\r
- * @retval None\r
- */\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
-/*--------------- Reset DAC init structure parameters values -----------------*/\r
- /* Initialize the DAC_Trigger member */\r
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
- /* Initialize the DAC_WaveGeneration member */\r
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
- /* Initialize the DAC_OutputBuffer member */\r
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel.\r
- * @param DAC_Channel: The selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the DAC channel. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the DAC channel is enabled the trigger source can no more\r
- * be modified.\r
- * @retval None\r
- */\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel */\r
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel */\r
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel software trigger.\r
- * @param DAC_Channel: the selected DAC channel.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel software trigger.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
- }\r
- else\r
- {\r
- /* Disable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables simultaneously the two DAC channels software\r
- * triggers.\r
- * @param NewState: new state of the DAC channels software triggers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for both DAC channels */\r
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r
- }\r
- else\r
- {\r
- /* Disable software trigger for both DAC channels */\r
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel wave generation.\r
- * @param DAC_Channel: the selected DAC channel.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_Wave: Specifies the wave type to enable or disable.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Wave_Noise: noise wave generation\r
- * @arg DAC_Wave_Triangle: triangle wave generation\r
- * @param NewState: new state of the selected DAC channel wave generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note \r
- * @retval None\r
- */\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_WAVE(DAC_Wave)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected wave generation for the selected DAC channel */\r
- DAC->CR |= DAC_Wave << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected wave generation for the selected DAC channel */\r
- DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel1.\r
- * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
-{ \r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE; \r
- tmp += DHR12R1_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel1 selected data holding register */\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel2.\r
- * @param DAC_Align: Specifies the data alignment for DAC channel2.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12R2_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel2 selected data holding register */\r
- *(__IO uint32_t *)tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for dual channel DAC.\r
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
- * holding register.\r
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
- * holding register.\r
- * @note In dual mode, a unique register access is required to write in both\r
- * DAC channels at the same time.\r
- * @retval None\r
- */\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
-{\r
- uint32_t data = 0, tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data1));\r
- assert_param(IS_DAC_DATA(Data2));\r
- \r
- /* Calculate and set dual DAC data holding register value */\r
- if (DAC_Align == DAC_Align_8b_R)\r
- {\r
- data = ((uint32_t)Data2 << 8) | Data1; \r
- }\r
- else\r
- {\r
- data = ((uint32_t)Data2 << 16) | Data1;\r
- }\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12RD_OFFSET + DAC_Align;\r
-\r
- /* Set the dual DAC selected data holding register */\r
- *(__IO uint32_t *)tmp = data;\r
-}\r
-\r
-/**\r
- * @brief Returns the last data output value of the selected DAC channel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @retval The selected DAC channel data output value.\r
- */\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- \r
- tmp = (uint32_t) DAC_BASE ;\r
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
- \r
- /* Returns the DAC channel data output register value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Group2 DMA management functions\r
- * @brief DMA management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DMA management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel DMA request.\r
- * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
- * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.\r
- * @param DAC_Channel: the selected DAC channel.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which \r
- * must be already configured. \r
- * @retval None\r
- */\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel DMA request */\r
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel DMA request */\r
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC interrupts.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
- * This parameter can be the following value:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @param NewState: new state of the specified DAC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */ \r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC interrupts */\r
- DAC->CR |= (DAC_IT << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC interrupts */\r
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC flag is set or not.\r
- * @param DAC_Channel: thee selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to check. \r
- * This parameter can be only of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @retval The new state of DAC_FLAG (SET or RESET).\r
- */\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Check the status of the specified DAC flag */\r
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
- {\r
- /* DAC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channel's pending flags.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to clear. \r
- * This parameter can be the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
- * @retval None\r
- */\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Clear the selected DAC flags */\r
- DAC->SR = (DAC_FLAG << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC interrupt has occurred or not.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt source to check. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
- * @note The DMA underrun occurs when a second external trigger arrives before\r
- * the acknowledgement for the first external trigger is received (first request).\r
- * @retval The new state of DAC_IT (SET or RESET).\r
- */\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT));\r
-\r
- /* Get the DAC_IT enable bit status */\r
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
- \r
- /* Check the status of the specified DAC interrupt */\r
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* DAC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channel's interrupt pending bits.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
- * @retval None\r
- */\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- /* Clear the selected DAC interrupt pending bits */\r
- DAC->SR = (DAC_IT << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dbgmcu.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides all the DBGMCU firmware functions.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dbgmcu.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU \r
- * @brief DBGMCU driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the device revision identifier.\r
- * @param None\r
- * @retval Device revision identifier\r
- */\r
-uint32_t DBGMCU_GetREVID(void)\r
-{\r
- return(DBGMCU->IDCODE >> 16);\r
-}\r
-\r
-/**\r
- * @brief Returns the device identifier.\r
- * @param None\r
- * @retval Device identifier\r
- */\r
-uint32_t DBGMCU_GetDEVID(void)\r
-{\r
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
-}\r
-\r
-/**\r
- * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the low power mode.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode\r
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode\r
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode\r
- * @param NewState: new state of the specified low power mode in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->CR |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->CR &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r
- * @arg DBGMCU_RTC_STOP:\r
- * + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when \r
- * Core is halted.\r
- * + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar \r
- * and Wakeup counter stopped when Core is halted.\r
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
- * halted\r
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
- * halted\r
- * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->APB1FZ |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
- * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
- * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->APB2FZ |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dma.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Direct Memory Access controller (DMA): \r
- * + Initialization and Configuration\r
- * + Data Counter\r
- * + Interrupts and flags management\r
- * \r
- * @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) Enable The DMA controller clock using \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or \r
- using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.\r
- (#) Enable and configure the peripheral to be connected to the DMA channel\r
- (except for internal SRAM / FLASH memories: no initialization is \r
- necessary).\r
- (#) For a given Channel, program the Source and Destination addresses, \r
- the transfer Direction, the Buffer Size, the Peripheral and Memory \r
- Incrementation mode and Data Size, the Circular or Normal mode, \r
- the channel transfer Priority and the Memory-to-Memory transfer \r
- mode (if needed) using the DMA_Init() function.\r
- (#) Enable the NVIC and the corresponding interrupt(s) using the function \r
- DMA_ITConfig() if you need to use DMA interrupts.\r
- (#) Enable the DMA channel using the DMA_Cmd() function.\r
- (#) Activate the needed channel Request using PPP_DMACmd() function for \r
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) \r
- The function allowing this operation is provided in each PPP peripheral \r
- driver (ie. SPI_DMACmd for SPI peripheral).\r
- (#) Optionally, you can configure the number of data to be transferred\r
- when the channel is disabled (ie. after each Transfer Complete event\r
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
- And you can get the number of remaining data to be transferred using \r
- the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
- enabled and running).\r
- (#) To control DMA events you can use one of the following two methods:\r
- (##) Check on DMA channel flags using the function DMA_GetFlagStatus().\r
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization\r
- phase and DMA_GetITStatus() function into interrupt routines in\r
- communication phase.\r
- After checking on a flag you should clear it using DMA_ClearFlag()\r
- function. And after checking on an interrupt event you should \r
- clear it using DMA_ClearITPendingBit() function.\r
- @endverbatim\r
- \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dma.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA \r
- * @brief DMA driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* DMA1 Channelx interrupt pending bit masks */\r
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
-\r
-/* DMA2 Channelx interrupt pending bit masks */\r
-#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-\r
-/* DMA FLAG mask */\r
-#define FLAG_MASK ((uint32_t)0x10000000)\r
-\r
-/* DMA registers Masks */\r
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
- [..] This subsection provides functions allowing to initialize the DMA channel \r
- source and destination addresses, incrementation and data sizes, transfer \r
- direction, buffer size, circular/normal mode selection, memory-to-memory \r
- mode selection and channel priority value.\r
- [..] The DMA_Init() function follows the DMA configuration procedures as described \r
- in reference manual (RM0038).\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes the DMAy Channelx registers to their default reset\r
- * values.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
-\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
-\r
- /* Reset DMAy Channelx control register */\r
- DMAy_Channelx->CCR = 0;\r
- \r
- /* Reset DMAy Channelx remaining bytes register */\r
- DMAy_Channelx->CNDTR = 0;\r
- \r
- /* Reset DMAy Channelx peripheral address register */\r
- DMAy_Channelx->CPAR = 0;\r
- \r
- /* Reset DMAy Channelx memory address register */\r
- DMAy_Channelx->CMAR = 0;\r
- \r
- if (DMAy_Channelx == DMA1_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel1 */\r
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel2 */\r
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel3 */\r
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel4 */\r
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel5 */\r
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel6)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel6 */\r
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel7)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel7 */\r
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel1 */\r
- DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel2 */\r
- DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel3 */\r
- DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel4 */\r
- DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;\r
- }\r
- else\r
- { \r
- if (DMAy_Channelx == DMA2_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel5 */\r
- DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMAy Channelx according to the specified\r
- * parameters in the DMA_InitStruct.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
- * contains the configuration information for the specified DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
-\r
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
- /* Get the DMAy_Channelx CCR value */\r
- tmpreg = DMAy_Channelx->CCR;\r
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmpreg &= CCR_CLEAR_MASK;\r
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
- /* Set DIR bit according to DMA_DIR value */\r
- /* Set CIRC bit according to DMA_Mode value */\r
- /* Set PINC bit according to DMA_PeripheralInc value */\r
- /* Set MINC bit according to DMA_MemoryInc value */\r
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
- /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
- /* Set PL bits according to DMA_Priority value */\r
- /* Set the MEM2MEM bit according to DMA_M2M value */\r
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
-\r
- /* Write to DMAy Channelx CCR */\r
- DMAy_Channelx->CCR = tmpreg;\r
-\r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
-\r
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CPAR */\r
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
-\r
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CMAR */\r
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
-}\r
-\r
-/**\r
- * @brief Fills each DMA_InitStruct member with its default value.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
-/*-------------- Reset DMA init structure parameters values ------------------*/\r
- /* Initialize the DMA_PeripheralBaseAddr member */\r
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
- /* Initialize the DMA_MemoryBaseAddr member */\r
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
- /* Initialize the DMA_DIR member */\r
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
- /* Initialize the DMA_BufferSize member */\r
- DMA_InitStruct->DMA_BufferSize = 0;\r
- /* Initialize the DMA_PeripheralInc member */\r
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- /* Initialize the DMA_MemoryInc member */\r
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
- /* Initialize the DMA_PeripheralDataSize member */\r
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
- /* Initialize the DMA_MemoryDataSize member */\r
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
- /* Initialize the DMA_Mode member */\r
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
- /* Initialize the DMA_Priority member */\r
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
- /* Initialize the DMA_M2M member */\r
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param NewState: new state of the DMAy Channelx. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group2 Data Counter functions\r
- * @brief Data Counter functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Data Counter functions #####\r
- ===============================================================================\r
- [..] This subsection provides function allowing to configure and read the buffer \r
- size (number of data to be transferred).The DMA data counter can be written \r
- only when the DMA channel is disabled (ie. after transfer complete event).\r
- [..] The following function can be used to write the Channel data counter value:\r
- (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t \r
- DataNumber).\r
- -@- It is advised to use this function rather than DMA_Init() in situations \r
- where only the Data buffer needs to be reloaded.\r
- [..] The DMA data counter can be read to indicate the number of remaining transfers \r
- for the relative DMA channel. This counter is decremented at the end of each \r
- data transfer and when the transfer is complete: \r
- (+) If Normal mode is selected: the counter is set to 0.\r
- (+) If Circular mode is selected: the counter is reloaded with the initial \r
- value(configured before enabling the DMA channel).\r
- [..] The following function can be used to read the Channel data counter value:\r
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DataNumber: The number of data units in the current DMAy Channelx\r
- * transfer.\r
- * @note This function can only be used when the DMAy_Channelx is disabled.\r
- * @retval None.\r
- */\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- \r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DataNumber; \r
-}\r
-\r
-/**\r
- * @brief Returns the number of remaining data units in the current\r
- * DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval The number of remaining data units in the current DMAy Channelx\r
- * transfer.\r
- */\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Return the number of remaining data units for DMAy Channelx */\r
- return ((uint16_t)(DMAy_Channelx->CNDTR));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
- [..] This subsection provides functions allowing to configure the DMA Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage \r
- the DMA controller events: Polling mode or Interrupt mode. \r
- *** Polling Mode ***\r
- ====================\r
- [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller \r
- number x : DMA channel number ).\r
- (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.\r
- (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.\r
- (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.\r
- (#) DMAy_FLAG_GLx : to indicate that at least one of the events described \r
- above occurred.\r
- -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
- [..]In this Mode it is advised to use the following functions:\r
- (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
- (+) void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-\r
- *** Interrupt Mode ***\r
- ======================\r
- [..] Each DMA channel can be managed through 4 Interrupts:\r
- (+) Interrupt Source\r
- (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete \r
- event.\r
- (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete \r
- event.\r
- (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
- (##) DMA_IT_GL : to indicate that at least one of the interrupts described \r
- above occurred.\r
- -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of \r
- the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
- [..]In this Mode it is advised to use the following functions:\r
- (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, \r
- FunctionalState NewState);\r
- (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
- (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx interrupts.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
- * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
- * or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @param NewState: new state of the specified DMA interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMA interrupts */\r
- DMAy_Channelx->CCR |= DMA_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMA interrupts */\r
- DMAy_Channelx->CCR &= ~DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
- * @param DMAy_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
- * \r
- * @note\r
- * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
- * relative to the same channel is set (Transfer Complete, Half-transfer \r
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
- * DMAy_FLAG_TEx). \r
- * \r
- * @retval The new state of DMAy_FLAG (SET or RESET).\r
- */\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));\r
-\r
- /* Calculate the used DMAy */\r
- if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR;\r
- }\r
- else\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR;\r
- }\r
-\r
- /* Check the status of the specified DMAy flag */\r
- if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)\r
- {\r
- /* DMAy_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMAy_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the DMAy_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's pending flags.\r
- * @param DMAy_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. \r
- * \r
- * @note\r
- * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
- * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearFlag(uint32_t DMAy_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));\r
-\r
- if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMAy flags */\r
- DMA1->IFCR = DMAy_FLAG;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMAy flags */\r
- DMA2->IFCR = DMAy_FLAG;\r
- } \r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
- * @param DMAy_IT: specifies the DMAy interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. \r
- * \r
- * @note\r
- * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
- * interrupts relative to the same channel is set (Transfer Complete, \r
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
- * DMAy_IT_HTx or DMAy_IT_TEx). \r
- * \r
- * @retval The new state of DMAy_IT (SET or RESET).\r
- */\r
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_IT(DMAy_IT));\r
-\r
- /* Calculate the used DMAy */\r
- if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR;\r
- }\r
- else\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR;\r
- }\r
- \r
- /* Check the status of the specified DMAy interrupt */\r
- if ((tmpreg & DMAy_IT) != (uint32_t)RESET)\r
- {\r
- /* DMAy_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMAy_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DMAy_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's interrupt pending bits.\r
- * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. \r
- * \r
- * @note\r
- * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
- * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
- * DMAy_IT_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearITPendingBit(uint32_t DMAy_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_IT(DMAy_IT));\r
-\r
- /* Calculate the used DMAy */\r
- if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMAy interrupt pending bits */\r
- DMA1->IFCR = DMAy_IT;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMAy interrupt pending bits */\r
- DMA2->IFCR = DMAy_IT;\r
- } \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides all the Flash firmware functions. These functions \r
- * can be executed from Internal FLASH or Internal SRAM memories. \r
- * The functions that should be called from SRAM are defined inside \r
- * the "stm32l1xx_flash_ramfunc.c" file.\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the FLASH peripheral:\r
- * + FLASH Interface configuration\r
- * + FLASH Memory Programming\r
- * + DATA EEPROM Programming\r
- * + Option Bytes Programming\r
- * + Interrupts and flags management\r
- *\r
- * @verbatim\r
-\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..] This driver provides functions to configure and program the Flash \r
- memory of all STM32L1xx devices.\r
- [..] These functions are split in 5 groups:\r
- (#) FLASH Interface configuration functions: this group includes \r
- the management of following features:\r
- (++) Set the latency.\r
- (++) Enable/Disable the prefetch buffer.\r
- (++) Enable/Disable the 64 bit Read Access. \r
- (++) Enable/Disable the RUN PowerDown mode.\r
- (++) Enable/Disable the SLEEP PowerDown mode. \r
- \r
- (#) FLASH Memory Programming functions: this group includes all \r
- needed functions to erase and program the main memory:\r
- (++) Lock and Unlock the Flash interface.\r
- (++) Erase function: Erase Page.\r
- (++) Program functions: Fast Word and Half Page(should be \r
- executed from internal SRAM).\r
- \r
- (#) DATA EEPROM Programming functions: this group includes all \r
- needed functions to erase and program the DATA EEPROM memory:\r
- (++) Lock and Unlock the DATA EEPROM interface.\r
- (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase \r
- (++) Double Word (should be executed from internal SRAM).\r
- (++) Program functions: Fast Program Byte, Fast Program Half-Word, \r
- FastProgramWord, Program Byte, Program Half-Word, \r
- Program Word and Program Double-Word (should be executed \r
- from internal SRAM).\r
- \r
- (#) FLASH Option Bytes Programming functions: this group includes \r
- all needed functions to:\r
- (++) Lock and Unlock the Flash Option bytes.\r
- (++) Set/Reset the write protection.\r
- (++) Set the Read protection Level.\r
- (++) Set the BOR level.\r
- (++) rogram the user option Bytes.\r
- (++) Launch the Option Bytes loader.\r
- (++) Get the Write protection.\r
- (++) Get the read protection status.\r
- (++) Get the BOR level.\r
- (++) Get the user option bytes.\r
- \r
- (#) FLASH Interrupts and flag management functions: this group \r
- includes all needed functions to:\r
- (++) Enable/Disable the flash interrupt sources.\r
- (++) Get flags status.\r
- (++) Clear flags.\r
- (++) Get Flash operation status.\r
- (++) Wait for last flash operation.\r
-\r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_flash.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
- \r
-/* FLASH Mask */\r
-#define WRP01_MASK ((uint32_t)0x0000FFFF)\r
-#define WRP23_MASK ((uint32_t)0xFFFF0000)\r
-#define WRP45_MASK ((uint32_t)0x0000FFFF)\r
-#define WRP67_MASK ((uint32_t)0xFFFF0000)\r
-#define WRP89_MASK ((uint32_t)0x0000FFFF)\r
-#define WRP1011_MASK ((uint32_t)0xFFFF0000)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
- * @brief FLASH Interface configuration functions \r
- *\r
-@verbatim \r
- ============================================================================== \r
- ##### FLASH Interface configuration functions #####\r
- ==============================================================================\r
-\r
- [..] FLASH_Interface configuration_Functions, includes the following functions:\r
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency):\r
- [..] To correctly read data from Flash memory, the number of wait states (LATENCY) \r
- must be correctly programmed according to the frequency of the CPU clock \r
- (HCLK) and the supply voltage of the device.\r
- [..] \r
- ----------------------------------------------------------------\r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------|\r
- | (Latency) | voltage range | voltage range |\r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------|\r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |-------------- |----------------|---------------|---------------|\r
- |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |---------------|----------------|---------------|---------------|\r
- |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
- ----------------------------------------------------------------\r
- [..]\r
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
- (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
- (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
- (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
- (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
- [..] \r
- Here below the allowed configuration of Latency, 64Bit access and prefetch buffer\r
- [..] \r
- --------------------------------------------------------------------------------\r
- | | ACC64 = 0 | ACC64 = 1 |\r
- | Latency |----------------|---------------|---------------|---------------|\r
- | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 |\r
- |---------------|----------------|---------------|---------------|---------------|\r
- |0WS(1CPU cycle)| YES | NO | YES | YES |\r
- |---------------|----------------|---------------|---------------|---------------|\r
- |1WS(2CPU cycle)| NO | NO | YES | YES |\r
- --------------------------------------------------------------------------------\r
- [..]\r
- All these functions don't need the unlock sequence.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the code latency value.\r
- * @param FLASH_Latency: specifies the FLASH Latency value.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle.\r
- * @arg FLASH_Latency_1: FLASH One Latency cycle.\r
- * @retval None\r
- */\r
-void FLASH_SetLatency(uint32_t FLASH_Latency)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
- \r
- /* Read the ACR register */\r
- tmpreg = FLASH->ACR; \r
- \r
- /* Sets the Latency value */\r
- tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
- tmpreg |= FLASH_Latency;\r
- \r
- /* Write the ACR register */\r
- FLASH->ACR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Prefetch Buffer.\r
- * @param NewState: new state of the FLASH prefetch buffer.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->ACR |= FLASH_ACR_PRFTEN;\r
- }\r
- else\r
- {\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables read access to flash by 64 bits.\r
- * @param NewState: new state of the FLASH read access mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note If this bit is set, the Read access 64 bit is used.\r
- * If this bit is reset, the Read access 32 bit is used.\r
- * @note This bit cannot be written at the same time as the LATENCY and \r
- * PRFTEN bits.\r
- * To reset this bit, the LATENCY should be zero wait state and the \r
- * prefetch off.\r
- * @retval None\r
- */\r
-void FLASH_ReadAccess64Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->ACR |= FLASH_ACR_ACC64;\r
- }\r
- else\r
- {\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the power down mode during Sleep mode.\r
- * @note This function is used to power down the FLASH when the system is in SLEEP LP mode.\r
- * @param NewState: new state of the power down mode during sleep mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */\r
- FLASH->ACR |= FLASH_ACR_SLEEP_PD;\r
- }\r
- else\r
- {\r
- /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */\r
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
- * @brief FLASH Memory Programming functions\r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### FLASH Memory Programming functions ##### \r
- ==============================================================================\r
-\r
- [..] The FLASH Memory Programming functions, includes the following functions:\r
- (+) void FLASH_Unlock(void);\r
- (+) void FLASH_Lock(void);\r
- (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
- (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
- \r
- [..] Any operation of erase or program should follow these steps:\r
- (#) Call the FLASH_Unlock() function to enable the flash control register and \r
- program memory access.\r
- (#) Call the desired function to erase page or program data.\r
- (#) Call the FLASH_Lock() to disable the flash program memory access \r
- (recommended to protect the FLASH memory against possible unwanted operation).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the FLASH control register and program memory access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)\r
- {\r
- /* Unlocking the data memory and FLASH_PECR register access */\r
- DATA_EEPROM_Unlock();\r
- \r
- /* Unlocking the program memory access */\r
- FLASH->PRGKEYR = FLASH_PRGKEY1;\r
- FLASH->PRGKEYR = FLASH_PRGKEY2; \r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the Program memory access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Lock(void)\r
-{\r
- /* Set the PRGLOCK Bit to lock the program memory access */\r
- FLASH->PECR |= FLASH_PECR_PRGLOCK;\r
-}\r
-\r
-/**\r
- * @brief Erases a specified page in program memory.\r
- * @note To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation)\r
- * @param Page_Address: The page address in program memory to be erased.\r
- * @note A Page is erased in the Program memory only if the address to load \r
- * is the start address of a page (multiple of 256 bytes).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to erase the page */\r
-\r
- /* Set the ERASE bit */\r
- FLASH->PECR |= FLASH_PECR_ERASE;\r
-\r
- /* Set PROG bit */\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write 00000000h to the first word of the program page to erase */\r
- *(__IO uint32_t *)Page_Address = 0x00000000;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-\r
- /* If the erase operation is completed, disable the ERASE and PROG bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); \r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in program memory.\r
- * @note To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_Lock() to disable the flash memory access\r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to program the new word */ \r
- *(__IO uint32_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASH_Group3 DATA EEPROM Programming functions\r
- * @brief DATA EEPROM Programming functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### DATA EEPROM Programming functions ##### \r
- =============================================================================== \r
- \r
- [..] The DATA_EEPROM Programming_Functions, includes the following functions:\r
- (+) void DATA_EEPROM_Unlock(void);\r
- (+) void DATA_EEPROM_Lock(void);\r
- (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);\r
- (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);\r
- (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
- (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
- (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
- (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
- (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
- (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
- (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
- \r
- [..] Any operation of erase or program should follow these steps:\r
- (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access\r
- and Flash program erase control register access.\r
- (#) Call the desired function to erase or program data.\r
- (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access\r
- and Flash program erase control register access(recommended\r
- to protect the DATA_EEPROM against possible unwanted operation).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the data memory and FLASH_PECR register access.\r
- * @param None\r
- * @retval None\r
- */\r
-void DATA_EEPROM_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
- { \r
- /* Unlocking the Data memory and FLASH_PECR register access*/\r
- FLASH->PEKEYR = FLASH_PEKEY1;\r
- FLASH->PEKEYR = FLASH_PEKEY2;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the Data memory and FLASH_PECR register access.\r
- * @param None\r
- * @retval None\r
- */\r
-void DATA_EEPROM_Lock(void)\r
-{\r
- /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
- FLASH->PECR |= FLASH_PECR_PELOCK;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog).\r
- * @param NewState: new state of the DATA EEPROM fixed Time programming mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;\r
- }\r
- else\r
- {\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Erase a byte in data memory.\r
- * @param Address: specifies the address to be erased.\r
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
- * density devices.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Write "00h" to valid address in the data memory" */\r
- *(__IO uint8_t *) Address = (uint8_t)0x00;\r
- }\r
- \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erase a halfword in data memory.\r
- * @param Address: specifies the address to be erased.\r
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
- * density devices.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Write "0000h" to valid address in the data memory" */\r
- *(__IO uint16_t *) Address = (uint16_t)0x0000;\r
- }\r
- \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erase a word in data memory.\r
- * @param Address: specifies the address to be erased.\r
- * @note For STM32L1XX_MD, A data memory word is erased in the data memory only \r
- * if the address to load is the start address of a word (multiple of a word).\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Write "00000000h" to valid address in the data memory" */\r
- *(__IO uint32_t *) Address = 0x00000000;\r
- }\r
- \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a Byte at a specified address in data memory.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased.\r
- * @retval FLASH Status: The returned value can be:\r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- uint32_t tmp = 0, tmpaddr = 0;\r
-#endif\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
-\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- if(Data != (uint8_t)0x00) \r
- {\r
- /* If the previous operation is completed, proceed to write the new Data */\r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
- else\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr;\r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
- } \r
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
- /* If the previous operation is completed, proceed to write the new Data */\r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-#endif \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Writes a half word at a specified address in data memory.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- uint32_t tmp = 0, tmpaddr = 0;\r
-#endif\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
-\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- if(Data != (uint16_t)0x0000) \r
- {\r
- /* If the previous operation is completed, proceed to write the new data */\r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
- else\r
- {\r
- if((Address & 0x3) != 0x3)\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
- }\r
- else\r
- {\r
- DATA_EEPROM_FastProgramByte(Address, 0x00);\r
- DATA_EEPROM_FastProgramByte(Address + 1, 0x00);\r
- }\r
- }\r
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
- /* If the previous operation is completed, proceed to write the new data */\r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-#endif\r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in data memory.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to the data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note This function assumes that the is data word is already erased.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Clear the FTDW bit */\r
- FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
- \r
- /* If the previous operation is completed, proceed to program the new data */ \r
- *(__IO uint32_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a Byte at a specified address in data memory without erase.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming.\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- uint32_t tmp = 0, tmpaddr = 0;\r
-#endif\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- if(Data != (uint8_t) 0x00)\r
- { \r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-\r
- }\r
- else\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
- }\r
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
- *(__IO uint8_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-#endif\r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Writes a half word at a specified address in data memory without erase.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be:\r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- uint32_t tmp = 0, tmpaddr = 0;\r
-#endif\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
- if(Data != (uint16_t)0x0000)\r
- {\r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
- else\r
- {\r
- if((Address & 0x3) != 0x3)\r
- {\r
- tmpaddr = Address & 0xFFFFFFFC;\r
- tmp = * (__IO uint32_t *) tmpaddr;\r
- tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
- tmp &= ~tmpaddr; \r
- status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
- status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
- }\r
- else\r
- {\r
- DATA_EEPROM_FastProgramByte(Address, 0x00);\r
- DATA_EEPROM_FastProgramByte(Address + 1, 0x00);\r
- }\r
- }\r
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
- *(__IO uint16_t *)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-#endif\r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address in data memory without erase.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
- * this function to configure the Fixed Time Programming.\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @retval FLASH Status: The returned value can be:\r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- *(__IO uint32_t *)Address = Data;\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group4 Option Bytes Programming functions\r
- * @brief Option Bytes Programming functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Option Bytes Programming functions ##### \r
- ============================================================================== \r
-\r
- [..] The FLASH_Option Bytes Programming_functions, includes the following functions:\r
- (+) void FLASH_OB_Unlock(void);\r
- (+) void FLASH_OB_Lock(void);\r
- (+) void FLASH_OB_Launch(void);\r
- (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
- (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);\r
- (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState); \r
- (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
- (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
- (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
- (+) uint8_t FLASH_OB_GetUser(void);\r
- (+) uint32_t FLASH_OB_GetWRP(void);\r
- (+) uint32_t FLASH_OB_GetWRP1(void);\r
- (+) uint32_t FLASH_OB_GetWRP2(void); \r
- (+) FlagStatus FLASH_OB_GetRDP(void);\r
- (+) uint8_t FLASH_OB_GetBOR(void);\r
- (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT);\r
- \r
- [..] Any operation of erase or program should follow these steps:\r
- (#) Call the FLASH_OB_Unlock() function to enable the Flash option control \r
- register access.\r
- (#) Call one or several functions to program the desired option bytes.\r
- (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r
- the desired sector write protection.\r
- (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level.\r
- (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r
- the user option Bytes: IWDG, STOP and the Standby.\r
- (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level.\r
- (++) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes .\r
- (#) Once all needed option bytes to be programmed are correctly written, call the\r
- FLASH_OB_Launch(void) function to launch the Option Bytes programming process.\r
- (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
- to protect the option Bytes against possible unwanted operations).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlocks the option bytes block access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Unlock(void)\r
-{\r
- if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)\r
- {\r
- /* Unlocking the data memory and FLASH_PECR register access */\r
- DATA_EEPROM_Unlock();\r
- \r
- /* Unlocking the option bytes block access */\r
- FLASH->OPTKEYR = FLASH_OPTKEY1;\r
- FLASH->OPTKEYR = FLASH_OPTKEY2;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Locks the option bytes block access.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Lock(void)\r
-{\r
- /* Set the OPTLOCK Bit to lock the option bytes block access */\r
- FLASH->PECR |= FLASH_PECR_OPTLOCK;\r
-}\r
-\r
-/**\r
- * @brief Launch the option byte loading.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_OB_Launch(void)\r
-{\r
- /* Set the OBL_Launch bit to lauch the option byte loading */\r
- FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;\r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages.\r
- * @note To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_WRP: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @param value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511\r
- * @param OB_WRP_AllPages\r
- * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r
-{\r
- uint32_t WRP01_Data = 0, WRP23_Data = 0;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp1 = 0, tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(OB_WRP));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));\r
- WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); \r
- tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);\r
- OB->WRP01 = tmp1;\r
- \r
- tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);\r
- OB->WRP23 = tmp2; \r
- } \r
- \r
- else\r
- {\r
- WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));\r
- WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); \r
-\r
- tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);\r
- OB->WRP01 = tmp1;\r
- \r
- tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);\r
- OB->WRP23 = tmp2;\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
-\r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages.\r
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
- * density devices.\r
- * To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_WRP1: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @arg value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023\r
- * @arg OB_WRP_AllPages\r
- * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState)\r
-{\r
- uint32_t WRP45_Data = 0, WRP67_Data = 0;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp1 = 0, tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(OB_WRP1));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- WRP45_Data = (uint16_t)(((OB_WRP1 & WRP45_MASK) | OB->WRP45));\r
- WRP67_Data = (uint16_t)((((OB_WRP1 & WRP67_MASK)>>16 | OB->WRP67))); \r
- tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data);\r
- OB->WRP45 = tmp1;\r
- \r
- tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data);\r
- OB->WRP67 = tmp2; \r
- } \r
- \r
- else\r
- {\r
- WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45));\r
- WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67))); \r
-\r
- tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data);\r
- OB->WRP45 = tmp1;\r
- \r
- tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data);\r
- OB->WRP67 = tmp2;\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
-\r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages.\r
- * @note This function can be used only for STM32L1XX_HD density devices.\r
- * To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_WRP2: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @arg value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535\r
- * @arg OB_WRP_AllPages\r
- * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState)\r
-{\r
- uint32_t WRP89_Data = 0, WRP1011_Data = 0;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp1 = 0, tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(OB_WRP2));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- if (NewState != DISABLE)\r
- {\r
- WRP89_Data = (uint16_t)(((OB_WRP2 & WRP89_MASK) | OB->WRP89));\r
- WRP1011_Data = (uint16_t)((((OB_WRP2 & WRP1011_MASK)>>16 | OB->WRP1011))); \r
- tmp1 = (uint32_t)(~(WRP89_Data) << 16)|(WRP89_Data);\r
- OB->WRP89 = tmp1;\r
- \r
- tmp2 = (uint32_t)(~(WRP1011_Data) << 16)|(WRP1011_Data);\r
- OB->WRP1011 = tmp2; \r
- } \r
- \r
- else\r
- {\r
- WRP89_Data = (uint16_t)(~OB_WRP2 & (WRP89_MASK & OB->WRP89));\r
- WRP1011_Data = (uint16_t)((((~OB_WRP2 & WRP1011_MASK)>>16 & OB->WRP1011))); \r
-\r
- tmp1 = (uint32_t)((~WRP89_Data) << 16)|(WRP89_Data);\r
- OB->WRP89 = tmp1;\r
- \r
- tmp2 = (uint32_t)((~WRP1011_Data) << 16)|(WRP1011_Data);\r
- OB->WRP1011 = tmp2;\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- }\r
-\r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the read out protection.\r
- * @note To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
- * This parameter can be:\r
- * @arg OB_RDP_Level_0: No protection\r
- * @arg OB_RDP_Level_1: Read protection of the memory\r
- * @arg OB_RDP_Level_2: Chip protection\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint8_t tmp1 = 0;\r
- uint32_t tmp2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_RDP(OB_RDP));\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* calculate the option byte to write */\r
- tmp1 = (uint8_t)(~(OB_RDP ));\r
- tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* program read protection level */\r
- OB->RDP = tmp2;\r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Read protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
- * @note To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_IWDG: Selects the WDG mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_IWDG_SW: Software WDG selected\r
- * @arg OB_IWDG_HW: Hardware WDG selected\r
- * @param OB_STOP: Reset event when entering STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
- * @arg OB_STOP_RST: Reset generated when entering in STOP\r
- * @param OB_STDBY: Reset event when entering Standby mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE; \r
- uint32_t tmp = 0, tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
-\r
- /* Get the User Option byte register */\r
- tmp1 = (FLASH->OBR & 0x000F0000) >> 16;\r
- \r
- /* Calculate the user option byte to write */ \r
- tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));\r
- tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Write the User Option Byte */ \r
- OB->USER = tmp; \r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
- * @note To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_BOR: Selects the brownout reset threshold level.\r
- * This parameter can be one of the following values:\r
- * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD \r
- * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
- * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
- * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
- * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
- * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
- * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- uint32_t tmp = 0, tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
-\r
- /* Get the User Option byte register */\r
- tmp1 = (FLASH->OBR & 0x00F00000) >> 16;\r
- \r
- /* Calculate the option byte to write */\r
- tmp = (uint32_t)~(OB_BOR | tmp1)<<16;\r
- tmp |= (OB_BOR | tmp1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Write the BOR Option Byte */ \r
- OB->USER = tmp; \r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Configures to boot from Bank1 or Bank2.\r
- * @note This function can be used only for STM32L1XX_HD density devices.\r
- * To correctly run this function, the FLASH_OB_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param OB_BOOT: select the FLASH Bank to boot from.\r
- * This parameter can be one of the following values:\r
- * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
- * depending on the activation of the bank. The active banks are checked in\r
- * the following order: Bank2, followed by Bank1.\r
- * The active bank is recognized by the value programmed at the base address\r
- * of the respective bank (corresponding to the initial stack pointer value\r
- * in the interrupt vector table).\r
- * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank1(Default).\r
- * For more information, please refer to AN2606 from www.st.com. \r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE; \r
- uint32_t tmp = 0, tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_BOOT_BANK(OB_BOOT));\r
-\r
- /* Get the User Option byte register */\r
- tmp1 = (FLASH->OBR & 0x007F0000) >> 16;\r
- \r
- /* Calculate the option byte to write */\r
- tmp = (uint32_t)~(OB_BOOT | tmp1)<<16;\r
- tmp |= (OB_BOOT | tmp1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Write the BOOT Option Byte */ \r
- OB->USER = tmp; \r
- }\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH User Option Bytes values.\r
- * @param None\r
- * @retval The FLASH User Option Bytes.\r
- */\r
-uint8_t FLASH_OB_GetUser(void)\r
-{\r
- /* Return the User Option Byte */\r
- return (uint8_t)(FLASH->OBR >> 20);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes value.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes value.\r
- */\r
-uint32_t FLASH_OB_GetWRP(void)\r
-{\r
- /* Return the FLASH write protection Register value */\r
- return (uint32_t)(FLASH->WRPR);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes value.\r
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
- * density devices.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes value.\r
- */\r
-uint32_t FLASH_OB_GetWRP1(void)\r
-{\r
- /* Return the FLASH write protection Register value */\r
- return (uint32_t)(FLASH->WRPR1);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes value.\r
- * @note This function can be used only for STM32L1XX_HD density devices.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes value.\r
- */\r
-uint32_t FLASH_OB_GetWRP2(void)\r
-{\r
- /* Return the FLASH write protection Register value */\r
- return (uint32_t)(FLASH->WRPR2);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
- * @param None\r
- * @retval FLASH ReadOut Protection Status(SET or RESET).\r
- */\r
-FlagStatus FLASH_OB_GetRDP(void)\r
-{\r
- FlagStatus readstatus = RESET;\r
- \r
- if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)\r
- {\r
- readstatus = SET;\r
- }\r
- else\r
- {\r
- readstatus = RESET;\r
- }\r
- return readstatus;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH BOR level.\r
- * @param None\r
- * @retval The FLASH User Option Bytes.\r
- */\r
-uint8_t FLASH_OB_GetBOR(void)\r
-{\r
- /* Return the BOR level */\r
- return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Group5 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified FLASH interrupts.\r
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
- * disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
- * @arg FLASH_IT_ERR: FLASH Error Interrupt\r
- * @retval None \r
- */\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->PECR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->PECR &= ~(uint32_t)FLASH_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FLASH flag is set or not.\r
- * @param FLASH_FLAG: specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
- * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode\r
- * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag\r
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
- * @arg FLASH_FLAG_SIZERR: FLASH size error flag\r
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
- * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag\r
- * @retval The new state of FLASH_FLAG (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
-\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the new state of FLASH_FLAG (SET or RESET) */\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the FLASH's pending flags.\r
- * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
- * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
- * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag\r
- * @retval None\r
- */\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
- \r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
- */\r
-FLASH_Status FLASH_GetStatus(void)\r
-{\r
- FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- FLASHstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
- { \r
- FLASHstatus = FLASH_ERROR_WRP;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)\r
- {\r
- FLASHstatus = FLASH_ERROR_PROGRAM; \r
- }\r
- else\r
- {\r
- FLASHstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the FLASH Status */\r
- return FLASHstatus;\r
-}\r
-\r
-\r
-/**\r
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
- * @param Timeout: FLASH programming Timeout.\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- __IO FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the FLASH Status */\r
- status = FLASH_GetStatus();\r
- \r
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetStatus();\r
- Timeout--;\r
- }\r
- \r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- /**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_flash_ramfunc.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides all the Flash firmware functions which should be\r
- * executed from the internal SRAM. This file should be placed in \r
- * internal SRAM. \r
- * Other FLASH memory functions that can be used from the FLASH are \r
- * defined in the "stm32l1xx_flash.c" file. \r
-@verbatim\r
-\r
- *** ARM Compiler ***\r
- --------------------\r
- [..] RAM functions are defined using the toolchain options. \r
- Functions that are be executed in RAM should reside in a separate\r
- source module. Using the 'Options for File' dialog you can simply change\r
- the 'Code / Const' area of a module to a memory space in physical RAM.\r
- Available memory areas are declared in the 'Target' tab of the \r
- Options for Target' dialog.\r
-\r
- *** ICCARM Compiler ***\r
- -----------------------\r
- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
-\r
- *** GNU Compiler ***\r
- --------------------\r
- [..] RAM functions are defined using a specific toolchain attribute\r
- "__attribute__((section(".data")))".\r
-\r
- *** TASKING Compiler ***\r
- ------------------------\r
- [..] RAM functions are defined using a specific toolchain pragma. This \r
- pragma is defined inside this file.\r
-\r
-@endverbatim\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_flash.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-static __RAM_FUNC GetStatus(void);\r
-static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
- \r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */ \r
-\r
-/** @addtogroup FLASH_Group1\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */ \r
-#if defined ( __TASKING__ )\r
-#pragma section_code_init on\r
-#endif\r
-\r
-/**\r
- * @brief Enable or disable the power down mode during RUN mode.\r
- * @note This function can be used only when the user code is running from Internal SRAM.\r
- * @param NewState: new state of the power down mode during RUN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Unlock the RUN_PD bit */\r
- FLASH->PDKEYR = FLASH_PDKEY1;\r
- FLASH->PDKEYR = FLASH_PDKEY2;\r
- \r
- /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
-\r
- if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)\r
- {\r
- status = FLASH_ERROR_PROGRAM;\r
- }\r
- }\r
- else\r
- {\r
- /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
- FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
- }\r
-\r
- /* Return the Write Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Group2\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Erases a specified 2 page in program memory in parallel.\r
- * @note This function can be used only for STM32L1XX_HD density devices.\r
- * To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @param Page_Address1: The page address in program memory to be erased in \r
- * the first Bank (BANK1). This parameter should be between 0x08000000\r
- * and 0x0802FF00.\r
- * @param Page_Address2: The page address in program memory to be erased in \r
- * the second Bank (BANK2). This parameter should be between 0x08030000\r
- * and 0x0805FF00.\r
- * @note A Page is erased in the Program memory only if the address to load \r
- * is the start address of a page (multiple of 256 bytes).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to erase the page */\r
-\r
- /* Set the PARALLBANK bit */\r
- FLASH->PECR |= FLASH_PECR_PARALLBANK;\r
- \r
- /* Set the ERASE bit */\r
- FLASH->PECR |= FLASH_PECR_ERASE;\r
-\r
- /* Set PROG bit */\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write 00000000h to the first word of the first program page to erase */\r
- *(__IO uint32_t *)Page_Address1 = 0x00000000;\r
- /* Write 00000000h to the first word of the second program page to erase */ \r
- *(__IO uint32_t *)Page_Address2 = 0x00000000; \r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
-\r
- /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); \r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a half page in program memory.\r
- * @param Address: specifies the address to be written.\r
- * @param pBuffer: pointer to the buffer containing the data to be written to \r
- * the half page.\r
- * @note To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation)\r
- * @note Half page write is possible only from SRAM.\r
- * @note If there are more than 32 words to write, after 32 words another \r
- * Half Page programming operation starts and has to be finished.\r
- * @note A half page is written to the program memory only if the first \r
- * address to load is the start address of a half page (multiple of 128 \r
- * bytes) and the 31 remaining words to load are in the same half page.\r
- * @note During the Program memory half page write all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.).\r
- * @note If a PGAERR is set during a Program memory half page write, the \r
- * complete write operation is aborted. Software should then reset the \r
- * FPRG and PROG/DATA bits and restart the write operation from the \r
- * beginning.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)\r
-{\r
- uint32_t count = 0; \r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
- This bit prevents the interruption of multicycle instructions and therefore \r
- will increase the interrupt latency. of Cortex-M3. */\r
- SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new \r
- half page */\r
- FLASH->PECR |= FLASH_PECR_FPRG;\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write one half page directly with 32 different words */\r
- while(count < 32)\r
- {\r
- *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);\r
- count ++; \r
- }\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* if the write operation is completed, disable the PROG and FPRG bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
- }\r
-\r
- SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs 2 half page in program memory in parallel.\r
- * @param Address1: specifies the first address to be written in the first bank \r
- * (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.\r
- * @param pBuffer1: pointer to the buffer containing the data to be written \r
- * to the first half page in the first bank.\r
- * @param Address2: specifies the second address to be written in the second bank\r
- * (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.\r
- * @param pBuffer2: pointer to the buffer containing the data to be written \r
- * to the second half page in the second bank.\r
- * @note This function can be used only for STM32L1XX_HD density devices.\r
- * @note To correctly run this function, the FLASH_Unlock() function\r
- * must be called before.\r
- * Call the FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation).\r
- * @note Half page write is possible only from SRAM.\r
- * @note If there are more than 32 words to write, after 32 words another \r
- * Half Page programming operation starts and has to be finished.\r
- * @note A half page is written to the program memory only if the first \r
- * address to load is the start address of a half page (multiple of 128 \r
- * bytes) and the 31 remaining words to load are in the same half page.\r
- * @note During the Program memory half page write all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.).\r
- * @note If a PGAERR is set during a Program memory half page write, the \r
- * complete write operation is aborted. Software should then reset the \r
- * FPRG and PROG/DATA bits and restart the write operation from the \r
- * beginning.\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)\r
-{\r
- uint32_t count = 0; \r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
- This bit prevents the interruption of multicycle instructions and therefore \r
- will increase the interrupt latency. of Cortex-M3. */\r
- SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
-\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to program the new \r
- half page */\r
- FLASH->PECR |= FLASH_PECR_PARALLBANK;\r
- FLASH->PECR |= FLASH_PECR_FPRG;\r
- FLASH->PECR |= FLASH_PECR_PROG;\r
- \r
- /* Write the first half page directly with 32 different words */\r
- while(count < 32)\r
- {\r
- *(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++);\r
- count ++; \r
- }\r
- count = 0;\r
- /* Write the second half page directly with 32 different words */\r
- while(count < 32)\r
- {\r
- *(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++);\r
- count ++; \r
- }\r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);\r
- }\r
-\r
- SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Group3\r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Erase a double word in data memory.\r
- * @param Address: specifies the address to be erased.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @note Data memory double word erase is possible only from SRAM.\r
- * @note A double word is erased to the data memory only if the first address \r
- * to load is the start address of a double word (multiple of 8 bytes).\r
- * @note During the Data memory double word erase, all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-\r
-__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
- This bit prevents the interruption of multicycle instructions and therefore \r
- will increase the interrupt latency. of Cortex-M3. */\r
- SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to erase the next double word */\r
- /* Set the ERASE bit */\r
- FLASH->PECR |= FLASH_PECR_ERASE;\r
-\r
- /* Set DATA bit */\r
- FLASH->PECR |= FLASH_PECR_DATA;\r
- \r
- /* Write 00000000h to the 2 words to erase */\r
- *(__IO uint32_t *)Address = 0x00000000;\r
- Address += 4;\r
- *(__IO uint32_t *)Address = 0x00000000;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* If the erase operation is completed, disable the ERASE and DATA bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);\r
- } \r
- \r
- SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write a double word in data memory without erase.\r
- * @param Address: specifies the address to be written.\r
- * @param Data: specifies the data to be written.\r
- * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
- * must be called before.\r
- * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
- * and Flash program erase control register access(recommended to protect \r
- * the DATA_EEPROM against possible unwanted operation).\r
- * @note Data memory double word write is possible only from SRAM.\r
- * @note A data memory double word is written to the data memory only if the \r
- * first address to load is the start address of a double word (multiple \r
- * of double word).\r
- * @note During the Data memory double word write, all read operations are \r
- * forbidden (this includes DMA read operations and debugger read \r
- * operations such as breakpoints, periodic updates, etc.).\r
- * @retval FLASH Status: The returned value can be: \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */ \r
-__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
- This bit prevents the interruption of multicycle instructions and therefore \r
- will increase the interrupt latency. of Cortex-M3. */\r
- SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* If the previous operation is completed, proceed to program the new data*/\r
- FLASH->PECR |= FLASH_PECR_FPRG;\r
- FLASH->PECR |= FLASH_PECR_DATA;\r
- \r
- /* Write the 2 words */ \r
- *(__IO uint32_t *)Address = (uint32_t) Data;\r
- Address += 4;\r
- *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
- \r
- /* Wait for last operation to be completed */\r
- status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
- \r
- /* If the write operation is completed, disable the FPRG and DATA bits */\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
- FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); \r
- }\r
- \r
- SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
- \r
- /* Return the Write Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-static __RAM_FUNC GetStatus(void)\r
-{\r
- FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- FLASHstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
- { \r
- FLASHstatus = FLASH_ERROR_WRP;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)\r
- {\r
- FLASHstatus = FLASH_ERROR_PROGRAM; \r
- }\r
- else\r
- {\r
- FLASHstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the FLASH Status */\r
- return FLASHstatus;\r
-}\r
-\r
-/**\r
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
- * @param Timeout: FLASH programming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
- * FLASH_TIMEOUT.\r
- */\r
-static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- __IO FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the FLASH Status */\r
- status = GetStatus();\r
- \r
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = GetStatus();\r
- Timeout--;\r
- }\r
- \r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-#if defined ( __TASKING__ )\r
-#pragma section_code_init restore\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- /**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_fsmc.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the FSMC peripheral:\r
- * + Initialization \r
- * + Interrupts and flags management\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_fsmc.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC \r
- * @brief FSMC driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup FSMC_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Group1 NOR/SRAM Controller functions\r
- * @brief NOR/SRAM Controller functions \r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### NOR-SRAM Controller functions #####\r
- ==============================================================================\r
- [..] The following sequence should be followed to configure the FSMC to \r
- interface with SRAM, PSRAM, NOR or OneNAND memory connected to the \r
- NOR/SRAM Bank: \r
- (#) Enable the clock for the FSMC and associated GPIOs using the following \r
- functions: \r
- (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); \r
- (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); \r
- (#) FSMC pins configuration \r
- (++) Connect the involved FSMC pins to AF12 using the following function \r
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);\r
- (++) Configure these FSMC pins in alternate function mode by calling the\r
- function GPIO_Init();\r
- (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: \r
- FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the \r
- FSMC_NORSRAMInitStructure variable with the allowed values of the \r
- structure member.\r
- (#) Initialize the NOR/SRAM Controller by calling the function \r
- FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); \r
- (#) Then enable the NOR/SRAM Bank, for example: \r
- FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); \r
- (#) At this stage you can read/write from/to the memory connected to the \r
- NOR/SRAM Bank.\r
- \r
-@endverbatim\r
-\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
- * reset values.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- \r
- /* FSMC_Bank1_NORSRAM1 */\r
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
- }\r
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
- else\r
- { \r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
- }\r
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
- * parameters in the FSMC_NORSRAMInitStruct.\r
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
- * structure that contains the configuration information for \r
- * the FSMC NOR/SRAM specified Banks. \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
- assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
- \r
- /* Bank1 NOR/SRAM control register configuration */ \r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
-\r
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;\r
- }\r
- \r
- /* Bank1 NOR/SRAM timing register configuration */\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
- \r
- \r
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
- {\r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
- }\r
- else\r
- {\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Reset NOR/SRAM Init structure parameters values */\r
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_i2c.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Inter-integrated circuit (I2C)\r
- * + Initialization and Configuration\r
- * + Data transfers\r
- * + PEC management\r
- * + DMA transfers management\r
- * + Interrupts, events and flags management \r
- * \r
- * @verbatim\r
- * \r
- * ============================================================================\r
- * ##### How to use this driver #####\r
- * ============================================================================\r
- [..]\r
- (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
- function for I2C1 or I2C2.\r
- (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
- RCC_AHBPeriphClockCmd() function. \r
- (#) Peripherals alternate function: \r
- (++) Connect the pin to the desired peripherals' Alternate \r
- Function (AF) using GPIO_PinAFConfig() function.\r
- (++) Configure the desired pin in alternate function by:\r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
- (++) Select the type, pull-up/pull-down and output speed via \r
- GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
- (++) Call GPIO_Init() function.\r
- (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r
- Address using the I2C_Init() function.\r
- (#) Optionally you can enable/configure the following parameters without\r
- re-initialization (i.e there is no need to call again I2C_Init() function):\r
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.\r
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.\r
- (++) Enable the general call using the I2C_GeneralCallCmd() function.\r
- (++) Enable the clock stretching using I2C_StretchClockCmd() function.\r
- (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r
- function.\r
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function.\r
- (++) For SMBus Mode: \r
- (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function.\r
- (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function.\r
- (#) Enable the NVIC and the corresponding interrupt using the function\r
- I2C_ITConfig() if you need to use interrupt mode.\r
- (#) When using the DMA mode \r
- (++) Configure the DMA using DMA_Init() function.\r
- (++) Active the needed channel Request using I2C_DMACmd() or\r
- I2C_DMALastTransferCmd() function.\r
- (#) Enable the I2C using the I2C_Cmd() function.\r
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
- transfers. \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_i2c.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C \r
- * @brief I2C driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */\r
-#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */\r
-#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_DeInit(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- if (I2Cx == I2C1)\r
- {\r
- /* Enable I2C1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
- /* Release I2C1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
- }\r
- else\r
- {\r
- /* Enable I2C2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
- /* Release I2C2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the I2Cx peripheral according to the specified \r
- * parameters in the I2C_InitStruct.\r
- * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency \r
- * (I2C peripheral input clock) must be a multiple of 10 MHz. \r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
- * contains the configuration information for the specified I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, freqrange = 0;\r
- uint16_t result = 0x04;\r
- uint32_t pclk1 = 8000000;\r
- RCC_ClocksTypeDef rcc_clocks;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
-\r
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
- /* Get the I2Cx CR2 value */\r
- tmpreg = I2Cx->CR2;\r
- /* Clear frequency FREQ[5:0] bits */\r
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r
- /* Get pclk1 frequency value */\r
- RCC_GetClocksFreq(&rcc_clocks);\r
- pclk1 = rcc_clocks.PCLK1_Frequency;\r
- /* Set frequency bits depending on pclk1 value */\r
- freqrange = (uint16_t)(pclk1 / 1000000);\r
- tmpreg |= freqrange;\r
- /* Write to I2Cx CR2 */\r
- I2Cx->CR2 = tmpreg;\r
-\r
-/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
- /* Disable the selected I2C peripheral to configure TRISE */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
- /* Reset tmpreg value */\r
- /* Clear F/S, DUTY and CCR[11:0] bits */\r
- tmpreg = 0;\r
-\r
- /* Configure speed in standard mode */\r
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
- {\r
- /* Standard mode speed calculate */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
- /* Test if CCR value is under 0x4*/\r
- if (result < 0x04)\r
- {\r
- /* Set minimum allowed value */\r
- result = 0x04; \r
- }\r
- /* Set speed value for standard mode */\r
- tmpreg |= result; \r
- /* Set Maximum Rise Time for standard mode */\r
- I2Cx->TRISE = freqrange + 1; \r
- }\r
- /* Configure speed in fast mode */\r
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r
- input clock) must be a multiple of 10 MHz */\r
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
- {\r
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
- }\r
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
- /* Set DUTY bit */\r
- result |= I2C_DutyCycle_16_9;\r
- }\r
-\r
- /* Test if CCR value is under 0x1*/\r
- if ((result & I2C_CCR_CCR) == 0)\r
- {\r
- /* Set minimum allowed value */\r
- result |= (uint16_t)0x0001; \r
- }\r
- /* Set speed value and set F/S bit for fast mode */\r
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r
- /* Set Maximum Rise Time for fast mode */\r
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
- }\r
-\r
- /* Write to I2Cx CCR */\r
- I2Cx->CCR = tmpreg;\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= I2C_CR1_PE;\r
-\r
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
- /* Get the I2Cx CR1 value */\r
- tmpreg = I2Cx->CR1;\r
- /* Clear ACK, SMBTYPE and SMBUS bits */\r
- tmpreg &= CR1_CLEAR_MASK;\r
- /* Configure I2Cx: mode and acknowledgement */\r
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
- /* Set ACK bit according to I2C_Ack value */\r
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
- /* Write to I2Cx CR1 */\r
- I2Cx->CR1 = tmpreg;\r
-\r
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
- /* Set I2Cx Own Address1 and acknowledged address */\r
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
-}\r
-\r
-/**\r
- * @brief Fills each I2C_InitStruct member with its default value.\r
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
-/*---------------- Reset I2C init structure parameters values ----------------*/\r
- /* initialize the I2C_ClockSpeed member */\r
- I2C_InitStruct->I2C_ClockSpeed = 5000;\r
- /* Initialize the I2C_Mode member */\r
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
- /* Initialize the I2C_DutyCycle member */\r
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
- /* Initialize the I2C_OwnAddress1 member */\r
- I2C_InitStruct->I2C_OwnAddress1 = 0;\r
- /* Initialize the I2C_Ack member */\r
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
- /* Initialize the I2C_AcknowledgedAddress member */\r
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= I2C_CR1_PE;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C peripheral */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication START condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C START condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a START condition */\r
- I2Cx->CR1 |= I2C_CR1_START;\r
- }\r
- else\r
- {\r
- /* Disable the START condition generation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication STOP condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C STOP condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a STOP condition */\r
- I2Cx->CR1 |= I2C_CR1_STOP;\r
- }\r
- else\r
- {\r
- /* Disable the STOP condition generation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C acknowledge feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C Acknowledgement.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the acknowledgement */\r
- I2Cx->CR1 |= I2C_CR1_ACK;\r
- }\r
- else\r
- {\r
- /* Disable the acknowledgement */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the specified I2C own address2.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the 7bit I2C own address2.\r
- * @retval None.\r
- */\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
-{\r
- uint16_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Get the old register value */\r
- tmpreg = I2Cx->OAR2;\r
-\r
- /* Reset I2Cx Own address2 bit [7:1] */\r
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r
-\r
- /* Set I2Cx Own address2 */\r
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
-\r
- /* Store the new register value */\r
- I2Cx->OAR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C dual addressing mode.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C dual addressing mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable dual addressing mode */\r
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r
- }\r
- else\r
- {\r
- /* Disable dual addressing mode */\r
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C general call feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C General call.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable generall call */\r
- I2Cx->CR1 |= I2C_CR1_ENGC;\r
- }\r
- else\r
- {\r
- /* Disable generall call */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C software reset.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C software reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Peripheral under reset */\r
- I2Cx->CR1 |= I2C_CR1_SWRST;\r
- }\r
- else\r
- {\r
- /* Peripheral not under reset */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
- * @retval None\r
- */\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
- {\r
- /* Drive the SMBusAlert pin Low */\r
- I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
- }\r
- else\r
- {\r
- /* Drive the SMBusAlert pin High */\r
- I2Cx->CR1 &= I2C_SMBusAlert_High;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C ARP.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx ARP. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C ARP */\r
- I2Cx->CR1 |= I2C_CR1_ENARP;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C ARP */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C Clock stretching.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx Clock stretching.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState == DISABLE)\r
- {\r
- /* Enable the selected I2C Clock stretching */\r
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C Clock stretching */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C fast mode duty cycle.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
- * @retval None\r
- */\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
- {\r
- /* I2C fast mode Tlow/Thigh=2 */\r
- I2Cx->CCR &= I2C_DutyCycle_2;\r
- }\r
- else\r
- {\r
- /* I2C fast mode Tlow/Thigh=16/9 */\r
- I2Cx->CCR |= I2C_DutyCycle_16_9;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits the address byte to select the slave device.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the slave address which will be transmitted.\r
- * @param I2C_Direction: specifies whether the I2C device will be a\r
- * Transmitter or a Receiver. This parameter can be one of the following values:\r
- * @arg I2C_Direction_Transmitter: Transmitter mode\r
- * @arg I2C_Direction_Receiver: Receiver mode\r
- * @retval None.\r
- */\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
- /* Test on the direction to set/reset the read/write bit */\r
- if (I2C_Direction != I2C_Direction_Transmitter)\r
- {\r
- /* Set the address bit0 for read */\r
- Address |= I2C_OAR1_ADD0;\r
- }\r
- else\r
- {\r
- /* Reset the address bit0 for write */\r
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r
- }\r
- /* Send the address */\r
- I2Cx->DR = Address;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group2 Data transfers functions\r
- * @brief Data transfers functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Data transfers functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sends a data byte through the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Data: Byte to be transmitted.\r
- * @retval None\r
- */\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Write in the DR register the data to be sent */\r
- I2Cx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The value of the received data.\r
- */\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the data in the DR register */\r
- return (uint8_t)I2Cx->DR;\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C NACK position in master receiver mode.\r
- * This function is useful in I2C Master Receiver mode when the number\r
- * of data to be received is equal to 2. In this case, this function \r
- * should be called (with parameter I2C_NACKPosition_Next) before data \r
- * reception starts,as described in the 2-byte reception procedure \r
- * recommended in Reference Manual in Section: Master receiver.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_NACKPosition: specifies the NACK position. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last\r
- * received byte.\r
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last \r
- * received byte.\r
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig() \r
- * but is intended to be used in I2C mode while I2C_PECPositionConfig() \r
- * is intended to used in SMBUS mode.\r
- * \r
- * @retval None\r
- */\r
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));\r
- \r
- /* Check the input parameter */\r
- if (I2C_NACKPosition == I2C_NACKPosition_Next)\r
- {\r
- /* Next byte in shift register is the last received byte */\r
- I2Cx->CR1 |= I2C_NACKPosition_Next;\r
- }\r
- else\r
- {\r
- /* Current byte in shift register is the last received byte */\r
- I2Cx->CR1 &= I2C_NACKPosition_Current;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group3 PEC management functions\r
- * @brief PEC management functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### PEC management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C PEC transfer.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C PEC transmission.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC transmission */\r
- I2Cx->CR1 |= I2C_CR1_PEC;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC transmission */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C PEC position.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_PECPosition: specifies the PEC position. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()\r
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() \r
- * is intended to used in I2C mode.\r
- * @retval None\r
- */\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
- if (I2C_PECPosition == I2C_PECPosition_Next)\r
- {\r
- /* Next byte in shift register is PEC */\r
- I2Cx->CR1 |= I2C_PECPosition_Next;\r
- }\r
- else\r
- {\r
- /* Current byte in shift register is PEC */\r
- I2Cx->CR1 &= I2C_PECPosition_Current;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PEC value calculation of the transferred bytes.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx PEC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC calculation */\r
- I2Cx->CR1 |= I2C_CR1_ENPEC;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC calculation */\r
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the PEC value for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The PEC value.\r
- */\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the selected I2C PEC value */\r
- return ((I2Cx->SR2) >> 8);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group4 DMA transfers management functions\r
- * @brief DMA transfers management functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DMA transfers management functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to configure the I2C DMA channels \r
- requests.\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C DMA requests.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C DMA requests */\r
- I2Cx->CR2 |= I2C_CR2_DMAEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C DMA requests */\r
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Specifies that the next DMA transfer is the last one.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA last transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Next DMA transfer is the last transfer */\r
- I2Cx->CR2 |= I2C_CR2_LAST;\r
- }\r
- else\r
- {\r
- /* Next DMA transfer is not the last transfer */\r
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Group5 Interrupts events and flags management functions\r
- * @brief Interrupts, events and flags management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Interrupts, events and flags management functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to configure the I2C Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage \r
- the communication: Polling mode, Interrupt mode or DMA mode. \r
-\r
-\r
- ##### I2C State Monitoring Functions #####\r
- =============================================================================== \r
- [..]This I2C driver provides three different ways for I2C state monitoring\r
- depending on the application requirements and constraints:\r
- \r
- \r
- ***. Basic state monitoring (Using I2C_CheckEvent() function) ***\r
- -----------------------------------------------------------------\r
- [..]It compares the status registers (SR1 and SR2) content to a given event\r
- (can be the combination of one or more flags).\r
- It returns SUCCESS if the current status includes the given flags \r
- and returns ERROR if one or more flags are missing in the current status.\r
-\r
- (+) When to use\r
- (++) This function is suitable for most applications as well as for \r
- startup activity since the events are fully described in the product \r
- reference manual (RM0038).\r
- (++) It is also suitable for users who need to define their own events.\r
- (+) Limitations\r
- (++) If an error occurs (ie. error flags are set besides to the monitored \r
- flags), the I2C_CheckEvent() function may return SUCCESS despite \r
- the communication hold or corrupted real state. \r
- In this case, it is advised to use error interrupts to monitor \r
- the error events and handle them in the interrupt IRQ handler.\r
- -@@- For error management, it is advised to use the following functions:\r
- (+@@) I2C_ITConfig() to configure and enable the error interrupts \r
- (I2C_IT_ERR).\r
- (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
- Where x is the peripheral instance (I2C1, I2C2 ...).\r
- (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the\r
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
- (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
- and/or I2C_GenerateStop() in order to clear the error flag and source\r
- and return to correct communication status.\r
-\r
- *** Advanced state monitoring (Using the function I2C_GetLastEvent()) ***\r
- ------------------------------------------------------------------------- \r
- [..] Using the function I2C_GetLastEvent() which returns the image of both status \r
- registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- by 16 bits and concatenated to Status Register 1).\r
-\r
- (+) When to use\r
- (++) This function is suitable for the same applications above but it \r
- allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
- function.\r
- (++) The returned value could be compared to events already defined in \r
- the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
- This function is suitable when multiple flags are monitored at the \r
- same time.\r
- (++) At the opposite of I2C_CheckEvent() function, this function allows \r
- user to choose when an event is accepted (when all events flags are \r
- set and no other flags are set or just when the needed flags are set \r
- like I2C_CheckEvent() function.\r
-\r
- (+) Limitations\r
- (++) User may need to define his own events.\r
- (++) Same remark concerning the error management is applicable for this \r
- function if user decides to check only regular communication flags \r
- (and ignores error flags).\r
- \r
- \r
- *** Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ***\r
- ----------------------------------------------------------------------------\r
- [..] Using the function I2C_GetFlagStatus() which simply returns the status of \r
- one single flag (ie. I2C_FLAG_RXNE ...).\r
- (+) When to use\r
- (++) This function could be used for specific applications or in debug \r
- phase.\r
- (++) It is suitable when only one flag checking is needed (most I2C \r
- events are monitored through multiple flags).\r
- (+) Limitations: \r
- (++) When calling this function, the Status register is accessed. \r
- Some flags are cleared when the status register is accessed. \r
- So checking the status of one Flag, may clear other ones.\r
- (++) Function may need to be called twice or more in order to monitor \r
- one single event.\r
- \r
- [..] For detailed description of Events, please refer to section I2C_Events in \r
- stm32l1xx_i2c.h file.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Reads the specified I2C register and returns its value.\r
- * @param I2C_Register: specifies the register to read.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_Register_CR1: CR1 register.\r
- * @arg I2C_Register_CR2: CR2 register.\r
- * @arg I2C_Register_OAR1: OAR1 register.\r
- * @arg I2C_Register_OAR2: OAR2 register.\r
- * @arg I2C_Register_DR: DR register.\r
- * @arg I2C_Register_SR1: SR1 register.\r
- * @arg I2C_Register_SR2: SR2 register.\r
- * @arg I2C_Register_CCR: CCR register.\r
- * @arg I2C_Register_TRISE: TRISE register.\r
- * @retval The value of the read register.\r
- */\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_REGISTER(I2C_Register));\r
-\r
- tmp = (uint32_t) I2Cx;\r
- tmp += I2C_Register;\r
-\r
- /* Return the selected register value */\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C interrupts.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_BUF: Buffer interrupt mask\r
- * @arg I2C_IT_EVT: Event interrupt mask\r
- * @arg I2C_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified I2C interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C interrupts */\r
- I2Cx->CR2 |= I2C_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C interrupts */\r
- I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
- }\r
-}\r
-\r
-/*\r
- ===============================================================================\r
- 1. Basic state monitoring \r
- ===============================================================================\r
- */\r
-\r
-/**\r
- * @brief Checks whether the last I2Cx Event is equal to the one passed\r
- * as parameter.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_EVENT: specifies the event to be checked. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1\r
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1\r
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2\r
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3\r
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2\r
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4\r
- * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5\r
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6\r
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6\r
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2\r
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9\r
- * @note For detailed description of Events, please refer to section \r
- * I2C_Events in stm32l1xx_i2c.h file.\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: Last event is equal to the I2C_EVENT\r
- * - ERROR: Last event is different from the I2C_EVENT\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
- ErrorStatus status = ERROR;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_EVENT(I2C_EVENT));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_MASK;\r
-\r
- /* Check whether the last event contains the I2C_EVENT */\r
- if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
- {\r
- /* SUCCESS: last event is equal to I2C_EVENT */\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- /* ERROR: last event is different from I2C_EVENT */\r
- status = ERROR;\r
- }\r
- /* Return status */\r
- return status;\r
-}\r
-\r
-/*\r
- ===============================================================================\r
- 2. Advanced state monitoring \r
- =============================================================================== \r
- */\r
-\r
-/**\r
- * @brief Returns the last I2Cx Event.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * \r
- * @note For detailed description of Events, please refer to section \r
- * I2C_Events in stm32l1xx_i2c.h file.\r
- * \r
- * @retval The last event\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_MASK;\r
-\r
- /* Return status */\r
- return lastevent;\r
-}\r
-\r
-/*\r
- ===============================================================================\r
- 3. Flag-based state monitoring \r
- =============================================================================== \r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified I2C flag is set or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
- * @arg I2C_FLAG_BUSY: Bus busy flag\r
- * @arg I2C_FLAG_MSL: Master/Slave flag\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"\r
- * Address matched flag (Slave mode)"ENDAD"\r
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_FLAG (SET or RESET).\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- __IO uint32_t i2creg = 0, i2cxbase = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
-\r
- /* Get the I2Cx peripheral base address */\r
- i2cxbase = (uint32_t)I2Cx;\r
- \r
- /* Read flag register index */\r
- i2creg = I2C_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_FLAG &= FLAG_MASK;\r
- \r
- if(i2creg != 0)\r
- {\r
- /* Get the I2Cx SR1 register address */\r
- i2cxbase += 0x14;\r
- }\r
- else\r
- {\r
- /* Flag in I2Cx SR2 Register */\r
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
- /* Get the I2Cx SR2 register address */\r
- i2cxbase += 0x18;\r
- }\r
- \r
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
- {\r
- /* I2C_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the I2C_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx's pending flags.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * \r
-\r
- *@note STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- *@note ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
- * second byte of the address in DR register.\r
- *@note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- *@note ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- *@note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
- * register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_FLAG & FLAG_MASK;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified I2C interrupt has occurred or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_IT_PECERR: PEC error in reception flag\r
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure flag\r
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_IT_BERR: Bus error flag\r
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_IT_BTF: Byte transfer finished flag\r
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"\r
- * Address matched flag (Slave mode)"ENDAD"\r
- * @arg I2C_IT_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_IT (SET or RESET).\r
- */\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_IT(I2C_IT));\r
-\r
- /* Check if the interrupt source is enabled or not */\r
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_IT &= FLAG_MASK;\r
-\r
- /* Check the status of the specified I2C flag */\r
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* I2C_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the I2C_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx's interrupt pending bits.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
- * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure interrupt\r
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
- * @arg I2C_IT_BERR: Bus error interrupt\r
- * \r
-\r
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
- * byte of the address in I2C_DR register.\r
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * @note SB (Start Bit) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_DR register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_IT & FLAG_MASK;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
-\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_iwdg.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Independent watchdog (IWDG) peripheral: \r
- * + Prescaler and Counter configuration\r
- * + IWDG activation\r
- * + Flag management\r
- *\r
- * @verbatim \r
- * \r
- ============================================================================== \r
- ##### IWDG features #####\r
- ============================================================================== \r
- [..] The IWDG can be started by either software or hardware (configurable\r
- through option byte).\r
- \r
- [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
- thus stays active even if the main clock fails.\r
- Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
- (LSI cannot be disabled too), and the counter starts counting down from \r
- the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
- a system reset is generated.\r
- The IWDG counter should be reloaded at regular intervals to prevent\r
- an MCU reset.\r
- \r
- [..] The IWDG is implemented in the VDD voltage domain that is still functional\r
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r
- \r
- [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
- reset occurs.\r
- \r
- [..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s\r
- The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx\r
- devices provide the capability to measure the LSI frequency (LSI clock\r
- connected internally to TIM10 CH1 input capture). The measured value\r
- can be used to have an IWDG timeout with an acceptable accuracy. \r
- For more information, please refer to the STM32L1xx Reference manual.\r
- \r
- ##### How to use this driver ##### \r
- ============================================================================== \r
- [..]\r
- (#) Enable write access to IWDG_PR and IWDG_RLR registers using\r
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.\r
- (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.\r
-\r
- (#) Configure the IWDG counter value using IWDG_SetReload() function.\r
- This value will be loaded in the IWDG counter each time the counter\r
- is reloaded, then the IWDG will start counting down from this value.\r
-\r
- (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
- in software mode (no need to enable the LSI, it will be enabled\r
- by hardware).\r
-\r
- (#) Then the application program must reload the IWDG counter at regular\r
- intervals during normal operation to prevent an MCU reset, using\r
- IWDG_ReloadCounter() function.\r
-\r
- @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_iwdg.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG \r
- * @brief IWDG driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* ---------------------- IWDG registers bit mask ----------------------------*/\r
-/* KR register bit mask */\r
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup IWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
- * @brief Prescaler and Counter configuration functions\r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Prescaler and Counter configuration functions #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
- * @retval None\r
- */\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
- IWDG->KR = IWDG_WriteAccess;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Prescaler value.\r
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
- * @retval None\r
- */\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
- IWDG->PR = IWDG_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Reload value.\r
- * @param Reload: specifies the IWDG Reload value.\r
- * This parameter must be a number between 0 and 0x0FFF.\r
- * @retval None\r
- */\r
-void IWDG_SetReload(uint16_t Reload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_RELOAD(Reload));\r
- IWDG->RLR = Reload;\r
-}\r
-\r
-/**\r
- * @brief Reloads IWDG counter with value defined in the reload register\r
- * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_ReloadCounter(void)\r
-{\r
- IWDG->KR = KR_KEY_RELOAD;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Group2 IWDG activation function\r
- * @brief IWDG activation function \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### IWDG activation function #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None.\r
- * @retval None.\r
- */\r
-void IWDG_Enable(void)\r
-{\r
- IWDG->KR = KR_KEY_ENABLE;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Group3 Flag management function \r
- * @brief Flag management function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Flag management function ##### \r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified IWDG flag is set or not.\r
- * @param IWDG_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
- * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
- * @retval The new state of IWDG_FLAG (SET or RESET).\r
- */\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_opamp.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following\r
- * functionalities of the operational amplifiers (opamp) peripheral:\r
- * + Initialization and configuration\r
- * + Calibration management\r
- * \r
- * @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..] The device integrates three independent rail-to-rail operational amplifiers\r
- OPAMP1, OPAMP2 and OPAMP3:\r
- (+) Internal connections to the ADC.\r
- (+) Internal connections to the DAC.\r
- (+) Internal connection to COMP1 (only OPAMP3).\r
- (+) Internal connection for unity gain (voltage follower) configuration.\r
- (+) Calibration capability.\r
- (+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).\r
- [..] \r
- (#) COMP AHB clock must be enabled to get write access\r
- to OPAMP registers using\r
- (#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)\r
- \r
- (#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)\r
- and OPAMPx_OUT in analog mode.\r
- \r
- (#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()\r
-\r
- (#) Enable the OPAMP peripheral using OPAMP_Cmd()\r
-\r
- -@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled\r
- and the ADC must use the OPAMP output channel number:\r
- (+@) OPAMP1 output is connected to ADC channel 3.\r
- (+@) OPAMP2 output is connected to ADC channel 8.\r
- (+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).\r
-\r
- * @endverbatim\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_opamp.h"\r
-\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup OPAMP \r
- * @brief OPAMP driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup OPAMP_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup OPAMP_Group1 Initialization and configuration\r
- * @brief Initialization and configuration\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Initialization and configuration #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Deinitialize the OPAMPs register to its default reset value.\r
- * @note At startup, OTR and LPOTR registers are set to factory programmed values.\r
- * @param None.\r
- * @retval None.\r
- */\r
-void OPAMP_DeInit(void)\r
-{\r
- /*!< Set OPAMP_CSR register to reset value */\r
- OPAMP->CSR = 0x00010101;\r
- /*!< Set OPAMP_OTR register to reset value */\r
- OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);\r
- /*!< Set OPAMP_LPOTR register to reset value */\r
- OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);\r
-}\r
-\r
-/**\r
- * @brief Close or Open the OPAMP switches.\r
- * @param OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.\r
- * This parameter can be any combinations of the following values:\r
- * @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to \r
- * OPAMP1 negative input (internal follower)\r
- * @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input\r
- * @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input\r
- * @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input\r
- * @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage\r
- * @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to \r
- * OPAMP2 negative input (internal follower)\r
- * @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input\r
- * @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input\r
- * @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input\r
- * @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input\r
- * @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage\r
- * @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to \r
- * OPAMP3 negative input (internal follower)\r
- * @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input\r
- * @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input\r
- * @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input\r
- * @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input\r
- *\r
- * @param NewState: New state of the OPAMP switch. \r
- * This parameter can be:\r
- * ENABLE to close the OPAMP switch\r
- * or DISABLE to open the OPAMP switch\r
- * @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.\r
- * @retval None\r
- */\r
-void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Close the selected switches */\r
- OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;\r
- }\r
- else\r
- {\r
- /* Open the selected switches */\r
- OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the OPAMP peripheral.\r
- * @param OPAMP_Selection: the selected OPAMP. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected\r
- * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected\r
- * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected\r
- * @param NewState: new state of the selected OPAMP peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected OPAMP */\r
- OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);\r
- }\r
- else\r
- {\r
- /* Disable the selected OPAMP */\r
- OPAMP->CSR |= (uint32_t) OPAMP_Selection;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enable or disable the low power mode for OPAMP peripheral.\r
- * @param OPAMP_Selection: the selected OPAMP. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Selection_OPAMP1: OPAMP1 selected\r
- * @arg OPAMP_Selection_OPAMP2: OPAMP2 selected\r
- * @arg OPAMP_Selection_OPAMP3: OPAMP3 selected\r
- * @param NewState: new low power state of the selected OPAMP peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the selected OPAMP in low power mode */\r
- OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);\r
- }\r
- else\r
- {\r
- /* Disable the low power mode for the selected OPAMP */\r
- OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Select the OPAMP power range.\r
- * @note The OPAMP power range selection must be performed while OPAMPs are powered down.\r
- * @param OPAMP_Range: the selected OPAMP power range. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).\r
- * @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).\r
- * @retval None\r
- */\r
-void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));\r
-\r
- /* Reset the OPAMP range bit */\r
- OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));\r
-\r
- /* Select the OPAMP power range */\r
- OPAMP->CSR |= OPAMP_PowerRange;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup OPAMP_Group2 Calibration functions\r
- * @brief Calibration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Calibration functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Select the trimming mode.\r
- * @param OffsetTrimming: the selected offset trimming mode. \r
- * This parameter can be one of the following values:\r
- * @arg OffsetTrimming_Factory: factory trimming values are used for offset\r
- * calibration.\r
- * @arg OffsetTrimming_User: user trimming values are used for offset\r
- * calibration.\r
- * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()\r
- * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust \r
- * trimming value.\r
- * @retval None\r
- */\r
-void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));\r
-\r
- /* Reset the OPAMP_OTR range bit */\r
- OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));\r
-\r
- /* Select the OPAMP offset trimming */\r
- OPAMP->CSR |= OPAMP_Trimming;\r
-\r
-}\r
-\r
-/**\r
- * @brief Configure the trimming value of OPAMPs in normal mode.\r
- * @param OPAMP_Selection: the selected OPAMP. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.\r
- * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.\r
- * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.\r
- * @param OPAMP_Input: the selected OPAMP input. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.\r
- * @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.\r
- * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower\r
- * or equal to 0x0000001F. \r
- * @retval None\r
- */\r
-void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
- assert_param(IS_OPAMP_INPUT(OPAMP_Input));\r
- assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));\r
-\r
- /* Get the OPAMP_OTR value */\r
- tmpreg = OPAMP->OTR;\r
-\r
- if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= OPAMP_Input;\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP1 PMOS input */\r
- tmpreg &= (0xFFFFFFE0);\r
- /* Set the new trimming value corresponding to OPAMP1 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP1 NMOS input */\r
- tmpreg &= (0xFFFFFC1F);\r
- /* Set the new trimming value corresponding to OPAMP1 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<5);\r
- }\r
- }\r
- else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= (uint32_t)(OPAMP_Input<<8);\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP2 PMOS input */\r
- tmpreg &= (0xFFFF83FF);\r
- /* Set the new trimming value corresponding to OPAMP2 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<10);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP2 NMOS input */\r
- tmpreg &= (0xFFF07FFF);\r
- /* Set the new trimming value corresponding to OPAMP2 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<15);\r
- }\r
- }\r
- else\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= (uint32_t)(OPAMP_Input<<16);\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP3 PMOS input */\r
- tmpreg &= (0xFE0FFFFF);\r
- /* Set the new trimming value corresponding to OPAMP3 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<20);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP3 NMOS input */\r
- tmpreg &= (0xC1FFFFFF);\r
- /* Set the new trimming value corresponding to OPAMP3 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<25);\r
- }\r
- }\r
-\r
- /* Set the OPAMP_OTR register */\r
- OPAMP->OTR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configure the trimming value of OPAMPs in low power mode.\r
- * @param OPAMP_Selection: the selected OPAMP. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.\r
- * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.\r
- * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.\r
- * @param OPAMP_Input: the selected OPAMP input. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.\r
- * @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.\r
- * @param OPAMP_TrimValue: the trimming value. \r
- * This parameter can be any value lower or equal to 0x0000001F. \r
- * @retval None\r
- */\r
-void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
- assert_param(IS_OPAMP_INPUT(OPAMP_Input));\r
- assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));\r
-\r
- /* Get the OPAMP_LPOTR value */\r
- tmpreg = OPAMP->LPOTR;\r
-\r
- if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= OPAMP_Input;\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP1 PMOS input */\r
- tmpreg &= (0xFFFFFFE0);\r
- /* Set the new trimming value corresponding to OPAMP1 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP1 NMOS input */\r
- tmpreg &= (0xFFFFFC1F);\r
- /* Set the new trimming value corresponding to OPAMP1 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<5);\r
- }\r
- }\r
- else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= (uint32_t)(OPAMP_Input<<8);\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP2 PMOS input */\r
- tmpreg &= (0xFFFF83FF);\r
- /* Set the new trimming value corresponding to OPAMP2 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<10);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP2 NMOS input */\r
- tmpreg &= (0xFFF07FFF);\r
- /* Set the new trimming value corresponding to OPAMP2 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<15);\r
- }\r
- }\r
- else\r
- {\r
- /* Reset the OPAMP inputs selection */\r
- tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);\r
- /* Select the OPAMP input */\r
- tmpreg |= (uint32_t)(OPAMP_Input<<16);\r
-\r
- if(OPAMP_Input == OPAMP_Input_PMOS)\r
- {\r
- /* Reset the trimming value corresponding to OPAMP3 PMOS input */\r
- tmpreg &= (0xFE0FFFFF);\r
- /* Set the new trimming value corresponding to OPAMP3 PMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<20);\r
- }\r
- else\r
- {\r
- /* Reset the trimming value corresponding to OPAMP3 NMOS input */\r
- tmpreg &= (0xC1FFFFFF);\r
- /* Set the new trimming value corresponding to OPAMP3 NMOS input */\r
- tmpreg |= (OPAMP_TrimValue<<25);\r
- }\r
- }\r
-\r
- /* Set the OPAMP_LPOTR register */\r
- OPAMP->LPOTR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified OPAMP calibration flag is set or not.\r
- * @note User should wait until calibration flag change the value when changing\r
- * the trimming value.\r
- * @param OPAMP_Selection: the selected OPAMP. \r
- * This parameter can be one of the following values:\r
- * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.\r
- * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.\r
- * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.\r
- * @retval The new state of the OPAMP calibration flag (SET or RESET).\r
- */\r
-FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameter */\r
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
- \r
- /* Get the CSR register value */\r
- tmpreg = OPAMP->CSR;\r
-\r
- /* Check if OPAMP1 is selected */\r
- if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
- {\r
- /* Check OPAMP1 CAL bit status */\r
- if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- /* Check if OPAMP2 is selected */\r
- else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
- {\r
- /* Check OPAMP2 CAL bit status */\r
- if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- } \r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- /* Check OPAMP3 CAL bit status */\r
- if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
* @author MCD Application Team\r
* @version V1.1.1\r
* @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Reset and clock control (RCC) peripheral: \r
+ * @brief This file provides firmware functions to manage the following\r
+ * functionalities of the Reset and clock control (RCC) peripheral:\r
* + Internal/external clocks, PLL, CSS and MCO configuration\r
* + System, AHB and APB busses clocks configuration\r
* + Peripheral clocks configuration\r
===============================================================================\r
##### RCC specific features #####\r
===============================================================================\r
- [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
+ [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,\r
all peripherals are off except internal SRAM, Flash and JTAG.\r
(#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
all peripherals mapped on these busses are running at MSI speed.\r
- (#) The clock for all peripherals is switched off, except the SRAM and \r
+ (#) The clock for all peripherals is switched off, except the SRAM and\r
FLASH.\r
(#) All GPIOs are in input floating state, except the JTAG pins which\r
are assigned to be used for debug purpose.\r
derived from the System clock (ADC, RTC/LCD and IWDG)\r
\r
@endverbatim\r
- \r
+\r
******************************************************************************\r
* @attention\r
*\r
*\r
* http://www.st.com/software_license_agreement_liberty_v2\r
*\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
* See the License for the specific language governing permissions and\r
* limitations under the License.\r
* @{\r
*/\r
\r
-/** @defgroup RCC \r
+/** @defgroup RCC\r
* @brief RCC driver modules\r
* @{\r
- */ \r
+ */\r
\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
*/\r
\r
/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions\r
*\r
@verbatim\r
===============================================================================\r
##### Internal-external clocks, PLL, CSS and MCO configuration functions #####\r
===============================================================================\r
- [..] This section provide functions allowing to configure the internal/external \r
+ [..] This section provide functions allowing to configure the internal/external\r
clocks, PLL, CSS and MCO.\r
- (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly \r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly\r
or through the PLL as System clock source.\r
- (#) MSI (multi-speed internal), multispeed low power RC \r
+ (#) MSI (multi-speed internal), multispeed low power RC\r
(65.536 KHz to 4.194 MHz) MHz used as System clock source.\r
- (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG \r
+ (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG\r
and/or RTC clock source.\r
- (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used \r
- directly or through the PLL as System clock source. Can be used \r
+ (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used\r
+ directly or through the PLL as System clock source. Can be used\r
also as RTC clock source.\r
(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
(#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
- (#) CSS (Clock security system), once enable and if a HSE clock failure \r
- occurs (HSE used directly or through PLL as System clock source), \r
- the System clock is automatically switched to MSI and an interrupt \r
- is generated if enabled. \r
- The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
+ (#) CSS (Clock security system), once enable and if a HSE clock failure\r
+ occurs (HSE used directly or through PLL as System clock source),\r
+ the System clock is automatically switched to MSI and an interrupt\r
+ is generated if enabled.\r
+ The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)\r
exception vector.\r
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, \r
- HSE, PLL, LSI or LSE clock (through a configurable prescaler) on \r
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,\r
+ HSE, PLL, LSI or LSE clock (through a configurable prescaler) on\r
PA8 pin.\r
\r
@endverbatim\r
* @note All interrupts disabled\r
* @note However, this function doesn't modify the configuration of the\r
* @note Peripheral clocks\r
- * @note LSI, LSE and RTC clocks \r
+ * @note LSI, LSE and RTC clocks\r
* @param None\r
* @retval None\r
*/\r
void RCC_DeInit(void)\r
{\r
- \r
+\r
/* Set MSION bit */\r
RCC->CR |= (uint32_t)0x00000100;\r
\r
/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
RCC->CFGR &= (uint32_t)0x88FFC00C;\r
- \r
+\r
/* Reset HSION, HSEON, CSSON and PLLON bits */\r
RCC->CR &= (uint32_t)0xEEFEFFFE;\r
\r
* @note HSE state can not be changed if it is used directly or through the\r
* PLL as system clock. In this case, you have to select another source\r
* of the system clock then change the HSE state (ex. disable it).\r
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
* @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
* was previously enabled you have to enable it again after calling this\r
* function.\r
\r
/**\r
* @brief Waits for HSE start-up.\r
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
- * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if\r
+ * this flag is set, otherwise returns ERROR if the timeout is reached\r
* and this flag is not set. The timeout value is defined by the constant\r
* HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
- * on the HSE crystal used in your application. \r
+ * on the HSE crystal used in your application.\r
* @param None\r
* @retval An ErrorStatus enumeration value:\r
* - SUCCESS: HSE oscillator is stable and ready to use\r
__IO uint32_t StartUpCounter = 0;\r
ErrorStatus status = ERROR;\r
FlagStatus HSEStatus = RESET;\r
- \r
+\r
/* Wait till HSE is ready and if timeout is reached exit */\r
do\r
{\r
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
- StartUpCounter++; \r
+ StartUpCounter++;\r
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
- \r
+\r
if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
{\r
status = SUCCESS;\r
else\r
{\r
status = ERROR;\r
- } \r
+ }\r
return (status);\r
}\r
\r
* @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
* @note The calibration is used to compensate for the variations in voltage\r
* and temperature that influence the frequency of the internal MSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
+ * Refer to the Application Note AN3300 for more details on how to\r
* calibrate the MSI.\r
* @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
* This parameter must be a number between 0 and 0xFF.\r
*/\r
void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
{\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
\r
- *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
+ *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;\r
}\r
\r
/**\r
* @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
- * @note After restart from Reset or wakeup from STANDBY, the MSI clock is \r
+ * @note After restart from Reset or wakeup from STANDBY, the MSI clock is\r
* around 2.097 MHz. The MSI clock does not change after wake-up from\r
* STOP mode.\r
- * @note The MSI clock range can be modified on the fly. \r
+ * @note The MSI clock range can be modified on the fly.\r
* @param RCC_MSIRange: specifies the MSI Clock range.\r
* This parameter must be one of the following values:\r
* @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
* @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
* @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
* @arg RCC_MSIRange_6: MSI clock is around 4.194 MHz\r
- * \r
+ *\r
* @retval None\r
*/\r
void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
- \r
+\r
tmpreg = RCC->ICSCR;\r
- \r
+\r
/* Clear MSIRANGE[2:0] bits */\r
tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
- \r
+\r
/* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
tmpreg |= (uint32_t)RCC_MSIRange;\r
\r
* It is used (enabled by hardware) as system clock source after\r
* startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
* of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled). \r
+ * (if the Clock Security System CSS is enabled).\r
* @note MSI can not be stopped if it is used as system clock source.\r
* In this case, you have to select another source of the system\r
- * clock then stop the MSI. \r
+ * clock then stop the MSI.\r
* @note After enabling the MSI, the application software should wait on\r
* MSIRDY flag to be set indicating that MSI clock is stable and can\r
- * be used as system clock source. \r
+ * be used as system clock source.\r
* @param NewState: new state of the MSI.\r
* This parameter can be: ENABLE or DISABLE.\r
* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
- * clock cycles. \r
+ * clock cycles.\r
* @retval None\r
*/\r
void RCC_MSICmd(FunctionalState NewState)\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
}\r
\r
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
* @note The calibration is used to compensate for the variations in voltage\r
* and temperature that influence the frequency of the internal HSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
+ * Refer to the Application Note AN3300 for more details on how to\r
* calibrate the HSI.\r
* @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
* This parameter must be a number between 0 and 0x1F.\r
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
- \r
+\r
tmpreg = RCC->ICSCR;\r
- \r
+\r
/* Clear HSITRIM[4:0] bits */\r
tmpreg &= ~RCC_ICSCR_HSITRIM;\r
- \r
+\r
/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
\r
\r
/**\r
* @brief Enables or disables the Internal High Speed oscillator (HSI).\r
- * @note After enabling the HSI, the application software should wait on \r
+ * @note After enabling the HSI, the application software should wait on\r
* HSIRDY flag to be set indicating that HSI clock is stable and can\r
* be used to clock the PLL and/or system clock.\r
* @note HSI can not be stopped if it is used directly or through the PLL\r
- * as system clock. In this case, you have to select another source \r
+ * as system clock. In this case, you have to select another source\r
* of the system clock then stop the HSI.\r
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
* @param NewState: new state of the HSI.\r
* This parameter can be: ENABLE or DISABLE.\r
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
- * clock cycles. \r
+ * clock cycles.\r
* @retval None\r
*/\r
void RCC_HSICmd(FunctionalState NewState)\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
}\r
\r
/**\r
* @brief Configures the External Low Speed oscillator (LSE).\r
* @note As the LSE is in the RTC domain and write access is denied to this\r
- * domain after reset, you have to enable write access using \r
+ * domain after reset, you have to enable write access using\r
* PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
- * (to be done once after reset). \r
+ * (to be done once after reset).\r
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
* software should wait on LSERDY flag to be set indicating that LSE clock\r
* is stable and can be used to clock the RTC.\r
{\r
/* Check the parameters */\r
assert_param(IS_RCC_LSE(RCC_LSE));\r
- \r
+\r
/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
*(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
\r
/* Set the new LSE configuration -------------------------------------------*/\r
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;\r
}\r
\r
/**\r
- * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
- * @note After enabling the LSI, the application software should wait on \r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on\r
* LSIRDY flag to be set indicating that LSI clock is stable and can\r
* be used to clock the IWDG and/or the RTC.\r
- * @note LSI can not be disabled if the IWDG is running. \r
+ * @note LSI can not be disabled if the IWDG is running.\r
* @param NewState: new state of the LSI.\r
* This parameter can be: ENABLE or DISABLE.\r
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
- * clock cycles. \r
+ * clock cycles.\r
* @retval None\r
*/\r
void RCC_LSICmd(FunctionalState NewState)\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
}\r
\r
/**\r
* @brief Configures the PLL clock source and multiplication factor.\r
* @note This function must be used only when the PLL is disabled.\r
- * \r
+ *\r
* @param RCC_PLLSource: specifies the PLL entry clock source.\r
* This parameter can be one of the following values:\r
* @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
* @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
* PLL source).\r
- * \r
+ *\r
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
* This parameter can be:\r
* @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
* @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
* @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
* @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
- * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
+ * @arg RCC_PLLMul_16: PLL clock source multiplied by 16\r
* @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
* @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
* @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
* - 48 MHz as PLLVCO when the product is in range 2\r
* - 24 MHz when the product is in range 3\r
* @note When using the USB the PLLVCO should be 96MHz\r
- * \r
+ *\r
* @param RCC_PLLDiv: specifies the PLL division factor.\r
* This parameter can be:\r
- * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
- * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
- * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
+ * @arg RCC_PLLDiv_2: PLL Clock output divided by 2\r
+ * @arg RCC_PLLDiv_3: PLL Clock output divided by 3\r
+ * @arg RCC_PLLDiv_4: PLL Clock output divided by 4\r
* @note The application software must set correctly the output division to avoid\r
* exceeding 32 MHz as SYSCLK.\r
- * \r
+ *\r
* @retval None\r
*/\r
void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
- \r
+\r
*(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
}\r
\r
/**\r
* @brief Enables or disables the PLL.\r
- * @note After enabling the PLL, the application software should wait on \r
+ * @note After enabling the PLL, the application software should wait on\r
* PLLRDY flag to be set indicating that PLL clock is stable and can\r
* be used as system clock source.\r
* @note The PLL can not be disabled if it is used as system clock source\r
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
+ * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.\r
* @param NewState: new state of the PLL.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
}\r
\r
* @note If a failure is detected on the HSE oscillator clock, this oscillator\r
* is automatically disabled and an interrupt is generated to inform the\r
* software about the failure (Clock Security System Interrupt, CSSI),\r
- * allowing the MCU to perform rescue operations. The CSSI is linked to \r
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to\r
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.\r
* @param NewState: new state of the Clock Security System.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
}\r
\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)NewState;\r
}\r
\r
/**\r
* @brief Selects the clock source to output on MCO pin (PA8).\r
- * @note PA8 should be configured in alternate function mode. \r
+ * @note PA8 should be configured in alternate function mode.\r
* @param RCC_MCOSource: specifies the clock source to output.\r
* This parameter can be one of the following values:\r
* @arg RCC_MCOSource_NoClock: No clock selected\r
* @arg RCC_MCOSource_SYSCLK: System clock selected\r
* @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
- * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
+ * @arg RCC_MCOSource_MSI: MSI oscillator clock selected\r
* @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
* @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
* @arg RCC_MCOSource_LSI: LSI clock selected\r
- * @arg RCC_MCOSource_LSE: LSE clock selected \r
+ * @arg RCC_MCOSource_LSE: LSE clock selected\r
* @param RCC_MCODiv: specifies the MCO prescaler.\r
- * This parameter can be one of the following values: \r
- * @arg RCC_MCODiv_1: no division applied to MCO clock \r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODiv_1: no division applied to MCO clock\r
* @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
* @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
* @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
- * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
+ * @arg RCC_MCODiv_16: division by 16 applied to MCO clock\r
* @retval None\r
*/\r
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
/* Check the parameters */\r
assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
- \r
+\r
/* Select MCO clock source and prescaler */\r
- *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv;\r
}\r
\r
/**\r
===============================================================================\r
##### System, AHB and APB busses clocks configuration functions #####\r
===============================================================================\r
- [..] This section provide functions allowing to configure the System, AHB, \r
+ [..] This section provide functions allowing to configure the System, AHB,\r
APB1 and APB2 busses clocks.\r
- (#) Several clock sources can be used to drive the System clock (SYSCLK): \r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK):\r
MSI, HSI, HSE and PLL.\r
- The AHB clock (HCLK) is derived from System clock through configurable \r
- prescaler and used to clock the CPU, memory and peripherals mapped \r
- on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are \r
- derived from AHB clock through configurable prescalers and used to \r
- clock the peripherals mapped on these busses. You can use \r
- "RCC_GetClocksFreq()" function to retrieve the frequencies of these \r
- clocks. \r
-\r
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) \r
+ The AHB clock (HCLK) is derived from System clock through configurable\r
+ prescaler and used to clock the CPU, memory and peripherals mapped\r
+ on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are\r
+ derived from AHB clock through configurable prescalers and used to\r
+ clock the peripherals mapped on these busses. You can use\r
+ "RCC_GetClocksFreq()" function to retrieve the frequencies of these\r
+ clocks.\r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK)\r
except:\r
(+@) The USB 48 MHz clock which is derived from the PLL VCO clock.\r
- (+@) The ADC clock which is always the HSI clock. A divider by 1, 2 \r
- or 4 allows to adapt the clock frequency to the device operating \r
- conditions. \r
- (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz \r
+ (+@) The ADC clock which is always the HSI clock. A divider by 1, 2\r
+ or 4 allows to adapt the clock frequency to the device operating\r
+ conditions.\r
+ (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz\r
HSE_RTC (HSE divided by a programmable prescaler).\r
- The System clock (SYSCLK) frequency must be higher or equal to \r
+ The System clock (SYSCLK) frequency must be higher or equal to\r
the RTC/LCD clock frequency.\r
(+@) IWDG clock which is always the LSI clock.\r
- \r
+\r
(#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
- Depending on the device voltage range, the maximum frequency should \r
+ Depending on the device voltage range, the maximum frequency should\r
be adapted accordingly:\r
\r
+----------------------------------------------------------------+\r
|1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+----------------------------------------------------------------+\r
\r
- (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS, \r
+ (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS,\r
Flash 32-bit access is enabled and prefetch is disabled.\r
- [..] It is recommended to use the following software sequences to tune the \r
- number of wait states needed to access the Flash memory with the CPU \r
+ [..] It is recommended to use the following software sequences to tune the\r
+ number of wait states needed to access the Flash memory with the CPU\r
frequency (HCLK).\r
(+) Increasing the CPU frequency (in the same voltage range)\r
- (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" \r
+ (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)"\r
function\r
(+) Check that 64-bit access is taken into account by reading FLASH_ACR\r
- (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" \r
+ (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)"\r
function\r
- (+) Check that the new number of WS is taken into account by reading \r
+ (+) Check that the new number of WS is taken into account by reading\r
FLASH_ACR\r
(+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" \r
+ (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"\r
function\r
- (+) Check that the new CPU clock source is taken into account by reading \r
- the clock source status, using "RCC_GetSYSCLKSource()" function \r
+ (+) Check that the new CPU clock source is taken into account by reading\r
+ the clock source status, using "RCC_GetSYSCLKSource()" function\r
(+) Decreasing the CPU frequency (in the same voltage range)\r
(+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" \r
+ (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"\r
function\r
- (+) Check that the new CPU clock source is taken into account by reading \r
+ (+) Check that the new CPU clock source is taken into account by reading\r
the clock source status, using "RCC_GetSYSCLKSource()" function\r
(+) Program the new number of WS, using "FLASH_SetLatency()" function\r
- (+) Check that the new number of WS is taken into account by reading \r
+ (+) Check that the new number of WS is taken into account by reading\r
FLASH_ACR\r
- (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" \r
+ (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)"\r
function\r
(+) Check that 32-bit access is taken into account by reading FLASH_ACR\r
\r
* of failure of the HSE used directly or indirectly as system clock\r
* (if the Clock Security System CSS is enabled).\r
* @note A switch from one clock source to another occurs only if the target\r
- * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * clock source is ready (clock stable after startup delay or PLL locked).\r
* If a clock source which is not yet ready is selected, the switch will\r
- * occur when the clock source will be ready. \r
+ * occur when the clock source will be ready.\r
* You can use RCC_GetSYSCLKSource() function to know which clock is\r
- * currently used as system clock source. \r
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
+ * currently used as system clock source.\r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source\r
* This parameter can be one of the following values:\r
* @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
- \r
+\r
tmpreg = RCC->CFGR;\r
- \r
+\r
/* Clear SW[1:0] bits */\r
tmpreg &= ~RCC_CFGR_SW;\r
- \r
+\r
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
tmpreg |= RCC_SYSCLKSource;\r
- \r
+\r
/* Store the new value */\r
RCC->CFGR = tmpreg;\r
}\r
/**\r
* @brief Returns the clock source used as system clock.\r
* @param None\r
- * @retval The clock source used as system clock. The returned value can be one \r
+ * @retval The clock source used as system clock. The returned value can be one\r
* of the following values:\r
* - 0x00: MSI used as system clock\r
- * - 0x04: HSI used as system clock \r
+ * - 0x04: HSI used as system clock\r
* - 0x08: HSE used as system clock\r
* - 0x0C: PLL used as system clock\r
*/\r
* these bits to ensure that the system frequency does not exceed the\r
* maximum allowed frequency (for more details refer to section above\r
* "CPU, AHB and APB busses clocks configuration functions")\r
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from\r
* the system clock (SYSCLK).\r
* This parameter can be one of the following values:\r
* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
- \r
+\r
tmpreg = RCC->CFGR;\r
- \r
+\r
/* Clear HPRE[3:0] bits */\r
tmpreg &= ~RCC_CFGR_HPRE;\r
- \r
+\r
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
tmpreg |= RCC_SYSCLK;\r
- \r
+\r
/* Store the new value */\r
RCC->CFGR = tmpreg;\r
}\r
\r
/**\r
* @brief Configures the Low Speed APB clock (PCLK1).\r
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from\r
* the AHB clock (HCLK).\r
* This parameter can be one of the following values:\r
* @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
+\r
tmpreg = RCC->CFGR;\r
- \r
+\r
/* Clear PPRE1[2:0] bits */\r
tmpreg &= ~RCC_CFGR_PPRE1;\r
- \r
+\r
/* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
tmpreg |= RCC_HCLK;\r
- \r
+\r
/* Store the new value */\r
RCC->CFGR = tmpreg;\r
}\r
\r
/**\r
* @brief Configures the High Speed APB clock (PCLK2).\r
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from\r
* the AHB clock (HCLK).\r
* This parameter can be one of the following values:\r
* @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
{\r
uint32_t tmpreg = 0;\r
- \r
+\r
/* Check the parameters */\r
assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
+\r
tmpreg = RCC->CFGR;\r
- \r
+\r
/* Clear PPRE2[2:0] bits */\r
tmpreg &= ~RCC_CFGR_PPRE2;\r
- \r
+\r
/* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
tmpreg |= RCC_HCLK << 3;\r
- \r
+\r
/* Store the new value */\r
RCC->CFGR = tmpreg;\r
}\r
* @note The frequency returned by this function is not the real frequency\r
* in the chip. It is calculated based on the predefined constant and\r
* the source selected by RCC_SYSCLKConfig():\r
- * \r
+ *\r
* @note If SYSCLK source is MSI, function returns values based on MSI\r
* Value as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
- * \r
+ *\r
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
- * \r
+ *\r
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
- * \r
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r
+ *\r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)\r
* or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
+ *\r
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
* 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
- * \r
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().\r
+ *\r
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
* 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
* frequency of the crystal used. Otherwise, this function may\r
* return wrong result.\r
- * \r
+ *\r
* - The result of this function could be not correct when using fractional\r
- * value for HSE crystal. \r
- * \r
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
- * the clocks frequencies. \r
- * \r
- * @note This function can be used by the user application to compute the \r
+ * value for HSE crystal.\r
+ *\r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
+ * the clocks frequencies.\r
+ *\r
+ * @note This function can be used by the user application to compute the\r
* baudrate for the communication peripherals or configure other parameters.\r
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\r
* must be called to update the structure's field. Otherwise, any\r
* configuration based on this function will be incorrect.\r
- * \r
+ *\r
* @retval None\r
*/\r
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
\r
/* Get SYSCLK source -------------------------------------------------------*/\r
tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
+\r
switch (tmp)\r
{\r
case 0x00: /* MSI used as system clock */\r
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
pllmul = PLLMulTable[(pllmul >> 18)];\r
plldiv = (plldiv >> 22) + 1;\r
- \r
+\r
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
\r
if (pllsource == 0x00)\r
/* Get HCLK prescaler */\r
tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
tmp = tmp >> 4;\r
- presc = APBAHBPrescTable[tmp]; \r
+ presc = APBAHBPrescTable[tmp];\r
/* HCLK clock frequency */\r
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
\r
*/\r
\r
/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
- * @brief Peripheral clocks configuration functions \r
+ * @brief Peripheral clocks configuration functions\r
*\r
@verbatim\r
===============================================================================\r
##### Peripheral clocks configuration functions #####\r
===============================================================================\r
- [..] This section provide functions allowing to configure the Peripheral clocks. \r
- (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC \r
+ [..] This section provide functions allowing to configure the Peripheral clocks.\r
+ (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC\r
(HSE divided by a programmable prescaler).\r
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are \r
- off except internal SRAM, Flash and JTAG. Before to start using a \r
- peripheral you have to enable its interface clock. You can do this \r
- using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and \r
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are\r
+ off except internal SRAM, Flash and JTAG. Before to start using a\r
+ peripheral you have to enable its interface clock. You can do this\r
+ using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and\r
RCC_APB1PeriphClockCmd() functions.\r
\r
- (#) To reset the peripherals configuration (to the default state after \r
- device reset) you can use RCC_AHBPeriphResetCmd(), \r
+ (#) To reset the peripherals configuration (to the default state after\r
+ device reset) you can use RCC_AHBPeriphResetCmd(),\r
RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.\r
- (#) To further reduce power consumption in SLEEP mode the peripheral \r
+ (#) To further reduce power consumption in SLEEP mode the peripheral\r
clocks can be disabled prior to executing the WFI or WFE instructions.\r
- You can do this using RCC_AHBPeriphClockLPModeCmd(), \r
- RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() \r
+ You can do this using RCC_AHBPeriphClockLPModeCmd(),\r
+ RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd()\r
functions.\r
\r
@endverbatim\r
* @note As the RTC clock configuration bits are in the RTC domain and write\r
* access is denied to this domain after reset, you have to enable write\r
* access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
- * the RTC clock source (to be done once after reset). \r
+ * the RTC clock source (to be done once after reset).\r
* @note Once the RTC clock is configured it can't be changed unless the RTC\r
* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
- * \r
+ *\r
* @param RCC_RTCCLKSource: specifies the RTC clock source.\r
* This parameter can be one of the following values:\r
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
* @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
* @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
* @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
- * \r
+ *\r
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
* work in STOP and STANDBY modes, and can be used as wakeup source.\r
* However, when the HSE clock is used as RTC clock source, the RTC\r
* cannot be used in STOP and STANDBY modes.\r
- * \r
+ *\r
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
* RTC clock source).\r
- * \r
+ *\r
* @retval None\r
*/\r
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
\r
/* Check the parameters */\r
assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
- \r
+\r
if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
- { \r
+ {\r
/* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
tmpreg = RCC->CR;\r
\r
/* Store the new value */\r
RCC->CR = tmpreg;\r
}\r
- \r
+\r
RCC->CSR &= ~RCC_CSR_RTCSEL;\r
- \r
+\r
/* Select the RTC clock source */\r
RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
}\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
}\r
\r
{\r
/* Check the parameters */\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
*(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
}\r
\r
/**\r
* @brief Enables or disables the AHB peripheral clock.\r
* @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
* @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
* @arg RCC_AHBPeriph_GPIOG: GPIOG clock\r
* @arg RCC_AHBPeriph_CRC: CRC clock\r
- * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)\r
* @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
* @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
* @arg RCC_AHBPeriph_AES: AES clock\r
/* Check the parameters */\r
assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
if (NewState != DISABLE)\r
{\r
RCC->AHBENR |= RCC_AHBPeriph;\r
/**\r
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
* @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
+ * is disabled and the application software has to enable this clock before\r
* using it.\r
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
/**\r
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
* @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
+ * is disabled and the application software has to enable this clock before\r
* using it.\r
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_APB1Periph_TIM2: TIM2 clock\r
* @arg RCC_APB1Periph_TIM3: TIM3 clock\r
* @arg RCC_APB1Periph_TIM4: TIM4 clock\r
- * @arg RCC_APB1Periph_TIM5: TIM5 clock \r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
* @arg RCC_APB1Periph_TIM6: TIM6 clock\r
* @arg RCC_APB1Periph_TIM7: TIM7 clock\r
* @arg RCC_APB1Periph_LCD: LCD clock\r
* @arg RCC_APB1Periph_USART2: USART2 clock\r
* @arg RCC_APB1Periph_USART3: USART3 clock\r
* @arg RCC_APB1Periph_UART4: UART4 clock\r
- * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
* @arg RCC_APB1Periph_I2C1: I2C1 clock\r
* @arg RCC_APB1Periph_I2C2: I2C2 clock\r
* @arg RCC_APB1Periph_USB: USB clock\r
* This parameter can be any combination of the following values:\r
* @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
* @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock \r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock\r
* @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
* @arg RCC_AHBPeriph_GPIOE: GPIOE clock\r
* @arg RCC_AHBPeriph_GPIOH: GPIOH clock\r
* @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
- * @arg RCC_AHBPeriph_GPIOG: GPIOG clock \r
+ * @arg RCC_AHBPeriph_GPIOG: GPIOG clock\r
* @arg RCC_AHBPeriph_CRC: CRC clock\r
- * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)\r
* @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
* @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
* @arg RCC_AHBPeriph_AES: AES clock\r
- * @arg RCC_AHBPeriph_FSMC: FSMC clock \r
+ * @arg RCC_AHBPeriph_FSMC: FSMC clock\r
* @param NewState: new state of the specified peripheral reset.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
- * @arg RCC_APB2Periph_TIM9: TIM9 clock \r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock\r
* @arg RCC_APB2Periph_TIM10: TIM10 clock\r
* @arg RCC_APB2Periph_TIM11: TIM11 clock\r
* @arg RCC_APB2Periph_ADC1: ADC1 clock\r
* @arg RCC_APB1Periph_TIM2: TIM2 clock\r
* @arg RCC_APB1Periph_TIM3: TIM3 clock\r
* @arg RCC_APB1Periph_TIM4: TIM4 clock\r
- * @arg RCC_APB1Periph_TIM5: TIM5 clock \r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
* @arg RCC_APB1Periph_TIM6: TIM6 clock\r
* @arg RCC_APB1Periph_TIM7: TIM7 clock\r
* @arg RCC_APB1Periph_LCD: LCD clock\r
* @arg RCC_APB1Periph_WWDG: WWDG clock\r
* @arg RCC_APB1Periph_SPI2: SPI2 clock\r
- * @arg RCC_APB1Periph_SPI3: SPI3 clock \r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
* @arg RCC_APB1Periph_USART2: USART2 clock\r
* @arg RCC_APB1Periph_USART3: USART3 clock\r
* @arg RCC_APB1Periph_UART4: UART4 clock\r
- * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
* @arg RCC_APB1Periph_I2C1: I2C1 clock\r
* @arg RCC_APB1Periph_I2C2: I2C2 clock\r
* @arg RCC_APB1Periph_USB: USB clock\r
* @arg RCC_APB1Periph_PWR: PWR clock\r
* @arg RCC_APB1Periph_DAC: DAC clock\r
- * @arg RCC_APB1Periph_COMP \r
+ * @arg RCC_APB1Periph_COMP\r
* @param NewState: new state of the specified peripheral clock.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
* @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
* power consumption.\r
* - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * - By default, all peripheral clocks are enabled during SLEEP mode.\r
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
* @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock \r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock\r
* @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
* @arg RCC_AHBPeriph_GPIOE: GPIOE clock\r
* @arg RCC_AHBPeriph_GPIOH: GPIOH clock\r
* @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
- * @arg RCC_AHBPeriph_GPIOG: GPIOG clock \r
+ * @arg RCC_AHBPeriph_GPIOG: GPIOG clock\r
* @arg RCC_AHBPeriph_CRC: CRC clock\r
- * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_SRAM: SRAM clock \r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)\r
+ * @arg RCC_AHBPeriph_SRAM: SRAM clock\r
* @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
* @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
* @arg RCC_AHBPeriph_AES: AES clock\r
/* Check the parameters */\r
assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
if (NewState != DISABLE)\r
{\r
RCC->AHBLPENR |= RCC_AHBPeriph;\r
* @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
* power consumption.\r
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
* @arg RCC_APB2Periph_TIM10: TIM10 clock\r
* @arg RCC_APB2Periph_TIM11: TIM11 clock\r
* @arg RCC_APB2Periph_ADC1: ADC1 clock\r
- * @arg RCC_APB2Periph_SDIO: SDIO clock \r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock\r
* @arg RCC_APB2Periph_SPI1: SPI1 clock\r
* @arg RCC_APB2Periph_USART1: USART1 clock\r
* @param NewState: new state of the specified peripheral clock.\r
/* Check the parameters */\r
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
if (NewState != DISABLE)\r
{\r
RCC->APB2LPENR |= RCC_APB2Periph;\r
* @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
* power consumption.\r
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
* This parameter can be any combination of the following values:\r
* @arg RCC_APB1Periph_TIM2: TIM2 clock\r
* @arg RCC_APB1Periph_USART2: USART2 clock\r
* @arg RCC_APB1Periph_USART3: USART3 clock\r
* @arg RCC_APB1Periph_UART4: UART4 clock\r
- * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
* @arg RCC_APB1Periph_I2C1: I2C1 clock\r
* @arg RCC_APB1Periph_I2C2: I2C2 clock\r
* @arg RCC_APB1Periph_USB: USB clock\r
* @arg RCC_APB1Periph_PWR: PWR clock\r
* @arg RCC_APB1Periph_DAC: DAC clock\r
* @arg RCC_APB1Periph_COMP: COMP clock\r
- * @param NewState: new state \r
+ * @param NewState: new state\r
* @param NewState: new state of the specified peripheral clock.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
/* Check the parameters */\r
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
if (NewState != DISABLE)\r
{\r
RCC->APB1LPENR |= RCC_APB1Periph;\r
*/\r
\r
/** @defgroup RCC_Group4 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
+ * @brief Interrupts and flags management functions\r
*\r
@verbatim\r
===============================================================================\r
* @brief Enables or disables the specified RCC interrupts.\r
* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
* and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
- * automatically generated. The NMI will be executed indefinitely, and \r
+ * automatically generated. The NMI will be executed indefinitely, and\r
* since NMI has higher priority than any other IRQ (and main program)\r
* the application will be stacked in the NMI ISR unless the CSS interrupt\r
* pending bit is cleared.\r
* @arg RCC_IT_HSERDY: HSE ready interrupt\r
* @arg RCC_IT_PLLRDY: PLL ready interrupt\r
* @arg RCC_IT_MSIRDY: MSI ready interrupt\r
- * @arg RCC_IT_LSECSS: LSE CSS interrupt \r
+ * @arg RCC_IT_LSECSS: LSE CSS interrupt\r
* @param NewState: new state of the specified RCC interrupts.\r
* This parameter can be: ENABLE or DISABLE.\r
* @retval None\r
/* Check the parameters */\r
assert_param(IS_RCC_IT(RCC_IT));\r
assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
+\r
if (NewState != DISABLE)\r
{\r
/* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
* @param RCC_FLAG: specifies the flag to check.\r
* This parameter can be one of the following values:\r
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
- * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
+ * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready\r
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
* @arg RCC_FLAG_PLLRDY: PLL clock ready\r
- * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected \r
+ * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected\r
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset\r
* @arg RCC_FLAG_PINRST: Pin reset\r
* @arg RCC_FLAG_PORRST: POR/PDR reset\r
* @arg RCC_FLAG_SFTRST: Software reset\r
\r
/**\r
* @brief Clears the RCC reset flags.\r
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,\r
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
* @param None\r
* @retval None\r
* @param RCC_IT: specifies the RCC interrupt source to check.\r
* This parameter can be one of the following values:\r
* @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt \r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
* @arg RCC_IT_HSIRDY: HSI ready interrupt\r
* @arg RCC_IT_HSERDY: HSE ready interrupt\r
* @arg RCC_IT_PLLRDY: PLL ready interrupt\r
* @arg RCC_IT_MSIRDY: MSI ready interrupt\r
- * @arg RCC_IT_LSECSS: LSE CSS interrupt \r
+ * @arg RCC_IT_LSECSS: LSE CSS interrupt\r
* @arg RCC_IT_CSS: Clock Security System interrupt\r
* @retval The new state of RCC_IT (SET or RESET).\r
*/\r
ITStatus bitstatus = RESET;\r
/* Check the parameters */\r
assert_param(IS_RCC_GET_IT(RCC_IT));\r
- \r
+\r
/* Check the status of the specified RCC interrupt */\r
if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
{\r
* @arg RCC_IT_HSIRDY: HSI ready interrupt\r
* @arg RCC_IT_HSERDY: HSE ready interrupt\r
* @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
* @arg RCC_IT_LSECSS: LSE CSS interrupt\r
* @arg RCC_IT_CSS: Clock Security System interrupt\r
* @retval None\r
{\r
/* Check the parameters */\r
assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
- \r
+\r
/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
pending bits */\r
*(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_sdio.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the SDIO peripheral:\r
- * + Initialization \r
- * + Interrupts and flags management\r
- *\r
- * @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL\r
- (PLLVCO) througth a fixed divider by 2.\r
- Before to start working with SDIO peripheral make sure that the PLLVCO is \r
- well configured to 96MHz. \r
- The SDIO peripheral uses two clock signals: \r
- (++) SDIO adapter clock (SDIOCLK = 48 MHz).\r
- (++) APB2 bus clock (PCLK2).\r
- PCLK2 and SDIO_CK clock frequencies must respect the following \r
- condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).\r
- (#) Enable peripheral clock using \r
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). \r
- (#) According to the SDIO mode, enable the GPIO clocks using\r
- RCC_AHBPeriphClockCmd() function.\r
- The I/O can be one of the following configurations: \r
- (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. \r
- (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. \r
- (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].\r
-\r
- (#) Peripheral's alternate function: \r
- (++) Connect the pin to the desired peripherals' Alternate \r
- Function (AF) using GPIO_PinAFConfig() function.\r
- (++) Configure the desired pin in alternate function by: \r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
- (++) Select the type, pull-up/pull-down and output speed via \r
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
- (++) Call GPIO_Init() function.\r
-\r
- (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, \r
- hardware, flow control and the Clock Divider using the SDIO_Init() \r
- function. \r
- (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) \r
- function. \r
- (#) Enable the clock using the SDIO_ClockCmd() function. \r
- (#) Enable the NVIC and the corresponding interrupt using the function \r
- SDIO_ITConfig() if you need to use interrupt mode. \r
- (#) When using the DMA mode\r
- (++) Configure the DMA using DMA_Init() function.\r
- (++) Active the needed channel Request using SDIO_DMACmd() function.\r
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.\r
- (#) To control the CPSM (Command Path State Machine) and send commands to the\r
- card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and \r
- SDIO_GetResponse() functions. First, user has to fill the command \r
- structure (pointer to SDIO_CmdInitTypeDef) according to the selected \r
- command to be sent. The parameters that should be filled are: \r
- (++) Command Argument.\r
- (++) Command Index.\r
- (++) Command Response type.\r
- (++) Command Wait.\r
- (++) CPSM Status (Enable or Disable).\r
- To check if the command is well received, read the SDIO_CMDRESP register \r
- using the SDIO_GetCommandResponse(). The SDIO responses registers \r
- (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function. \r
- (#) To control the DPSM (Data Path State Machine) and send/receive \r
- data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),\r
- SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.\r
-\r
- *** Read Operations *** \r
- ----------------------- \r
- [..]\r
- (#) First, user has to fill the data structure (pointer to \r
- SDIO_DataInitTypeDef) according to the selected data type to be received. \r
- The parameters that should be filled are:\r
- (++) Data TimeOut.\r
- (++) Data Length.\r
- (++) Data Block size.\r
- (++) Data Transfer direction: should be from card (To SDIO).\r
- (++) Data Transfer mode.\r
- (++) DPSM Status (Enable or Disable).\r
- (#) Configure the SDIO resources to receive the data from the card \r
- according to selected transfer mode (Refer to Step 8, 9 and 10).\r
- (#) Send the selected Read command (refer to step 11).\r
- (#) Use the SDIO flags/interrupts to check the transfer status.\r
- \r
- *** Write Operations *** \r
- ------------------------ \r
- [..]\r
- (#) First, user has to fill the data structure (pointer to\r
- SDIO_DataInitTypeDef) according to the selected data type to be received. \r
- The parameters that should be filled are: \r
- (++) Data TimeOut.\r
- (++) Data Length.\r
- (++) Data Block size.\r
- (++) Data Transfer direction: should be to card (To CARD).\r
- (++) Data Transfer mode.\r
- (++) DPSM Status (Enable or Disable).\r
- (#) Configure the SDIO resources to send the data to the card \r
- according to selected transfer mode (Refer to Step 8, 9 and 10).\r
- (#) Send the selected Write command (refer to step 11).\r
- (#) Use the SDIO flags/interrupts to check the transfer status.\r
-\r
- @endverbatim\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_sdio.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO \r
- * @brief SDIO driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/ \r
-\r
-/* ------------ SDIO registers bit address in the alias region ----------- */\r
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* Alias word address of CLKEN bit */\r
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
-#define CLKEN_BitNumber 0x08\r
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* Alias word address of SDIOSUSPEND bit */\r
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
-#define SDIOSUSPEND_BitNumber 0x0B\r
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
-\r
-/* Alias word address of ENCMDCOMPL bit */\r
-#define ENCMDCOMPL_BitNumber 0x0C\r
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
-\r
-/* Alias word address of NIEN bit */\r
-#define NIEN_BitNumber 0x0D\r
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
-\r
-/* Alias word address of ATACMD bit */\r
-#define ATACMD_BitNumber 0x0E\r
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* Alias word address of DMAEN bit */\r
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
-#define DMAEN_BitNumber 0x03\r
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTART bit */\r
-#define RWSTART_BitNumber 0x08\r
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTOP bit */\r
-#define RWSTOP_BitNumber 0x09\r
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
-\r
-/* Alias word address of RWMOD bit */\r
-#define RWMOD_BitNumber 0x0A\r
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
-\r
-/* Alias word address of SDIOEN bit */\r
-#define SDIOEN_BitNumber 0x0B\r
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
-\r
-/* ---------------------- SDIO registers bit mask ------------------------ */\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* CLKCR register clear mask */\r
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
-\r
-/* --- PWRCTRL Register ---*/\r
-\r
-/* SDIO PWRCTRL Mask */\r
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* SDIO DCTRL Clear Mask */\r
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* CMD Register clear mask */\r
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
-\r
-/* SDIO RESP Registers Address */\r
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup SDIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ==============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void SDIO_DeInit(void)\r
-{\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); \r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO peripheral according to the specified \r
- * parameters in the SDIO_InitStruct.\r
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
- * that contains the configuration information for the SDIO peripheral.\r
- * @retval None\r
- */\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
- \r
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
- /* Get the SDIO CLKCR value */\r
- tmpreg = SDIO->CLKCR;\r
- \r
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
- tmpreg &= CLKCR_CLEAR_MASK;\r
- \r
- /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
- /* Set BYPASS bit according to SDIO_ClockBypass value */\r
- /* Set WIDBUS bits according to SDIO_BusWide value */\r
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
- \r
- /* Write to SDIO CLKCR */\r
- SDIO->CLKCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_InitStruct member with its default value.\r
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- /* SDIO_InitStruct members default value */\r
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO Clock.\r
- * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_ClockCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets the power status of the controller.\r
- * @param SDIO_PowerState: new state of the Power state. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_PowerState_OFF: SDIO Power OFF.\r
- * @arg SDIO_PowerState_ON: SDIO Power ON.\r
- * @retval None\r
- */\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
-\r
- SDIO->POWER = SDIO_PowerState;\r
-}\r
-\r
-/**\r
- * @brief Gets the power status of the controller.\r
- * @param None\r
- * @retval Power status of the controller. The returned value can\r
- * be one of the following:\r
- * - 0x00: Power OFF\r
- * - 0x02: Power UP\r
- * - 0x03: Power ON \r
- */\r
-uint32_t SDIO_GetPowerState(void)\r
-{\r
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group2 DMA transfers management functions\r
- * @brief DMA transfers management functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### DMA transfers management functions #####\r
- ==============================================================================\r
- [..] This section provide functions allowing to program SDIO DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the SDIO DMA request.\r
- * @param NewState: new state of the selected SDIO DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_DMACmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group3 Command path state machine (CPSM) management functions\r
- * @brief Command path state machine (CPSM) management functions \r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### Command path state machine (CPSM) management functions #####\r
- ==============================================================================\r
- [..] This section provide functions allowing to program and read the Command \r
- path state machine (CPSM).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the SDIO Command according to the specified \r
- * parameters in the SDIO_CmdInitStruct and send the command.\r
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
- * structure that contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
- \r
-/*---------------------------- SDIO ARG Configuration ------------------------*/\r
- /* Set the SDIO Argument value */\r
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
- \r
-/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
- /* Get the SDIO CMD value */\r
- tmpreg = SDIO->CMD;\r
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
- tmpreg &= CMD_CLEAR_MASK;\r
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
- /* Set WAITRESP bits according to SDIO_Response value */\r
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
- /* Set CPSMEN bits according to SDIO_CPSM value */\r
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
- \r
- /* Write to SDIO CMD */\r
- SDIO->CMD = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
-{\r
- /* SDIO_CmdInitStruct members default value */\r
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns command index of last command for which response received.\r
- * @param None\r
- * @retval Returns the command index of the last command response received.\r
- */\r
-uint8_t SDIO_GetCommandResponse(void)\r
-{\r
- return (uint8_t)(SDIO->RESPCMD);\r
-}\r
-\r
-/**\r
- * @brief Returns response received from the card for the last command.\r
- * @param SDIO_RESP: Specifies the SDIO response register. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_RESP1: Response Register 1.\r
- * @arg SDIO_RESP2: Response Register 2.\r
- * @arg SDIO_RESP3: Response Register 3.\r
- * @arg SDIO_RESP4: Response Register 4.\r
- * @retval The Corresponding response register value.\r
- */\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_RESP(SDIO_RESP));\r
-\r
- tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
- \r
- return (*(__IO uint32_t *) tmp); \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group4 Data path state machine (DPSM) management functions\r
- * @brief Data path state machine (DPSM) management functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### Data path state machine (DPSM) management functions #####\r
- ==============================================================================\r
- [..] This section provide functions allowing to program and read the Data path \r
- state machine (DPSM).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the SDIO data path according to the specified \r
- * parameters in the SDIO_DataInitStruct.\r
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
- * contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
-\r
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
- /* Set the SDIO Data TimeOut value */\r
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
-\r
-/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
- /* Set the SDIO DataLength value */\r
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
-\r
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
- /* Get the SDIO DCTRL value */\r
- tmpreg = SDIO->DCTRL;\r
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
- tmpreg &= DCTRL_CLEAR_MASK;\r
- /* Set DEN bit according to SDIO_DPSM value */\r
- /* Set DTMODE bit according to SDIO_TransferMode value */\r
- /* Set DTDIR bit according to SDIO_TransferDir value */\r
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
-\r
- /* Write to SDIO DCTRL */\r
- SDIO->DCTRL = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_DataInitStruct member with its default value.\r
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- /* SDIO_DataInitStruct members default value */\r
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns number of remaining data bytes to be transferred.\r
- * @param None\r
- * @retval Number of remaining data bytes to be transferred\r
- */\r
-uint32_t SDIO_GetDataCounter(void)\r
-{ \r
- return SDIO->DCOUNT;\r
-}\r
-\r
-/**\r
- * @brief Read one data word from Rx FIFO.\r
- * @param None\r
- * @retval Data received\r
- */\r
-uint32_t SDIO_ReadData(void)\r
-{ \r
- return SDIO->FIFO;\r
-}\r
-\r
-/**\r
- * @brief Write one data word to Tx FIFO.\r
- * @param Data: 32-bit data word to write.\r
- * @retval None\r
- */\r
-void SDIO_WriteData(uint32_t Data)\r
-{ \r
- SDIO->FIFO = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the number of words left to be written to or read from FIFO. \r
- * @param None\r
- * @retval Remaining number of words.\r
- */\r
-uint32_t SDIO_GetFIFOCount(void)\r
-{ \r
- return SDIO->FIFOCNT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group5 SDIO IO Cards mode management functions\r
- * @brief SDIO IO Cards mode management functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### SDIO IO Cards mode management functions #####\r
- ==============================================================================\r
- [..] This section provide functions allowing to program and read the SDIO IO \r
- Cards.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Starts the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Start SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Stops the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Stop SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets one of the two options of inserting read wait interval.\r
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
- * This parametre can be:\r
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.\r
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
- \r
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode Operation.\r
- * @param NewState: new state of SDIO specific operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOOperation(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode suspend command sending.\r
- * @param NewState: new state of the SD I/O Mode suspend command.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group6 CE-ATA mode management functions\r
- * @brief CE-ATA mode management functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### CE-ATA mode management functions #####\r
- ==============================================================================\r
- [..] This section provide functions allowing to program and read the CE-ATA \r
- card.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the command completion signal.\r
- * @param NewState: new state of command completion signal. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CE-ATA interrupt.\r
- * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CEATAITCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
-}\r
-\r
-/**\r
- * @brief Sends CE-ATA command (CMD61).\r
- * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendCEATACmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Group7 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
-\r
-\r
- @verbatim\r
- ==============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ==============================================================================\r
-\r
- @endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the SDIO interrupts.\r
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt.\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt.\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt.\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.\r
- * @param NewState: new state of the specified SDIO interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None \r
- */\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_IT(SDIO_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SDIO interrupts */\r
- SDIO->MASK |= SDIO_IT;\r
- }\r
- else\r
- {\r
- /* Disable the SDIO interrupts */\r
- SDIO->MASK &= ~SDIO_IT;\r
- } \r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO flag is set or not.\r
- * @param SDIO_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout.\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout.\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required).\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode.\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).\r
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress.\r
- * @arg SDIO_FLAG_TXACT: Data transmit in progress.\r
- * @arg SDIO_FLAG_RXACT: Data receive in progress.\r
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.\r
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.\r
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full.\r
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full.\r
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty.\r
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty.\r
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO.\r
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO.\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.\r
- * @retval The new state of SDIO_FLAG (SET or RESET).\r
- */\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
-{ \r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
- \r
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO's pending flags.\r
- * @param SDIO_FLAG: specifies the flag to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout.\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout.\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required).\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode.\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.\r
- * @retval None\r
- */\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
- \r
- SDIO->ICR = SDIO_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
- * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt.\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt.\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt.\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.\r
- * @retval The new state of SDIO_IT (SET or RESET).\r
- */\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
-{ \r
- ITStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO's interrupt pending bits.\r
- * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt.\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.\r
- * @retval None\r
- */\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
- \r
- SDIO->ICR = SDIO_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_spi.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Serial peripheral interface (SPI):\r
- * + Initialization and Configuration\r
- * + Data transfers functions\r
- * + Hardware CRC Calculation\r
- * + DMA transfers management\r
- * + Interrupts and flags management\r
- *\r
- * @verbatim\r
- [..] The I2S feature is not implemented in STM32L1xx Ultra Low Power\r
- Medium-density devices and it's supported only STM32L1xx Ultra Low Power\r
- Medium-density Plus and High-density devices.\r
- \r
- ===============================================================================\r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..]\r
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
- function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
- function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)\r
- for SPI3.\r
- \r
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using \r
- RCC_AHBPeriphClockCmd() function. \r
- \r
- (#) Peripherals alternate function: \r
- (++) Connect the pin to the desired peripherals' Alternate \r
- Function (AF) using GPIO_PinAFConfig() function.\r
- (++) Configure the desired pin in alternate function by:\r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
- (++) Select the type, pull-up/pull-down and output speed via \r
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
- (++) Call GPIO_Init() function.\r
- \r
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
- function.In I2S mode, program the Mode, Standard, Data Format, MCLK \r
- Output, Audio frequency and Polarity using I2S_Init() function.\r
- \r
- (#) Enable the NVIC and the corresponding interrupt using the function \r
- SPI_ITConfig() if you need to use interrupt mode. \r
- \r
- (#) When using the DMA mode \r
- (++) Configure the DMA using DMA_Init() function.\r
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function.\r
- \r
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using\r
- I2S_Cmd().\r
- \r
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
- \r
- (#) Optionally, you can enable/configure the following parameters without\r
- re-initialization (i.e there is no need to call again SPI_Init() function):\r
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
- is programmed as Data direction parameter using the SPI_Init() \r
- function it can be possible to switch between SPI_Direction_Tx \r
- or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.\r
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter \r
- using the SPI_Init() function it can be possible to manage the \r
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function.\r
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. \r
- \r
- (#) To use the CRC Hardware calculation feature refer to the Peripheral \r
- CRC hardware Calculation subsection.\r
- \r
- @endverbatim \r
- \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_spi.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI \r
- * @brief SPI driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* SPI registers Masks */\r
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup SPI_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
- [..] This section provides a set of functions allowing to initialize the SPI \r
- Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS \r
- Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
- [..] The SPI_Init() function follows the SPI configuration procedures for \r
- Master mode and Slave mode (details for these procedures are available \r
- in reference manual (RM0038)).\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SPIx peripheral registers to their default\r
- * reset values.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
- * @retval None\r
- */\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
-\r
- if (SPIx == SPI1)\r
- {\r
- /* Enable SPI1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
- /* Release SPI1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
- }\r
- else if (SPIx == SPI2)\r
- {\r
- /* Enable SPI2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
- /* Release SPI2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
- }\r
- else\r
- {\r
- if (SPIx == SPI3)\r
- {\r
- /* Enable SPI3 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
- /* Release SPI3 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the SPI_InitStruct.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Check the SPI parameters */\r
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
-\r
-/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
- /* Get the SPIx CR1 value */\r
- tmpreg = SPIx->CR1;\r
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
- tmpreg &= CR1_CLEAR_MASK;\r
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
- master/salve mode, CPOL and CPHA */\r
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
- /* Set LSBFirst bit according to SPI_FirstBit value */\r
- /* Set BR bits according to SPI_BaudRatePrescaler value */\r
- /* Set CPOL bit according to SPI_CPOL value */\r
- /* Set CPHA bit according to SPI_CPHA value */\r
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
- /* Write to SPIx CR1 */\r
- SPIx->CR1 = tmpreg;\r
-\r
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);\r
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
- /* Write to SPIx CRCPOLY */\r
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the I2S_InitStruct.\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
- * (configured in I2S mode).\r
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral\r
- * configured in I2S mode.\r
- * @note\r
- * The function calculates the optimal prescaler needed to obtain the most \r
- * accurate audio frequency (depending on the I2S clock source, the PLL values \r
- * and the product configuration). But in case the prescaler value is greater \r
- * than 511, the default value (0x02) will be configured instead. \r
- * @retval None\r
- */\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
- uint32_t tmp = 0;\r
- RCC_ClocksTypeDef RCC_Clocks;\r
- uint32_t sourceclock = 0;\r
- \r
- /* Check the I2S parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
-\r
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
- SPIx->I2SPR = 0x0002;\r
- \r
- /* Get the I2SCFGR register value */\r
- tmpreg = SPIx->I2SCFGR;\r
- \r
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
- {\r
- i2sodd = (uint16_t)0;\r
- i2sdiv = (uint16_t)2; \r
- }\r
- /* If the requested audio frequency is not the default, compute the prescaler */\r
- else\r
- {\r
- /* Check the frame length (For the Prescaler computing) */\r
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
- {\r
- /* Packet length is 16 bits */\r
- packetlength = 1;\r
- }\r
- else\r
- {\r
- /* Packet length is 32 bits */\r
- packetlength = 2;\r
- }\r
-\r
- /* I2S Clock source is System clock: Get System Clock frequency */\r
- RCC_GetClocksFreq(&RCC_Clocks); \r
- \r
- /* Get the source clock value: based on System Clock value */\r
- sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
- \r
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
- {\r
- /* MCLK output is enabled */\r
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- else\r
- {\r
- /* MCLK output is disabled */\r
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- \r
- /* Remove the flaoting point */\r
- tmp = tmp / 10; \r
- \r
- /* Check the parity of the divider */\r
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
- \r
- /* Compute the i2sdiv prescaler */\r
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
- \r
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
- i2sodd = (uint16_t) (i2sodd << 8);\r
- }\r
- \r
- /* Test if the divider is 1 or 0 or greater than 0xFF */\r
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
- {\r
- /* Set the default values */\r
- i2sdiv = 2;\r
- i2sodd = 0;\r
- }\r
-\r
- /* Write to SPIx I2SPR register the computed value */\r
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
- \r
- /* Configure the I2S with the SPI_InitStruct values */\r
- tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
- (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
- \r
- /* Write to SPIx I2SCFGR */ \r
- SPIx->I2SCFGR = tmpreg; \r
-}\r
-\r
-/**\r
- * @brief Fills each SPI_InitStruct member with its default value.\r
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
-/*--------------- Reset SPI init structure parameters values -----------------*/\r
- /* Initialize the SPI_Direction member */\r
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
- /* initialize the SPI_Mode member */\r
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
- /* initialize the SPI_DataSize member */\r
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
- /* Initialize the SPI_CPOL member */\r
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
- /* Initialize the SPI_CPHA member */\r
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
- /* Initialize the SPI_NSS member */\r
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
- /* Initialize the SPI_BaudRatePrescaler member */\r
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
- /* Initialize the SPI_FirstBit member */\r
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
- /* Initialize the SPI_CRCPolynomial member */\r
- SPI_InitStruct->SPI_CRCPolynomial = 7;\r
-}\r
-\r
-/**\r
- * @brief Fills each I2S_InitStruct member with its default value.\r
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
-/*--------------- Reset I2S init structure parameters values -----------------*/\r
- /* Initialize the I2S_Mode member */\r
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
- \r
- /* Initialize the I2S_Standard member */\r
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
- \r
- /* Initialize the I2S_DataFormat member */\r
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
- \r
- /* Initialize the I2S_MCLKOutput member */\r
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
- \r
- /* Initialize the I2S_AudioFreq member */\r
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
- \r
- /* Initialize the I2S_CPOL member */\r
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral */\r
- SPIx->CR1 |= SPI_CR1_SPE;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral */\r
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral (in I2S mode) */\r
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral in I2S mode */\r
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the data size for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_DataSize: specifies the SPI data size.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_DataSize_16b: Set data frame format to 16bit.\r
- * @arg SPI_DataSize_8b: Set data frame format to 8bit.\r
- * @retval None.\r
- */\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
- /* Clear DFF bit */\r
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
- /* Set new DFF bit value */\r
- SPIx->CR1 |= SPI_DataSize;\r
-}\r
-\r
-/**\r
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_Direction_Tx: Selects Tx transmission direction.\r
- * @arg SPI_Direction_Rx: Selects Rx receive direction.\r
- * @retval None\r
- */\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
- if (SPI_Direction == SPI_Direction_Tx)\r
- {\r
- /* Set the Tx only mode */\r
- SPIx->CR1 |= SPI_Direction_Tx;\r
- }\r
- else\r
- {\r
- /* Set the Rx only mode */\r
- SPIx->CR1 &= SPI_Direction_Rx;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures internally by software the NSS pin for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally.\r
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally.\r
- * @retval None\r
- */\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
- {\r
- /* Set NSS pin internally by software */\r
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
- }\r
- else\r
- {\r
- /* Reset NSS pin internally by software */\r
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SS output for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx SS output.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI SS output */\r
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI SS output */\r
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group2 Data transfers functions\r
- * @brief Data transfers functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Data transfers functions #####\r
- ===============================================================================\r
-....[..] This section provides a set of functions allowing to manage the SPI data \r
- transfers.\r
-....[..] In reception, data are received and then stored into an internal Rx buffer \r
- while In transmission, data are first stored into an internal Tx buffer \r
- before being transmitted.\r
-....[..] The read access of the SPI_DR register can be done using the \r
- SPI_I2S_ReceiveData() function and returns the Rx buffered value. \r
- Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData() \r
- function and stores the written data into Tx buffer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3\r
- * in SPI mode or 2 or 3 in I2S mode.\r
- * @retval The value of the received data.\r
- */\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the data in the DR register */\r
- return SPIx->DR;\r
-}\r
-\r
-/**\r
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
- * @param Data: Data to be transmitted.\r
- * @retval None\r
- */\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Write in the DR register the data to be sent */\r
- SPIx->DR = Data;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
- * @brief Hardware CRC Calculation functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Hardware CRC Calculation functions #####\r
- ===============================================================================\r
- [..] This section provides a set of functions allowing to manage the SPI CRC \r
- hardware calculation SPI communication using CRC is possible through \r
- the following procedure:\r
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate \r
- Prescaler, Slave Management, Peripheral Mode and CRC Polynomial \r
- values using the SPI_Init() function.\r
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
- (#) Enable the SPI using the SPI_Cmd() function.\r
- (#) Before writing the last data to the TX buffer, set the CRCNext bit \r
- using the SPI_TransmitCRC() function to indicate that after \r
- transmission of the last data, the CRC should be transmitted.\r
- (#) After transmitting the last data, the SPI transmits the CRC.\r
- The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and \r
- compared against the SPI_RXCRCR value. \r
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an \r
- interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
- -@-\r
- (+@) It is advised to don't read the calculate CRC values during the communication.\r
- (+@) When the SPI is in slave mode, be careful to enable CRC calculation only \r
- when the clock is stable, that is, when the clock is in the steady state. \r
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
- the value of the SPE bit.\r
- (+@) With high bitrate frequencies, be careful when transmitting the CRC.\r
- As the number of used CPU cycles has to be as low as possible in the CRC \r
- transfer phase, it is forbidden to call software functions in the CRC \r
- transmission sequence to avoid errors in the last data and CRC reception. \r
- In fact, CRCNEXT bit has to be written before the end of the transmission/\r
- reception of the last data.\r
- (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
- degradation of the SPI speed performance due to CPU accesses impacting the \r
- SPI bandwidth.\r
- (+@) When the STM32L15xxx are configured as slaves and the NSS hardware mode is \r
- used, the NSS pin needs to be kept low between the data phase and the CRC \r
- phase.\r
- (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
- calculation takes place even if a high level is applied on the NSS pin. \r
- This may happen for example in case of a multislave environment where the \r
- communication master addresses slaves alternately.\r
- (+@) Between a slave deselection (high level on NSS) and a new slave selection \r
- (low level on NSS), the CRC value should be cleared on both master and slave\r
- sides in order to resynchronize the master and slave for their respective \r
- CRC calculation.\r
- -@- To clear the CRC, follow the procedure below:\r
- (#@) Disable SPI using the SPI_Cmd() function\r
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.\r
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
- (#@) Enable SPI using the SPI_Cmd() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx CRC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI CRC calculation */\r
- SPIx->CR1 |= SPI_CR1_CRCEN;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI CRC calculation */\r
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmit the SPIx CRC value.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Enable the selected SPI CRC transmission */\r
- SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
-}\r
-\r
-/**\r
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_CRC: specifies the CRC register to be read.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_CRC_Tx: Selects Tx CRC register.\r
- * @arg SPI_CRC_Rx: Selects Rx CRC register.\r
- * @retval The selected CRC register value.\r
- */\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
-{\r
- uint16_t crcreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_CRC(SPI_CRC));\r
- if (SPI_CRC != SPI_CRC_Rx)\r
- {\r
- /* Get the Tx CRC register */\r
- crcreg = SPIx->TXCRCR;\r
- }\r
- else\r
- {\r
- /* Get the Rx CRC register */\r
- crcreg = SPIx->RXCRCR;\r
- }\r
- /* Return the selected CRC register */\r
- return crcreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the CRC Polynomial register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval The CRC Polynomial register value.\r
- */\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the CRC polynomial register */\r
- return SPIx->CRCPR;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group4 DMA transfers management functions\r
- * @brief DMA transfers management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DMA transfers management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.\r
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.\r
- * @param NewState: new state of the selected SPI DMA transfer request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI DMA requests */\r
- SPIx->CR2 |= SPI_I2S_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI DMA requests */\r
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Group5 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
- [..] This section provides a set of functions allowing to configure the SPI \r
- Interrupts sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to \r
- manage the communication: Polling mode, Interrupt mode or DMA mode.\r
- *** Polling Mode ***\r
- ====================\r
- [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:\r
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer \r
- register.\r
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer \r
- register.\r
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer \r
- of the SPI.\r
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.\r
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.\r
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.\r
- (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.\r
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.\r
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.\r
- -@- Do not use the BSY flag to handle each data transmission or reception.\r
- It is better to use the TXE and RXNE flags instead.\r
- [..] In this Mode it is advised to use the following functions:\r
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).\r
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).\r
-\r
- *** Interrupt Mode ***\r
- ======================\r
- [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt \r
- sources and 7 pending bits: \r
- [..] Pending Bits:\r
- (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.\r
- (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.\r
- (#) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur.\r
- (#) SPI_IT_MODF : to indicate if a Mode Fault error occur.\r
- (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.\r
- (#) I2S_IT_UDR : to indicate an Underrun Error occurs.\r
- (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.\r
- [..] Interrupt Source:\r
- (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
- interrupt.\r
- (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
- empty interrupt.\r
- (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
- [..] In this Mode it is advised to use the following functions:\r
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT,\r
- FunctionalState NewState).\r
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).\r
- (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).\r
-\r
- *** DMA Mode ***\r
- ================\r
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel \r
- requests:\r
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
-\r
- [..] In this Mode it is advised to use the following function:\r
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq,\r
- FunctionalState NewState).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI/I2S interrupts.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
-\r
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.\r
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.\r
- * @arg SPI_I2S_IT_ERR: Error interrupt mask.\r
- * @param NewState: new state of the specified SPI interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
-{\r
- uint16_t itpos = 0, itmask = 0 ;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI IT index */\r
- itpos = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = (uint16_t)1 << (uint16_t)itpos;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI interrupt */\r
- SPIx->CR2 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI interrupt */\r
- SPIx->CR2 &= (uint16_t)~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
-\r
- * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
- * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
- * @arg SPI_FLAG_MODF: Mode Fault flag.\r
- * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
- * @arg SPI_I2S_FLAG_FRE: Format Error.\r
- * @arg I2S_FLAG_UDR: Underrun Error flag.\r
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
- */\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Check the status of the specified SPI flag */\r
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
- {\r
- /* SPI_I2S_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
-\r
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
- * This function clears only CRCERR flag.\r
-\r
- * @note OVR (OverRun error) flag is cleared by software sequence: a read \r
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * @note UDR (UnderRun error) flag is cleared by a read operation to \r
- * SPI_SR register (SPI_I2S_GetFlagStatus()). \r
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Clear the selected SPI CRC Error (CRCERR) flag */\r
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
-\r
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
- * @arg SPI_IT_MODF: Mode Fault interrupt.\r
- * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
- * @arg I2S_IT_UDR: Underrun interrupt. \r
- * @arg SPI_I2S_IT_FRE: Format Error interrupt. \r
- * @retval The new state of SPI_I2S_IT (SET or RESET).\r
- */\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI_I2S_IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Get the SPI_I2S_IT IT mask */\r
- itmask = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = 0x01 << itmask;\r
-\r
- /* Get the SPI_I2S_IT enable bit status */\r
- enablestatus = (SPIx->CR2 & itmask) ;\r
-\r
- /* Check the status of the specified SPI interrupt */\r
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
- {\r
- /* SPI_I2S_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
- * in SPI mode or 2 or 3 in I2S mode.\r
-\r
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
- * This function clears only CRCERR interrupt pending bit. \r
-\r
- * OVR (OverRun Error) interrupt pending bit is cleared by software \r
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
- * operation to SPI_SR register (SPI_I2S_GetITStatus()). \r
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
- * the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- uint16_t itpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI_I2S IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
- SPIx->SR = (uint16_t)~itpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_usart.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Universal synchronous asynchronous receiver\r
- * transmitter (USART): \r
- * + Initialization and Configuration\r
- * + Data transfers\r
- * + Multi-Processor Communication\r
- * + LIN mode\r
- * + Half-duplex mode\r
- * + Smartcard mode\r
- * + IrDA mode\r
- * + DMA transfers management\r
- * + Interrupts and flags management \r
- * \r
- * @verbatim\r
- ===============================================================================\r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..]\r
- (#) Enable peripheral clock using\r
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) function for\r
- USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
- function for USART2 and USART3.\r
- (#) According to the USART mode, enable the GPIO clocks using\r
- RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,\r
- or and SCLK).\r
- (#) Peripheral's alternate function:\r
- (++) Connect the pin to the desired peripherals' Alternate\r
- Function (AF) using GPIO_PinAFConfig() function.\r
- (++) Configure the desired pin in alternate function by:\r
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
- (++) Select the type, pull-up/pull-down and output speed via\r
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
- (++) Call GPIO_Init() function.\r
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware\r
- flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
- function.\r
- (#) For synchronous mode, enable the clock and program the polarity,\r
- phase and last bit using the USART_ClockInit() function.\r
- (#) Enable the NVIC and the corresponding interrupt using the function\r
- USART_ITConfig() if you need to use interrupt mode.\r
- (#) When using the DMA mode.\r
- (++) Configure the DMA using DMA_Init() function.\r
- (++) Active the needed channel Request using USART_DMACmd() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.\r
- [..]\r
- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
- for more details.\r
- \r
-@endverbatim\r
- \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_usart.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup USART \r
- * @brief USART driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
- USART_CR1_PS | USART_CR1_TE | \\r
- USART_CR1_RE))\r
-\r
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
- USART_CR2_CPHA | USART_CR2_LBCL))\r
-\r
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
-\r
-/*!< USART Interrupts mask */\r
-#define IT_MASK ((uint16_t)0x001F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup USART_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup USART_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to initialize the USART \r
- in asynchronous and in synchronous modes.\r
- (+) For the asynchronous mode only these parameters can be configured: \r
- (+) Baud Rate.\r
- (+) Word Length.\r
- (+) Stop Bit.\r
- (+) Parity: If the parity is enabled, then the MSB bit of the data written\r
- in the data register is transmitted but is changed by the parity bit.\r
- Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
- the possible USART frame formats are as listed in the following table:\r
- [..]\r
- +-------------------------------------------------------------+\r
- | M bit | PCE bit | USART frame |\r
- |---------------------|---------------------------------------|\r
- | 0 | 0 | | SB | 8 bit data | STB | |\r
- |---------|-----------|---------------------------------------|\r
- | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
- |---------|-----------|---------------------------------------|\r
- | 1 | 0 | | SB | 9 bit data | STB | |\r
- |---------|-----------|---------------------------------------|\r
- | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
- +-------------------------------------------------------------+\r
- [..]\r
- (+) Hardware flow control.\r
- (+) Receiver/transmitter modes.\r
- [..] The USART_Init() function follows the USART asynchronous configuration \r
- procedure(details for the procedure are available in reference manual \r
- (RM0038)).\r
- (+) For the synchronous mode in addition to the asynchronous mode parameters\r
- these parameters should be also configured:\r
- (++) USART Clock Enabled.\r
- (++) USART polarity.\r
- (++) USART phase.\r
- (++) USART LastBit.\r
- [..] These parameters can be configured using the USART_ClockInit() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values: USART1, USART2, USART3, \r
- * UART4 or UART5.\r
- * @retval None.\r
- */\r
-void USART_DeInit(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
-\r
- if (USARTx == USART1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
- }\r
- else if (USARTx == USART2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
- }\r
- else if (USARTx == USART3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
- } \r
- else if (USARTx == UART4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
- } \r
- else\r
- {\r
- if (USARTx == UART5)\r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
- }\r
- } \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral according to the specified\r
- * parameters in the USART_InitStruct.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values: USART1, USART2, USART3, \r
- * UART4 or UART5.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that \r
- * contains the configuration information for the specified USART peripheral.\r
- * @retval None.\r
- */\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
-{\r
- uint32_t tmpreg = 0x00, apbclock = 0x00;\r
- uint32_t integerdivider = 0x00;\r
- uint32_t fractionaldivider = 0x00;\r
- RCC_ClocksTypeDef RCC_ClocksStatus;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
-\r
- /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- }\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear STOP[13:12] bits */\r
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
-\r
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set STOP[13:12] bits according to USART_StopBits value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
- \r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR1 Configuration -----------------------*/\r
- tmpreg = USARTx->CR1;\r
- /* Clear M, PCE, PS, TE and RE bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
-\r
- /* Configure the USART Word Length, Parity and mode ----------------------- */\r
- /* Set the M bits according to USART_WordLength value */\r
- /* Set PCE and PS bits according to USART_Parity value */\r
- /* Set TE and RE bits according to USART_Mode value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
- USART_InitStruct->USART_Mode;\r
-\r
- /* Write to USART CR1 */\r
- USARTx->CR1 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR3 Configuration -----------------------*/ \r
- tmpreg = USARTx->CR3;\r
- /* Clear CTSE and RTSE bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
-\r
- /* Configure the USART HFC -------------------------------------------------*/\r
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
-\r
- /* Write to USART CR3 */\r
- USARTx->CR3 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART BRR Configuration -----------------------*/\r
- /* Configure the USART Baud Rate -------------------------------------------*/\r
- RCC_GetClocksFreq(&RCC_ClocksStatus);\r
- if (USARTx == USART1) \r
- {\r
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
- }\r
- else\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
- }\r
-\r
- /* Determine the integer part */\r
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
- {\r
- /* Integer part computing in case Oversampling mode is 8 Samples */\r
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- /* Integer part computing in case Oversampling mode is 16 Samples */\r
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- tmpreg = (integerdivider / 100) << 4;\r
-\r
- /* Determine the fractional part */\r
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
-\r
- /* Implement the fractional part in the register */\r
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
- {\r
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
- }\r
- \r
- /* Write to USART BRR */\r
- USARTx->BRR = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_InitStruct member with its default value.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
-{\r
- /* USART_InitStruct members default value */\r
- USART_InitStruct->USART_BaudRate = 9600;\r
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
- USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
- USART_InitStruct->USART_Parity = USART_Parity_No ;\r
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral Clock according to the \r
- * specified parameters in the USART_ClockInitStruct.\r
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure that contains the configuration information for the specified \r
- * USART peripheral.\r
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.\r
- * @retval None.\r
- */\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- uint32_t tmpreg = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set CLKEN bit according to USART_Clock value */\r
- /* Set CPOL bit according to USART_CPOL value */\r
- /* Set CPHA bit according to USART_CPHA value */\r
- /* Set LBCL bit according to USART_LastBit value */\r
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_ClockInitStruct member with its default value.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- /* USART_ClockInitStruct members default value */\r
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USARTx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected USART by setting the UE bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_UE;\r
- }\r
- else\r
- {\r
- /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the system clock prescaler.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Prescaler: specifies the prescaler clock. \r
- * @note The function is used for IrDA mode with UART4 and UART5. \r
- * @retval None.\r
- */\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Clear the USART prescaler */\r
- USARTx->GTPR &= USART_GTPR_GT;\r
- /* Set the USART prescaler */\r
- USARTx->GTPR |= USART_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's 8x oversampling mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART 8x oversampling mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- *\r
- * @note\r
- * This function has to be called before calling USART_Init()\r
- * function in order to have correct baudrate Divider value.\r
- * @retval None\r
- */\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_OVER8;\r
- }\r
- else\r
- {\r
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
- }\r
-} \r
-\r
-/**\r
- * @brief Enables or disables the USART's one bit sampling method.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART one bit sampling method.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_ONEBIT;\r
- }\r
- else\r
- {\r
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group2 Data transfers functions\r
- * @brief Data transfers functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Data transfers functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage \r
- the USART data transfers.\r
- [..] During an USART reception, data shifts in least significant bit first \r
- through the RX pin. In this mode, the USART_DR register consists of \r
- a buffer (RDR) between the internal bus and the received shift register.\r
- When a transmission is taking place, a write instruction to \r
- the USART_DR register stores the data in the TDR register and which is \r
- copied in the shift register at the end of the current transmission.\r
- [..] The read access of the USART_DR register can be done using \r
- the USART_ReceiveData() function and returns the RDR buffered value.\r
- Whereas a write access to the USART_DR can be done using USART_SendData()\r
- function and stores the written data into TDR buffer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Transmits single data through the USARTx peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param Data: the data to transmit.\r
- * @retval None.\r
- */\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DATA(Data)); \r
- \r
- /* Transmit Data */\r
- USARTx->DR = (Data & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the USARTx peripheral.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval The received data.\r
- */\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Receive Data */\r
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group3 MultiProcessor Communication functions\r
- * @brief Multi-Processor Communication functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Multi-Processor Communication functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage the USART \r
- multiprocessor communication.\r
- [..] For instance one of the USARTs can be the master, its TX output is\r
- connected to the RX input of the other USART. The others are slaves,\r
- their respective TX outputs are logically ANDed together and connected \r
- to the RX input of the master. USART multiprocessor communication is \r
- possible through the following procedure:\r
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, \r
- Mode transmitter or Mode receiver and hardware flow control values \r
- using the USART_Init() function.\r
- (#) Configures the USART address using the USART_SetAddress() function.\r
- (#) Configures the wake up methode (USART_WakeUp_IdleLine or \r
- USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only \r
- for the slaves.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() \r
- function.\r
-\r
- [..] The USART Slave exit from mute mode when receive the wake up condition.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the address of the USART node.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Address: Indicates the address of the USART node.\r
- * @retval None\r
- */\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_ADDRESS(USART_Address)); \r
- \r
- /* Clear the USART address */\r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
- /* Set the USART address node */\r
- USARTx->CR2 |= USART_Address;\r
-}\r
-\r
-/**\r
- * @brief Determines if the USART is in mute mode or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART mute mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
- USARTx->CR1 |= USART_CR1_RWU;\r
- }\r
- else\r
- {\r
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
- }\r
-}\r
-/**\r
- * @brief Selects the USART WakeUp method.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_WakeUp: specifies the USART wakeup method.\r
- * This parameter can be one of the following values:\r
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection.\r
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark.\r
- * @retval None.\r
- */\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
- \r
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
- USARTx->CR1 |= USART_WakeUp;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group4 LIN mode functions\r
- * @brief LIN mode functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### LIN mode functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage the USART \r
- LIN Mode communication.\r
- [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance \r
- with the LIN standard.\r
- [..] Only this LIN Feature is supported by the USART IP:\r
- (+) LIN Master Synchronous Break send capability and LIN slave break \r
- detection capability : 13-bit break generation and 10/11 bit break \r
- detection.\r
- [..] USART LIN Master transmitter communication is possible through the \r
- following procedure:\r
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
- Mode transmitter or Mode receiver and hardware flow control values \r
- using the USART_Init() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Enable the LIN mode using the USART_LINCmd() function.\r
- (#) Send the break character using USART_SendBreak() function.\r
- [..] USART LIN Master receiver communication is possible through the \r
- following procedure:\r
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
- Mode transmitter or Mode receiver and hardware flow control values \r
- using the USART_Init() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Configures the break detection length \r
- using the USART_LINBreakDetectLengthConfig() function.\r
- (#) Enable the LIN mode using the USART_LINCmd() function.\r
- -@- In LIN mode, the following bits must be kept cleared:\r
- (+@) CLKEN in the USART_CR2 register.\r
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the USART LIN Break detection length.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
- * This parameter can be one of the following values:\r
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection.\r
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection.\r
- * @retval None.\r
- */\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
- \r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
- USARTx->CR2 |= USART_LINBreakDetectLength; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's LIN mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART LIN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
- USARTx->CR2 |= USART_CR2_LINEN;\r
- }\r
- else\r
- {\r
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits break characters.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval None.\r
- */\r
-void USART_SendBreak(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Send break characters */\r
- USARTx->CR1 |= USART_CR1_SBK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group5 Halfduplex mode function\r
- * @brief Half-duplex mode function \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Half-duplex mode function #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage the USART\r
- Half-duplex communication.\r
- [..] The USART can be configured to follow a single-wire half-duplex protocol \r
- where the TX and RX lines are internally connected.\r
- [..] USART Half duplex communication is possible through the following procedure:\r
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
- or Mode receiver and hardware flow control values using the USART_Init()\r
- function.\r
- (#) Configures the USART address using the USART_SetAddress() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
- -@- The RX pin is no longer used.\r
- -@- In Half-duplex mode the following bits must be kept cleared:\r
- (+@) LINEN and CLKEN bits in the USART_CR2 register.\r
- (+@) SCEN and IREN bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the USART's Half Duplex communication.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART Communication.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_HDSEL;\r
- }\r
- else\r
- {\r
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup USART_Group6 Smartcard mode functions\r
- * @brief Smartcard mode functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Smartcard mode functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage the USART \r
- Smartcard communication.\r
- [..] The Smartcard interface is designed to support asynchronous protocol \r
- Smartcards as defined in the ISO 7816-3 standard. The USART can provide \r
- a clock to the smartcard through the SCLK output. In smartcard mode, \r
- SCLK is not associated to the communication but is simply derived from \r
- the internal peripheral input clock through a 5-bit prescaler.\r
- [..] Smartcard communication is possible through the following procedure:\r
- (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() \r
- function.\r
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() \r
- function.\r
- (#) Program the USART clock using the USART_ClockInit() function as following:\r
- (++) USART Clock enabled.\r
- (++) USART CPOL Low.\r
- (++) USART CPHA on first edge.\r
- (++) USART Last Bit Clock Enabled.\r
- (#) Program the Smartcard interface using the USART_Init() function as \r
- following:\r
- (++) Word Length = 9 Bits.\r
- (++) 1.5 Stop Bit.\r
- (++) Even parity.\r
- (++) BaudRate = 12096 baud.\r
- (++) Hardware flow control disabled (RTS and CTS signals).\r
- (++) Tx and Rx enabled\r
- (#) Optionally you can enable the parity error interrupt using \r
- the USART_ITConfig() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
- (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
- [..] \r
- Please refer to the ISO 7816-3 specification for more details.\r
- [..] \r
- (@) It is also possible to choose 0.5 stop bit for receiving but it is \r
- recommended to use 1.5 stop bits for both transmitting and receiving \r
- to avoid switching between the two configurations.\r
- (@) In smartcard mode, the following bits must be kept cleared:\r
- (+@) LINEN bit in the USART_CR2 register.\r
- (+@) HDSEL and IREN bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the specified USART guard time.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param USART_GuardTime: specifies the guard time. \r
- * @retval None.\r
- */\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- \r
- /* Clear the USART Guard time */\r
- USARTx->GTPR &= USART_GTPR_PSC;\r
- /* Set the USART guard time */\r
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's Smart Card mode.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the Smart Card mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_SCEN;\r
- }\r
- else\r
- {\r
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables NACK transmission.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2 or USART3.\r
- * @param NewState: new state of the NACK transmission.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None.\r
- */\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_NACK;\r
- }\r
- else\r
- {\r
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group7 IrDA mode functions\r
- * @brief IrDA mode functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### IrDA mode functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to manage the USART \r
- IrDA communication.\r
- [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, \r
- any data on the IrDA receive line will be ignored by the IrDA decoder \r
- and if the Receiver is busy, data on the TX from the USART to IrDA will \r
- not be encoded by IrDA. While receiving data, transmission should be \r
- avoided as the data to be transmitted could be corrupted.\r
-\r
- [..] IrDA communication is possible through the following procedure:\r
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, \r
- Transmitter/Receiver modes and hardware flow control values using \r
- the USART_Init() function.\r
- (#) Enable the USART using the USART_Cmd() function.\r
- (#) Configures the IrDA pulse width by configuring the prescaler using \r
- the USART_SetPrescaler() function.\r
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal \r
- mode using the USART_IrDAConfig() function.\r
- (#) Enable the IrDA using the USART_IrDACmd() function.\r
-\r
- [..]\r
- (@) A pulse of width less than two and greater than one PSC period(s) may or \r
- may not be rejected.\r
- (@) The receiver set up time should be managed by software. The IrDA physical \r
- layer specification specifies a minimum of 10 ms delay between \r
- transmission and reception (IrDA is a half duplex protocol).\r
- (@) In IrDA mode, the following bits must be kept cleared:\r
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
- (+@) SCEN and HDSEL bits in the USART_CR3 register.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the USART's IrDA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IrDAMode: specifies the IrDA mode.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.\r
- * @arg USART_IrDAMode_Normal: USART IrDA Normal mode selected.\r
- * @retval None\r
- */\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
- \r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
- USARTx->CR3 |= USART_IrDAMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's IrDA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the IrDA mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
- USARTx->CR3 |= USART_CR3_IREN;\r
- }\r
- else\r
- {\r
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Group8 DMA transfers management functions\r
- * @brief DMA transfers management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### DMA transfers management functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Enables or disables the USART's DMA interface.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_DMAReq: specifies the DMA request.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_DMAReq_Tx: USART DMA transmit request.\r
- * @arg USART_DMAReq_Rx: USART DMA receive request.\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None\r
- */\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 |= USART_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup USART_Group9 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to configure the \r
- USART Interrupts sources, DMA channels requests and check or clear the \r
- flags or pending bits status. The user should identify which mode will \r
- be used in his application to manage the communication: Polling mode, \r
- Interrupt mode or DMA mode.\r
- *** Polling Mode ***\r
- ====================\r
- [..] In Polling Mode, the SPI communication can be managed by 10 flags:\r
- (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.\r
- (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.\r
- (#) USART_FLAG_TC: to indicate the status of the transmit operation.\r
- (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.\r
- (#) USART_FLAG_CTS: to indicate the status of the nCTS input.\r
- (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.\r
- (#) USART_FLAG_NE: to indicate if a noise error occur.\r
- (#) USART_FLAG_FE: to indicate if a frame error occur.\r
- (#) USART_FLAG_PE: to indicate if a parity error occur.\r
- (#) USART_FLAG_ORE: to indicate if an Overrun error occur.\r
- [..] In this Mode it is advised to use the following functions:\r
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
- \r
- *** Interrupt Mode ***\r
- ======================\r
- [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt \r
- sources and 10 pending bits:\r
- (+) Pending Bits:\r
- (##) USART_IT_TXE: to indicate the status of the transmit buffer \r
- register.\r
- (##) USART_IT_RXNE: to indicate the status of the receive buffer \r
- register.\r
- (##) USART_IT_TC: to indicate the status of the transmit operation.\r
- (##) USART_IT_IDLE: to indicate the status of the Idle Line.\r
- (##) USART_IT_CTS: to indicate the status of the nCTS input.\r
- (##) USART_IT_LBD: to indicate the status of the LIN break detection.\r
- (##) USART_IT_NE: to indicate if a noise error occur.\r
- (##) USART_IT_FE: to indicate if a frame error occur.\r
- (##) USART_IT_PE: to indicate if a parity error occur.\r
- (##) USART_IT_ORE: to indicate if an Overrun error occur\r
- (if the RXNEIE or EIE bits are set).\r
-\r
- (+) Interrupt Source:\r
- (##) USART_IT_TXE: specifies the interrupt source for the Tx buffer \r
- empty interrupt. \r
- (##) USART_IT_RXNE: specifies the interrupt source for the Rx buffer \r
- not empty interrupt.\r
- (##) USART_IT_TC: specifies the interrupt source for the Transmit \r
- complete interrupt. \r
- (##) USART_IT_IDLE: specifies the interrupt source for the Idle Line \r
- interrupt.\r
- (##) USART_IT_CTS: specifies the interrupt source for the CTS interrupt. \r
- (##) USART_IT_LBD: specifies the interrupt source for the LIN break \r
- detection interrupt. \r
- (##) USART_IT_PE: specifies the interrupt source for theparity error \r
- interrupt. \r
- (##) USART_IT_ERR: specifies the interrupt source for the errors \r
- interrupt.\r
- -@@- Some parameters are coded in order to use them as interrupt \r
- source or as pending bits.\r
- [..] In this Mode it is advised to use the following functions:\r
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, \r
- FunctionalState NewState).\r
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).\r
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).\r
- \r
- *** DMA Mode ***\r
- ================\r
- [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel \r
- requests:\r
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
- [..] In this Mode it is advised to use the following function:\r
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, \r
- FunctionalState NewState).\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified USART interrupts.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt.\r
- * @arg USART_IT_LBD: LIN Break detection interrupt.\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.\r
- * @arg USART_IT_TC: Transmission complete interrupt.\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
- * @arg USART_IT_IDLE: Idle line detection interrupt.\r
- * @arg USART_IT_PE: Parity Error interrupt.\r
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error).\r
- * @param NewState: new state of the specified USARTx interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
-{\r
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
- uint32_t usartxbase = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CONFIG_IT(USART_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- usartxbase = (uint32_t)USARTx;\r
-\r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
-\r
- /* Get the interrupt position */\r
- itpos = USART_IT & IT_MASK;\r
- itmask = (((uint32_t)0x01) << itpos);\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- usartxbase += 0x0C;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- usartxbase += 0x10;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- usartxbase += 0x14; \r
- }\r
- if (NewState != DISABLE)\r
- {\r
- *(__IO uint32_t*)usartxbase |= itmask;\r
- }\r
- else\r
- {\r
- *(__IO uint32_t*)usartxbase &= ~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART flag is set or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
- * @arg USART_FLAG_LBD: LIN Break detection flag.\r
- * @arg USART_FLAG_TXE: Transmit data register empty flag.\r
- * @arg USART_FLAG_TC: Transmission Complete flag.\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
- * @arg USART_FLAG_IDLE: Idle Line detection flag.\r
- * @arg USART_FLAG_ORE: OverRun Error flag.\r
- * @arg USART_FLAG_NE: Noise Error flag.\r
- * @arg USART_FLAG_FE: Framing Error flag.\r
- * @arg USART_FLAG_PE: Parity Error flag.\r
- * @retval The new state of USART_FLAG (SET or RESET).\r
- */\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_FLAG(USART_FLAG));\r
-\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if (USART_FLAG == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx's pending flags.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
- * @arg USART_FLAG_LBD: LIN Break detection flag.\r
- * @arg USART_FLAG_TC: Transmission Complete flag.\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
- * \r
- *\r
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) flags are cleared by software \r
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
- * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
- * @note RXNE flag can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * @note TC flag can be also cleared by software sequence: a read operation to \r
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
- * to USART_DR register (USART_SendData()).\r
- * @note TXE flag is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
-\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- USARTx->SR = (uint16_t)~USART_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART interrupt has occurred or not.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.\r
- * @arg USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set. \r
- * @arg USART_IT_NE: Noise Error interrupt\r
- * @arg USART_IT_FE: Framing Error interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @retval The new state of USART_IT (SET or RESET).\r
- */\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_GET_IT(USART_IT)); \r
-\r
- /* The CTS interrupt is not available for UART4 and UART5 */ \r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
- /* Get the interrupt position */\r
- itmask = USART_IT & IT_MASK;\r
- itmask = (uint32_t)0x01 << itmask;\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- itmask &= USARTx->CR1;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- itmask &= USARTx->CR2;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- itmask &= USARTx->CR3;\r
- }\r
- \r
- bitpos = USART_IT >> 0x08;\r
- bitpos = (uint32_t)0x01 << bitpos;\r
- bitpos &= USARTx->SR;\r
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx's interrupt pending bits.\r
- * @param USARTx: Select the USART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt. \r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
- * \r
-\r
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) pending bits are cleared by \r
- * software sequence: a read operation to USART_SR register \r
- * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
- * (USART_ReceiveData()).\r
- * @note RXNE pending bit can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * @note TC pending bit can be also cleared by software sequence: a read \r
- * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
- * operation to USART_DR register (USART_SendData()).\r
- * @note TXE pending bit is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint16_t bitpos = 0x00, itmask = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
-\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- bitpos = USART_IT >> 0x08;\r
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
- USARTx->SR = (uint16_t)~itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_wwdg.c\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 05-March-2012\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Window watchdog (WWDG) peripheral: \r
- * + Prescaler, Refresh window and Counter configuration\r
- * + WWDG activation\r
- * + Interrupts and flags management\r
- * \r
- * @verbatim\r
- * \r
- ============================================================================== \r
- ##### WWDG features ##### \r
- ============================================================================== \r
- [..] Once enabled the WWDG generates a system reset on expiry of a programmed\r
- time period, unless the program refreshes the counter (downcounter) \r
- before to reach 0x3F value (i.e. a reset is generated when the counter\r
- value rolls over from 0x40 to 0x3F). \r
- [..] An MCU reset is also generated if the counter value is refreshed\r
- before the counter has reached the refresh window value. This \r
- implies that the counter must be refreshed in a limited window.\r
-\r
- [..] Once enabled the WWDG cannot be disabled except by a system reset.\r
-\r
- [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
- reset occurs.\r
-\r
- [..] The WWDG counter input clock is derived from the APB clock divided \r
- by a programmable prescaler.\r
-\r
- [..] WWDG counter clock = PCLK1 / Prescaler.\r
- [..] WWDG timeout = (WWDG counter clock) * (counter value).\r
-\r
- [..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.\r
-\r
- ##### How to use this driver ##### \r
- ==============================================================================\r
- [..]\r
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) \r
- function.\r
- \r
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.\r
- \r
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.\r
- \r
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.\r
- When the WWDG is enabled the counter value should be configured to \r
- a value greater than 0x40 to prevent generating an immediate reset.\r
- \r
- (#) Optionally you can enable the Early wakeup interrupt which is \r
- generated when the counter reach 0x40.\r
- Once enabled this interrupt cannot be disabled except by a system reset.\r
- \r
- (#) Then the application program must refresh the WWDG counter at regular\r
- intervals during normal operation to prevent an MCU reset, using\r
- WWDG_SetCounter() function. This operation must occur only when\r
- the counter value is lower than the refresh window value, \r
- programmed using WWDG_SetWindowValue().\r
- \r
- * @endverbatim \r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_wwdg.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG \r
- * @brief WWDG driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ----------- WWDG registers bit address in the alias region ----------- */\r
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
-\r
-/* Alias word address of EWI bit */\r
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
-#define EWI_BitNumber 0x09\r
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
-\r
-/* --------------------- WWDG registers bit mask ------------------------ */\r
-\r
-/* CFR register bit mask */\r
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
-#define BIT_MASK ((uint8_t)0x7F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup WWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
- * @brief Prescaler, Refresh window and Counter configuration functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Prescaler, Refresh window and Counter configuration functions #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG Prescaler.\r
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
- * @retval None\r
- */\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
- /* Clear WDGTB[1:0] bits */\r
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
- tmpreg |= WWDG_Prescaler;\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG window value.\r
- * @param WindowValue: specifies the window value to be compared to the downcounter.\r
- * This parameter value must be lower than 0x80.\r
- * @retval None\r
- */\r
-void WWDG_SetWindowValue(uint8_t WindowValue)\r
-{\r
- __IO uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
- /* Clear W[6:0] bits */\r
-\r
- tmpreg = WWDG->CFR & CFR_W_MASK;\r
-\r
- /* Set W[6:0] bits according to WindowValue value */\r
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
-\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
- * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_EnableIT(void)\r
-{\r
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG counter value.\r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
- * an immediate reset).\r
- * @retval None\r
- */\r
-void WWDG_SetCounter(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- /* Write to T[6:0] bits to configure the counter value, no need to do\r
- a read-modify-write; writing a 0 to WDGA bit does nothing */\r
- WWDG->CR = Counter & BIT_MASK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Group2 WWDG activation functions\r
- * @brief WWDG activation functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### WWDG activation function #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables WWDG and load the counter value. \r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
- * an immediate reset).\r
- * @retval None\r
- */\r
-void WWDG_Enable(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- WWDG->CR = WWDG_CR_WDGA | Counter;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Interrupts and flags management functions #####\r
- ============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
- * @param None\r
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).\r
- */\r
-FlagStatus WWDG_GetFlagStatus(void)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- if ((WWDG->SR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears Early Wakeup interrupt flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_ClearFlag(void)\r
-{\r
- WWDG->SR = (uint32_t)RESET;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_board.h\r
- * @author Microcontroller Division\r
- * @version V1.0.3\r
- * @date May-2013\r
- * @brief Input/Output defines\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-\r
-#ifndef __DISCOVER_BOARD_H\r
-#define __DISCOVER_BOARD_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h" \r
-\r
-#define bool _Bool\r
-#define FALSE 0\r
-#define TRUE !FALSE\r
-\r
-/* MACROs for SET, RESET or TOGGLE Output port */\r
-\r
-#define GPIO_HIGH(a,b) a->BSRRL = b\r
-#define GPIO_LOW(a,b) a->BSRRH = b\r
-#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
-\r
-#define USERBUTTON_GPIO_PORT GPIOA\r
-#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
-#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
-\r
-#define LD_GPIO_PORT GPIOB\r
-#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
-#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
-#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
-\r
-#define CTN_GPIO_PORT GPIOC\r
-#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
-#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
-\r
-#define WAKEUP_GPIO_PORT GPIOA\r
-\r
-#define IDD_MEASURE_PORT GPIOA\r
-#define IDD_MEASURE GPIO_Pin_4\r
-\r
-#endif\r
-\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l_discovery_lcd.c\r
- * @author Microcontroller Division\r
- * @version V1.0.3\r
- * @date May-2013\r
- * @brief This file includes driver for the glass LCD Module mounted on \r
- * STM32l discovery board MB963\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l_discovery_lcd.h"\r
-#include "discover_board.h"\r
-#include "stm32l1xx_lcd.h"\r
-#include "main.h"\r
-\r
-/* this variable can be used for accelerate the scrolling exit when push user button */\r
-volatile bool KeyPressed = FALSE; \r
- \r
-/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */\r
-uint8_t t_bar[2]={0x0,0X0};\r
- \r
-/* =========================================================================\r
- LCD MAPPING\r
- =========================================================================\r
- A\r
- _ ----------\r
-COL |_| |\ |J /|\r
- F| H | K |B\r
- _ | \ | / |\r
-COL |_| --G-- --M--\r
- | /| \ |\r
- E| Q | N |C\r
- _ | / |P \| \r
-DP |_| ----------- \r
- D \r
-\r
- An LCD character coding is based on the following matrix:\r
- { E , D , P , N }\r
- { M , C , COL , DP}\r
- { B , A , K , J }\r
- { G , F , Q , H }\r
-\r
- The character 'A' for example is:\r
- -------------------------------\r
-LSB { 1 , 0 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
-MSB { 1 , 1 , 0 , 0 }\r
- -------------------\r
- 'A' = F E 0 0 hexa\r
-\r
-*/\r
-\r
-/* Constant table for cap characters 'A' --> 'Z' */\r
-const uint16_t CapLetterMap[26]=\r
- {\r
- /* A B C D E F G H I */\r
- 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,\r
- /* J K L M N O P Q R */\r
- 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,\r
- /* S T U V W X Y Z */\r
- 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0\r
- };\r
-\r
-/* Constant table for number '0' --> '9' */\r
-const uint16_t NumberMap[10]=\r
- {\r
- /* 0 1 2 3 4 5 6 7 8 9 */\r
- 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00\r
- };\r
-\r
-static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);\r
-\r
-/**\r
- * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_GLASS_Init(void)\r
-{\r
- LCD_InitTypeDef LCD_InitStruct;\r
-\r
- \r
- LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;\r
- LCD_InitStruct.LCD_Divider = LCD_Divider_31;\r
- LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;\r
- LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;\r
- LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;\r
-\r
- \r
- /* Initialize the LCD */\r
- LCD_Init(&LCD_InitStruct);\r
- \r
- LCD_MuxSegmentCmd(ENABLE);\r
- \r
- /* To set contrast to mean value */\r
- LCD_ContrastConfig(LCD_Contrast_Level_4);\r
- \r
- LCD_DeadTimeConfig(LCD_DeadTime_0);\r
- LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);\r
-\r
- /* Wait Until the LCD FCR register is synchronized */\r
- LCD_WaitForSynchro();\r
- \r
- /* Enable LCD peripheral */\r
- LCD_Cmd(ENABLE);\r
- \r
- /* Wait Until the LCD is enabled */\r
- while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)\r
- {\r
- }\r
- /*!< Wait Until the LCD Booster is ready */ \r
- while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)\r
- {\r
- } \r
-\r
- LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
- LCD_GLASS_Clear();\r
-}\r
-\r
-/**\r
- * @brief To initialize the LCD pins\r
- * @caller main\r
- * @param None\r
- * @retval None\r
- */\r
-\r
-void LCD_GLASS_Configure_GPIO(void)\r
-{\r
- GPIO_InitTypeDef GPIO_InitStructure;\r
- \r
-/* Enable GPIOs clock */ \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
- RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);\r
-\r
- \r
-/* Configure Output for LCD */\r
-/* Port A */\r
- GPIO_StructInit(&GPIO_InitStructure);\r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOA, &GPIO_InitStructure);\r
-\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
- \r
-/* Configure Output for LCD */\r
-/* Port B */ \r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
- | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOB, &GPIO_InitStructure);\r
- \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
- \r
-/* Configure Output for LCD */\r
-/* Port C*/ \r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
- | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
- GPIO_Init( GPIOC, &GPIO_InitStructure); \r
- \r
-\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
-\r
-/* Disable GPIOs clock */ \r
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
- RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);\r
- \r
-}\r
-\r
-/**\r
- * @brief LCD contrast setting min-->max-->min by pressing user button\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_contrast()\r
-{\r
- uint32_t contrast ;\r
- \r
- /* To get the actual contrast value in register */\r
- contrast = LCD->FCR & LCD_Contrast_Level_7;\r
- \r
- while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)\r
- {\r
- contrast += LCD_Contrast_Level_1; \r
- \r
- if (contrast > LCD_Contrast_Level_7)\r
- contrast=LCD_Contrast_Level_0;\r
- \r
- LCD_ContrastConfig(contrast);\r
- Delay(100);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Setting bar on LCD, writes bar value in LCD frame buffer \r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_bar()\r
-{\r
- \r
- LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;\r
-/* bar1 bar3 */\r
- LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);\r
- \r
-/*bar0 bar2 */\r
- LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);\r
- \r
-}\r
-\r
-/**\r
- * @brief Converts an ascii char to the a LCD digit.\r
- * @param c: a char to display.\r
- * @param point: a point to add in front of char\r
- * This parameter can be: POINT_OFF or POINT_ON\r
- * @param column : flag indicating if a column has to be add in front\r
- * of displayed character.\r
- * This parameter can be: COLUMN_OFF or COLUMN_ON.\r
- * @param digit array with segment \r
- * @retval None\r
- */\r
-static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)\r
-{\r
- uint16_t ch = 0 ;\r
- uint8_t i,j;\r
- \r
- switch (*c)\r
- {\r
- case ' ' : \r
- ch = 0x00;\r
- break;\r
- \r
- case '*':\r
- ch = star;\r
- break;\r
- \r
- case 'µ' :\r
- ch = C_UMAP;\r
- break;\r
- \r
- case 'm' :\r
- ch = C_mMap;\r
- break;\r
- \r
- case 'n' :\r
- ch = C_nMap;\r
- break; \r
- \r
- case '-' :\r
- ch = C_minus;\r
- break;\r
- \r
- case '/' :\r
- ch = C_slatch;\r
- break; \r
- \r
- case '°' :\r
- ch = C_percent_1;\r
- break; \r
- case '%' :\r
- ch = C_percent_2; \r
- break;\r
- case 255 :\r
- ch = C_full;\r
- break ;\r
- \r
- case '0':\r
- case '1':\r
- case '2':\r
- case '3':\r
- case '4':\r
- case '5':\r
- case '6':\r
- case '7':\r
- case '8':\r
- case '9': \r
- ch = NumberMap[*c-0x30]; \r
- break;\r
- \r
- default:\r
- /* The character c is one letter in upper case*/\r
- if ( (*c < 0x5b) && (*c > 0x40) )\r
- {\r
- ch = CapLetterMap[*c-'A'];\r
- }\r
- /* The character c is one letter in lower case*/\r
- if ( (*c <0x7b) && ( *c> 0x60) )\r
- {\r
- ch = CapLetterMap[*c-'a'];\r
- }\r
- break;\r
- }\r
- \r
- /* Set the digital point can be displayed if the point is on */\r
- if (point)\r
- {\r
- ch |= 0x0002;\r
- }\r
-\r
- /* Set the "COL" segment in the character that can be displayed if the column is on */\r
- if (column)\r
- {\r
- ch |= 0x0020;\r
- } \r
-\r
- for (i = 12,j=0 ;j<4; i-=4,j++)\r
- {\r
- digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD frame buffer.\r
- * @param ch: the character to display.\r
- * @param point: a point to add in front of char\r
- * This parameter can be: POINT_OFF or POINT_ON\r
- * @param column: flag indicating if a column has to be add in front\r
- * of displayed character.\r
- * This parameter can be: COLUMN_OFF or COLUMN_ON. \r
- * @param position: position in the LCD of the caracter to write [0:7]\r
- * @retval None\r
- * @par Required preconditions: The LCD should be cleared before to start the\r
- * write operation. \r
- */\r
-void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)\r
-{\r
- uint8_t digit[4]; /* Digit frame buffer */\r
- \r
-/* To convert displayed character in segment in array digit */\r
- LCD_Conv_Char_Seg(ch,point,column,digit);\r
-\r
- \r
- switch (position)\r
- {\r
- /* Position 1 on LCD (Digit1)*/\r
- case 1:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D \r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N\r
-\r
- break;\r
- \r
- /* Position 2 on LCD (Digit2)*/\r
- case 2:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; \r
- LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;\r
- \r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N\r
- \r
- break;\r
- \r
- /* Position 3 on LCD (Digit3)*/\r
- case 3:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N\r
- \r
- break;\r
- \r
- /* Position 4 on LCD (Digit4)*/\r
- case 4:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;\r
- \r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P\r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N\r
- \r
- break;\r
- \r
- /* Position 5 on LCD (Digit5)*/\r
- case 5:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N\r
- \r
- break;\r
- \r
- /* Position 6 on LCD (Digit6)*/\r
- case 6:\r
- LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;\r
- LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;\r
-\r
- LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E \r
- LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D\r
- LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P \r
- LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N\r
- \r
- break;\r
- \r
- default:\r
- break;\r
- }\r
-\r
-/* Refresh LCD bar */\r
- LCD_bar();\r
-\r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD RAM.\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @retval None\r
- */\r
-void LCD_GLASS_DisplayString(uint8_t* ptr)\r
-{\r
- uint8_t i = 0x01;\r
-\r
- /* wait for LCD Ready */ \r
- while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
- \r
- /* Send the string character by character on lCD */\r
- while ((*ptr != 0) & (i < 8))\r
- {\r
- /* Display one character on LCD */\r
- LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);\r
-\r
- /* Point on the next character */\r
- ptr++;\r
-\r
- /* Increment the character counter */\r
- i++;\r
- }\r
-\r
- /* Update the LCD display */\r
- LCD_UpdateDisplayRequest();\r
-}\r
-\r
-/**\r
- * @brief This function writes a char in the LCD RAM.\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @retval None\r
- * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag\r
- */\r
-void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)\r
-{\r
- uint8_t i = 0x01;\r
- uint8_t char_tmp;\r
-\r
- /* TO wait LCD Ready */ \r
- while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
- \r
- /* Send the string character by character on lCD */\r
- while ((*ptr != 0) & (i < 8))\r
- { \r
- char_tmp = (*ptr) & 0x00ff;\r
- \r
- switch ((*ptr) & 0xf000)\r
- {\r
- case DOT:\r
- /* Display one character on LCD with decimal point */\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);\r
- break;\r
- case DOUBLE_DOT:\r
- /* Display one character on LCD with decimal point */\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);\r
- break;\r
- default:\r
- LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); \r
- break;\r
- }/* Point on the next character */\r
- ptr++;\r
- \r
- /* Increment the character counter */\r
- i++;\r
- }\r
- /* Update the LCD display */\r
- LCD_UpdateDisplayRequest();\r
-}\r
-\r
-/**\r
- * @brief This function Clear the whole LCD RAM.\r
- * @param None\r
- * @retval None\r
- */\r
-void LCD_GLASS_Clear(void)\r
-{\r
- uint32_t counter = 0;\r
- \r
- /* TO wait LCD Ready */ \r
- while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
- \r
- for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)\r
- {\r
- LCD->RAM[counter] = 0;\r
- }\r
-\r
- /* Update the LCD display */\r
- LCD_UpdateDisplayRequest();\r
- \r
-}\r
-\r
-/**\r
- * @brief Display a string in scrolling mode\r
- * @param ptr: Pointer to string to display on the LCD Glass.\r
- * @param nScroll: Specifies how many time the message will be scrolled\r
- * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives\r
- * higher speed \r
- * @retval None\r
- * @par Required preconditions: The LCD should be cleared before to start the\r
- * write operation.\r
- */\r
-void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)\r
-{\r
- uint8_t Repetition;\r
- uint8_t Char_Nb;\r
- uint8_t* ptr1;\r
- uint8_t str[7]="";\r
- uint8_t Str_size;\r
- \r
- if (ptr == 0) return;\r
-\r
-/* To calculate end of string */\r
- for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;\r
- \r
- ptr1 = ptr;\r
- \r
- LCD_GLASS_DisplayString(ptr);\r
- Delay(ScrollSpeed);\r
- \r
-/* To shift the string for scrolling display*/\r
- for (Repetition=0; Repetition<nScroll; Repetition++)\r
- {\r
- for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)\r
- {\r
- *(str) =* (ptr1+((Char_Nb+1)%Str_size));\r
- *(str+1) =* (ptr1+((Char_Nb+2)%Str_size));\r
- *(str+2) =* (ptr1+((Char_Nb+3)%Str_size));\r
- *(str+3) =* (ptr1+((Char_Nb+4)%Str_size));\r
- *(str+4) =* (ptr1+((Char_Nb+5)%Str_size));\r
- *(str+5) =* (ptr1+((Char_Nb+6)%Str_size));\r
- LCD_GLASS_Clear();\r
- LCD_GLASS_DisplayString(str);\r
- \r
- /* user button pressed stop the scrolling sentence */\r
- if (KeyPressed)\r
- return; \r
- Delay(ScrollSpeed);\r
- } \r
- }\r
-\r
-}\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file stm32l_discovery_lcd.h\r
- * @author Microcontroller Division\r
- * @version V1.0.3\r
- * @date May-2013\r
- * @brief This file contains all the functions prototypes for the glass LCD\r
- * firmware driver.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __stm32l_discovery_lcd\r
-#define __stm32l_discovery_lcd\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h" \r
-#include "discover_board.h"\r
-\r
-/* Define for scrolling sentences*/\r
-#define SCROLL_SPEED 75\r
-#define SCROLL_SPEED_L 600\r
-#define SCROLL_NUM 1\r
-\r
-/* Define for character '.' */\r
-#define POINT_OFF FALSE\r
-#define POINT_ON TRUE\r
-\r
-/* Define for caracter ":" */\r
-#define COLUMN_OFF FALSE\r
-#define COLUMN_ON TRUE\r
-\r
-#define DOT 0x8000 /* for add decimal point in string */\r
-#define DOUBLE_DOT 0x4000 /* for add decimal point in string */\r
-\r
-\r
-/* =========================================================================\r
- LCD MAPPING\r
- =========================================================================\r
- A\r
- _ ----------\r
-COL |_| |\ |J /|\r
- F| H | K |B\r
- _ | \ | / |\r
-COL |_| --G-- --M--\r
- | /| \ |\r
- E| Q | N |C\r
- _ | / |P \| \r
-DP |_| ----------- \r
- D \r
-\r
- An LCD character coding is based on the following matrix:\r
- { E , D , P , N }\r
- { M , C , COL , DP}\r
- { B , A , K , J }\r
- { G , F , Q , H }\r
-\r
- The character 'A' for example is:\r
- -------------------------------\r
-LSB { 1 , 0 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
- { 1 , 1 , 0 , 0 }\r
-MSB { 1 , 1 , 0 , 0 }\r
- -------------------\r
- 'A' = F E 0 0 hexa\r
-\r
-*/\r
-/* Macros used for set/reset bar LCD bar */\r
-#define BAR0_ON t_bar[1] |= 8\r
-#define BAR0_OFF t_bar[1] &= ~8\r
-#define BAR1_ON t_bar[0] |= 8\r
-#define BAR1_OFF t_bar[0] &= ~8\r
-#define BAR2_ON t_bar[1] |= 2\r
-#define BAR2_OFF t_bar[1] &= ~2\r
-#define BAR3_ON t_bar[0] |= 2 \r
-#define BAR3_OFF t_bar[0] &= ~2 \r
-\r
-/* code for 'µ' character */\r
-#define C_UMAP 0x6084\r
-\r
-/* code for 'm' character */\r
-#define C_mMap 0xb210\r
-\r
-/* code for 'n' character */\r
-#define C_nMap 0x2210\r
-\r
-/* constant code for '*' character */\r
-#define star 0xA0DD\r
-\r
-/* constant code for '-' character */\r
-#define C_minus 0xA000\r
-\r
-/* constant code for '/' */\r
-#define C_slatch 0x00c0\r
-\r
-/* constant code for ° */\r
-#define C_percent_1 0xec00\r
-\r
-/* constant code for small o */\r
-#define C_percent_2 0xb300\r
-\r
-#define C_full 0xffdd\r
-\r
-void LCD_bar(void);\r
-void LCD_GLASS_Init(void);\r
-void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);\r
-void LCD_GLASS_DisplayString(uint8_t* ptr);\r
-void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);\r
-void LCD_GLASS_ClearChar(uint8_t position);\r
-void LCD_GLASS_Clear(void);\r
-void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);\r
-void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);\r
-void LCD_GLASS_Configure_GPIO(void);\r
-\r
-#endif /* stm32l_discovery_lcd*/\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_functions.c\r
- * @author Microcontroller Division\r
- * @version V1.0.3\r
- * @date May-2013\r
- * @brief Discover demo functions\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-\r
-/* stm32l1xxx std peripheral drivers headers*/ \r
-#include "stm32l1xx_exti.h"\r
-#include "misc.h"\r
-\r
-/* touch sensing library headers*/ \r
-//#include "stm32_tsl_api.h" -- superseded\r
-//#include "stm32l15x_tsl_ct_acquisition.h" -- superseded\r
-#include "tsl.h"\r
-#include "tsl_user.h"\r
-/* discover application headers*/ \r
-#include "discover_board.h"\r
-#include "discover_functions.h"\r
-#include "stm32l_discovery_lcd.h"\r
-#include "icc_measure.h"\r
- \r
-/*Variables placed in DataFlash */\r
-\r
-/* ADC converter value for Bias current value*/\r
-#if (defined ( __CC_ARM ))\r
-uint8_t Bias_Current __attribute__((at(0x08080000))); \r
-#elif (defined (__ICCARM__))\r
-uint8_t Bias_Current @ ".DataFlash" ; \r
-#elif (defined (__GNUC__))\r
-/* ADC converter value for Bias current value*/\r
-uint8_t Bias_Current __attribute__((section(".DataFlash")));\r
-#endif\r
-\r
-/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */\r
-#if (defined ( __CC_ARM ))\r
-bool self_test __attribute__((at(0x08080004))); \r
-#elif (defined (__ICCARM__))\r
-bool self_test @ ".DataFlash" ;\r
-#elif (defined (__GNUC__))\r
-/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */\r
-bool self_test __attribute__((section(".DataFlash")));\r
-#endif\r
-\r
-extern float Current_STBY;\r
-extern uint8_t t_bar[2];\r
-extern uint16_t Int_CurrentSTBY;\r
-\r
-/* Used for indicate that the automatic test is ON (set in interrupt handler).*/\r
-\r
-/* To indicate if user button function is actived*/\r
-bool UserButton ;\r
-/* Used for detect keypressed*/\r
-extern volatile bool KeyPressed;\r
-\r
-\r
-/**\r
- * @brief automatic test for VDD \r
- * @caller auto_test\r
- * @param None\r
- * @retval None\r
- */\r
-void test_vdd(void)\r
-{\r
- uint16_t vdd_test;\r
- uint16_t Message[6];\r
- \r
- /* Display test name*/\r
- LCD_GLASS_DisplayString(" VDD ");\r
- DELAY;\r
- /* get VDD voltage value */ \r
- vdd_test = (int)Vref_measure();\r
- DELAY;\r
- /* Check if value is correct */ \r
- if ((vdd_test>VCC_MAX) || (vdd_test<VCC_MIN))\r
- {\r
- /* if not correct stay in following infinit loop -- Press reset for exit */\r
- while(1)\r
- {\r
- /* Display VDD ERROR message*/\r
- LCD_GLASS_ScrollSentence("VDD ERROR ",1,SCROLL_SPEED); \r
- DELAY;\r
- /*convert vdd_test value in char and stor it into Message */\r
- convert_into_char (vdd_test, Message);\r
- /* Add unit and decimal point to Message */\r
- Message[5] = 'V';\r
- Message[4] = ' ';\r
- Message[1] |= DOT; \r
- Message[0] = ' ';\r
- /*Display Message*/ \r
- LCD_GLASS_DisplayStrDeci(Message); \r
- DELAY;\r
- DELAY; \r
- }\r
- }\r
- /* Display VDD OK message*/\r
- LCD_GLASS_DisplayString("VDD OK");\r
- DELAY ;\r
-}\r
-\r
-/**\r
- * @brief Automatic test current in Run Mode \r
- * @caller auto_test\r
- * @param None\r
- * @retval None\r
- */ \r
-void test_icc_Run(void)\r
-{\r
- uint16_t icc_test;\r
- uint16_t Message[6];\r
- \r
- /* Display test name*/\r
- LCD_GLASS_DisplayString("RUN ");\r
- DELAY;\r
- \r
- /* get ICC current value in RUN mode*/ \r
- icc_test = (int)Icc_RUN();\r
- DELAY;\r
- /* Check if value is correct */ \r
- if ((icc_test>ICC_RUN_MAX) || (icc_test<ICC_RUN_MIN))\r
- {\r
- /* if not correct stay in following infinit loop -- Press reset for exit */\r
- while (1)\r
- {\r
- KeyPressed = FALSE;\r
- /* Display RUN ERROR message*/\r
- LCD_GLASS_ScrollSentence("RUN ERROR ",1,SCROLL_SPEED); \r
- DELAY;\r
- /*convert icc_test value in char and stor it into tab */\r
- convert_into_char((uint32_t)(icc_test), Message);\r
- /* Add unit and decimal point to Message */\r
- Message[5] = 'A';\r
- Message[4] = 'm';\r
- Message[3] = ' ';\r
- Message[0] |= DOT;\r
- /*Display Message*/ \r
- LCD_GLASS_DisplayStrDeci(Message);\r
- DELAY;\r
- DELAY;\r
- }\r
- }\r
- /* Display RUN OK message*/\r
- LCD_GLASS_DisplayString("RUN OK");\r
- DELAY;\r
-}\r
-\r
-/**\r
- * @brief Automatic test bias value\r
- * @caller auto_test\r
- * @param None\r
- * @retval None\r
- */ \r
-void test_Bias(void)\r
-{\r
- float Current = 0;\r
- /* Display test name*/\r
- LCD_GLASS_DisplayString("BIAS ");\r
- DELAY;\r
- /* Get operational amplifier BIAS current value*/ \r
- Current = Bias_Current * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- display_MuAmp((uint32_t)Current);\r
- DELAY;\r
- /* Check if value is correct */ \r
- if ((Bias_Current > ICC_BIAS_MAX) || (Bias_Current == 0 ))\r
- {\r
- /* if not correct stay in following infinit loop */\r
- while (1)\r
- {\r
- KeyPressed = FALSE;\r
- /* Display BIAS ERROR message and BIAS current*/\r
- LCD_GLASS_ScrollSentence("BIAS ERROR ",1,SCROLL_SPEED);\r
- DELAY;\r
- display_MuAmp((uint32_t)Current);\r
- DELAY;\r
- DELAY;\r
- }\r
- }\r
- /* Display BIAS OK message*/\r
- LCD_GLASS_DisplayString("BIASOK");\r
- DELAY;\r
-}\r
-\r
-/**\r
- * @brief Automatic test current in STOP Mode\r
- * @caller auto_test\r
- * @param None\r
- * @retval None\r
- */\r
-void test_icc_STOP(void)\r
-{\r
- uint16_t icc_test;\r
- /* Display test name*/\r
- LCD_GLASS_DisplayString("STOP ");\r
- DELAY;\r
- \r
- /* Get operational Icc current value in Stop mode no RTC*/ \r
- icc_test = (int)Icc_Stop_NoRTC();\r
- DELAY;\r
- /* Test if value is correct */\r
- if ((icc_test>ICC_STOP_MAX) || (icc_test<ICC_STOP_MIN))\r
- {\r
- /* if not correct stay in following infinite loop */\r
- while (1)\r
- {\r
- KeyPressed = FALSE;\r
- /* Display ICC STOP ERROR message*/\r
- LCD_GLASS_ScrollSentence("ICC STOP ERROR ",1,SCROLL_SPEED);\r
- DELAY;\r
- /* Display ICC STOPvalue*/\r
- display_MuAmp((uint32_t)icc_test);\r
- DELAY;\r
- DELAY;\r
- }\r
- }\r
- /* Display STOP OK message*/\r
- LCD_GLASS_DisplayString("STOPOK");\r
- DELAY;\r
-}\r
-\r
-\r
-/**\r
- * @brief Automatic test current in STBY Mode\r
- * @caller auto_test\r
- * @param None\r
- * @retval None\r
- */\r
-void test_icc_STBY(void)\r
-{\r
- /* Display test name*/\r
- LCD_GLASS_DisplayString("STBY ");\r
- DELAY;\r
- /* Current value measured in Standby mode*/ \r
- ADC_Icc_Test(MCU_STBY);\r
- /* No Return software reset performed in ADC_Icc_Test function */\r
-}\r
-\r
-/**\r
- * @brief Run auto test\r
- * @caller main \r
- * @param None\r
- * @retval None\r
- */ \r
-void auto_test(void)\r
-{\r
- uint16_t tab[6]={0x20,0x20,0x20,0x20,0x20,0x20};\r
- \r
- AUTOTEST(TRUE) ;\r
- \r
- /* Switch off leds*/\r
- GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
- GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
- \r
- /* reset LCD bar indicator*/\r
- BAR0_OFF;\r
- BAR1_OFF;\r
- BAR2_OFF;\r
- BAR3_OFF;\r
- \r
- /* To display version */\r
- LCD_GLASS_DisplayString(" TEST ");\r
- DELAY;\r
- STR_VERSION;\r
- LCD_GLASS_DisplayStrDeci(tab);\r
- DELAY;\r
- DELAY;\r
- \r
- /* And launch the tests*/\r
- test_vdd();\r
- test_icc_Run();\r
- test_Bias();\r
- test_icc_STOP();\r
- test_icc_STBY();\r
- \r
- /* Infinite loop: Press reset button at the end of test for exit*/\r
- while (1)\r
- {\r
- LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);\r
- KeyPressed = FALSE;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Second part of Run auto test (run after sw reset)\r
- * @caller main after RESET \r
- * @param None\r
- * @retval None\r
- */ \r
-void auto_test_part2(void)\r
-{\r
- float Current_STBY;\r
- \r
- /* Substract operational amplifier bias current from mesured standby current*/\r
- if ( Int_CurrentSTBY > Bias_Current )\r
- Int_CurrentSTBY -= Bias_Current;\r
- /* convert value in uA */ \r
- Current_STBY = Int_CurrentSTBY * Vdd_appli()/ADC_CONV; \r
- Current_STBY *= 20L;\r
- /*Display Standby Icc current value*/\r
- display_MuAmp((uint32_t)Current_STBY);\r
- DELAY;\r
- /* Test if value is correct */\r
- if ((Current_STBY > ICC_STBY_MAX) || (Current_STBY < ICC_STBY_MIN))\r
- {\r
- /* if not correct stay in following infinite loop */\r
- while (1)\r
- {\r
- KeyPressed = FALSE;\r
- /* Display ICC STBY error message */ \r
- LCD_GLASS_ScrollSentence("ICC STBY ERROR ",1,SCROLL_SPEED); \r
- DELAY;\r
- /* Display ICC STBY current */\r
- display_MuAmp((uint32_t)Current_STBY);\r
- DELAY;\r
- DELAY;\r
- }\r
- }\r
- /* Display ICC STBY test OK*/ \r
- LCD_GLASS_DisplayString("STBYOK");\r
- DELAY; \r
- \r
- /* Infinite loop: Press reset button at the end of autotest to restart application*/\r
- while (1)\r
- {\r
- LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);\r
- KeyPressed = FALSE;\r
- }\r
-}\r
-/**\r
- * @brief Measures the BIAS current PJ1 Must be on OFF position\r
- * @caller main \r
- * @param None\r
- * @retval None\r
- */ \r
-void Bias_measurement(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- /* indicate that applicartion run in ** BIAS CURRENT ** mode */\r
- LCD_GLASS_ScrollSentence(" ** BIAS CURRENT ** JP1 OFF **",1,SCROLL_SPEED); \r
- \r
- /* Get operational amplifier Bias current value */\r
- MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
- \r
- /* convert mesured value in uA*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- \r
- /*display bias current value */\r
- display_MuAmp((uint32_t)Current);\r
-\r
- /* unlock E²Prom write access*/\r
- DATA_EEPROM_Unlock();\r
- \r
- /* Store the value in E²Prom for application needs*/\r
- DATA_EEPROM_FastProgramByte((uint32_t)&Bias_Current, MeasurINT) ;\r
- \r
- /* Lock back E²PROM write access */\r
- DATA_EEPROM_Lock(); \r
- \r
- /* Infinite loop: BIAS current display -- Press reset button in order to restart application*/\r
- while (1) \r
- { \r
- /* Get operational amplifier Bias current value */\r
- MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
- /* convert mesured value in uA*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- /*display bias current value */\r
- display_MuAmp((uint32_t)Current);\r
- Delay(800) ;\r
- }\r
-}\r
-\r
-/**\r
- * @brief converts a 32bit unsined int into ASCII \r
- * @caller several callers for display values\r
- * @param Number digit to displays\r
- * p_tab values in array in ASCII \r
- * @retval None\r
- */ \r
-void convert_into_char(uint32_t number, uint16_t *p_tab)\r
-{\r
- uint16_t units=0, tens=0, hundreds=0, thousands=0, misc=0;\r
- \r
- units = (((number%10000)%1000)%100)%10;\r
- tens = ((((number-units)/10)%1000)%100)%10;\r
- hundreds = (((number-tens-units)/100))%100%10;\r
- thousands = ((number-hundreds-tens-units)/1000)%10;\r
- misc = ((number-thousands-hundreds-tens-units)/10000);\r
- \r
- *(p_tab+4) = units + 0x30;\r
- *(p_tab+3) = tens + 0x30;\r
- *(p_tab+2) = hundreds + 0x30;\r
- *(p_tab+1) = thousands + 0x30;\r
- *(p_tab) = misc + 0x30;\r
-\r
-}\r
-\r
-/**\r
- * @brief Function to return the VDD measurement\r
- * @caller All measurements: VDD display or Current\r
- *\r
- * Method for VDD measurement:\r
- * The VREFINT is not stored in memory.\r
- * In this case:\r
- * Vdd_appli = (Theorical_Vref/Vref mesure) * ADC_Converter\r
- * Theorical_Vref = 1.224V\r
- * ADC_Converter 4096\r
- * ---> LSBIdeal = VREF/4096 or VDA/4096\r
- * @param None \r
- * @retval VDD measurements\r
- */\r
-float Vdd_appli(void)\r
-{\r
- uint16_t MeasurINT ;\r
-\r
- float f_Vdd_appli ;\r
- \r
- /*Read the BandGap value on ADC converter*/\r
- MeasurINT = ADC_Supply(); \r
- \r
- /* We use the theorical value */\r
- f_Vdd_appli = (VREF/MeasurINT) * ADC_CONV;\r
-\r
- /* convert Vdd_appli into mV */ \r
- f_Vdd_appli *= 1000L;\r
- \r
- return f_Vdd_appli;\r
-}\r
-\r
-/**\r
- * @brief Function to measure VDD\r
- * @caller main\r
- * @param None \r
- * @retval Vdd value in mV\r
- */\r
-uint16_t Vref_measure(void)\r
-{\r
- uint16_t tab[6]; \r
- uint16_t Vdd_mV ;\r
- \r
- Vdd_mV = (uint16_t)Vdd_appli();\r
-\r
- convert_into_char (Vdd_mV, tab);\r
- \r
- /* To add unit and decimal point */\r
- tab[5] = 'V';\r
- tab[4] = ' ';\r
- tab[1] |= DOT; /* To add decimal point for display in volt */\r
- tab[0] = ' ';\r
- \r
- LCD_GLASS_DisplayStrDeci(tab);\r
-\r
- return Vdd_mV;\r
-}\r
-\r
-/**\r
- * @brief funtion to display the current in µA\r
- * @caller several funcions\r
- * @param Current value.\r
- * @retval none\r
- */ \r
-void display_MuAmp (uint32_t Current)\r
-{\r
- uint16_t tab[6];\r
- \r
- convert_into_char(Current, tab);\r
- tab[5] = 'A';\r
- tab[4] = 'µ';\r
- \r
-/* Test the significant digit for displays 3 or 4 digits*/\r
- if ( tab[0] != '0')\r
- {\r
- tab[1] |= DOT; /* To add decimal point */\r
- } else {\r
- /* To shift for suppress '0' before decimal */\r
- tab[0] = tab[1] ; \r
- tab[0] |= DOT ;\r
- tab[1] = tab[2] ;\r
- tab[2] = tab[3] ; \r
- tab[3] = ' ';\r
- }\r
- \r
- LCD_GLASS_DisplayStrDeci(tab);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in RUN mode\r
- * @caller main and test_icc_RUN\r
- * @param none\r
- * @retval Current (mA)\r
- */ \r
-float Icc_RUN(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- uint16_t tab[6]; \r
- /* Get Icc current value in Run mode*/ \r
- MeasurINT = ADC_Icc_Test(MCU_RUN);\r
- /* Convert value in mA*/ \r
- Current = MeasurINT * Vdd_appli()/ADC_CONV;\r
- Current *= 100L; \r
- /* Convert value in ASCII and store it into tab*/\r
- convert_into_char((uint32_t)(Current), tab);\r
- /* Add unit and decimal point */\r
- tab[5] = 'A';\r
- tab[4] = 'm';\r
- tab[3] = ' ';\r
- tab[0] |= DOT; \r
- /* Display mesured value */\r
- LCD_GLASS_DisplayStrDeci(tab);\r
- \r
- return (Current);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in SLEEP mode\r
- * @caller main\r
- * @param none\r
- * @retval Current (mA)\r
- */ \r
-float Icc_SLEEP(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- uint16_t tab[6]; \r
- \r
- /* Get Icc current value in Sleep mode*/ \r
- MeasurINT = ADC_Icc_Test(MCU_SLEEP);\r
- /* Substract operational amplifier bias current from value*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- /* Convert value in mA*/ \r
- Current *= 100L;\r
- /* Convert value in ASCII and store it into tab*/\r
- convert_into_char((uint32_t)(Current), tab);\r
- /* Add unit and decimal point */\r
- tab[5] = 'A';\r
- tab[4] = 'm';\r
- tab[3] = ' ';\r
- tab[0] |= DOT; \r
- /*Display mesured value */\r
- LCD_GLASS_DisplayStrDeci(tab);\r
- /* Return value in mA*/\r
- return(Current);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in Low power\r
- * @caller main\r
- * @param none\r
- * @retval Current (uA)\r
- */ \r
-float Icc_LPRUN(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
-\r
- /* Get Icc current value in Low power mode*/\r
- MeasurINT = ADC_Icc_Test(MCU_LP_RUN);\r
- /* Substract operational amplifier bias current from value*/\r
- if ( MeasurINT > Bias_Current )\r
- MeasurINT -= Bias_Current;\r
- /* Convert value in uA*/ \r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- /* Display mesured value */\r
- display_MuAmp((uint32_t)Current);\r
- /* Return value in uA*/ \r
- return(Current);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in Low power\r
- * @caller main\r
- * @param none\r
- * @retval Current (µA)\r
- */ \r
-float Icc_LPSLEEP(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- /* Get Icc current value in Low power sleep mode*/\r
- MeasurINT = ADC_Icc_Test(MCU_LP_SLEEP);\r
- /* Substract operational amplifier bias current from value*/\r
- if ( MeasurINT > Bias_Current )\r
- MeasurINT -= Bias_Current;\r
- /* Convert value in uA*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- /* Test if value is correct */\r
- if ((int) Current<MAX_CURRENT)\r
- {\r
- /* if correct : Display mesured value */\r
- display_MuAmp((uint32_t)Current);\r
- } else{\r
- /* if not correct : Display ERROR */\r
- LCD_GLASS_Clear();\r
- LCD_GLASS_DisplayString("Error");\r
- }\r
- /* Return value in uA*/\r
- return(Current);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in Stop mode with LCD ON\r
- * @caller main and test_icc_LCD\r
- * @param none\r
- * @retval Current (µA)\r
- */\r
-float Icc_STOP(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- \r
- /* Get Icc current value in STOP mode*/ \r
- MeasurINT = ADC_Icc_Test(MCU_STOP_RTC); \r
- /* Substract operational amplifier bias current from value*/\r
- if ( MeasurINT > Bias_Current )\r
- MeasurINT -= Bias_Current;\r
- /* Convert value in uA*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L; \r
- /* test if value is correct */\r
- if ((int) Current<MAX_CURRENT)\r
- {\r
- /* if correct : Display mesured value */\r
- display_MuAmp((uint32_t)Current);\r
- }\r
- else\r
- {\r
- /* if not correct : Display error if not in autotest */\r
- if (!self_test)\r
- {\r
- LCD_GLASS_Clear();\r
- LCD_GLASS_DisplayString("Error");\r
- }\r
- }\r
- /* Return value in uA*/\r
- return (Current);\r
-}\r
-\r
-/**\r
- * @brief funtion Current measurement in Stop mode with LCD OFF\r
- * @caller main\r
- * @param none\r
- * @retval none\r
- */\r
-float Icc_Stop_NoRTC(void)\r
-{\r
- float Current;\r
- uint16_t MeasurINT;\r
- \r
- /* Get Icc current value in STOP mode with no RTC */ \r
- MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
- /* Substract operational amplifier bias current from value*/\r
- if ( MeasurINT > Bias_Current )\r
- MeasurINT -= Bias_Current;\r
- /* Convert value in uA*/\r
- Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
- Current *= 20L;\r
- /* Display mesured value */ \r
- display_MuAmp((uint32_t)Current);\r
- /* Return value in uA*/\r
- return (Current);\r
-} \r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
\r
/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky low power\r
demo, or 0 to run the more comprehensive test and demo application. */\r
-#define configCREATE_LOW_POWER_DEMO 0\r
+#define configCREATE_LOW_POWER_DEMO 1\r
\r
/* A few settings are dependent on the configCREATE_LOW_POWER_DEMO setting. */\r
#if configCREATE_LOW_POWER_DEMO == 1\r
+++ /dev/null
- /**\r
- ******************************************************************************\r
- * @file discover_functions.h\r
- * @author Microcontroller Division\r
- * @version V1.0.3\r
- * @date May-2013\r
- * @brief This file contains measurement values and board\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __DISCOVER_FUNCTIONS_H\r
-#define __DISCOVER_FUNCTIONS_H\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx.h" \r
-\r
-#define DELAY Delay(150)\r
-#define TEMPO if(!KeyPressed) DELAY\r
-\r
-//#define SLIDER_DETECTED (sMCKeyInfo[0].Setting.b.DETECTED)\r
-//#define SLIDER_POSITION (sMCKeyInfo[0].UnScaledPosition)\r
-\r
-#define enableGlobalInterrupts() __set_PRIMASK(0);\r
-#define disableGlobalInterrupts() __set_PRIMASK(1);\r
-\r
-#define STR_VERSION tab[1] = 'V';tab[2] = '2'|DOT; tab[3] = '0'|DOT; tab[4] = '4'\r
-\r
-#define STATE_VREF 0\r
-#define STATE_SLIDER_VALUE 1\r
-#define STATE_SLIDER_BUTTON 2\r
-#define STATE_ICC_RUN 3\r
-#define STATE_ICC_LP_RUN 4\r
-#define STATE_ICC_STOP 5\r
-#define STATE_ICC_STBY 6\r
-\r
-#define MAX_STATE 7\r
-\r
-\r
-/* Theorically BandGAP 1.224volt */\r
-#define VREF 1.224L\r
-\r
-\r
-/*\r
- ADC Converter \r
- LSBIdeal = VREF/4096 or VDA/4096\r
-*/\r
-#define ADC_CONV 4096\r
-\r
-/*\r
- VDD Factory for VREFINT measurement \r
-*/\r
-#define VDD_FACTORY 3.0L\r
-\r
-#define MAX_CURRENT 99999\r
-\r
-/* AUTO TEST VALUE */\r
-\r
-#define VCC_MIN 2920 /* nominal Vcc/Vdd is 2.99V, allow 2.5% lower - Vref can be ~2% lower than 1.225 */\r
-#define VCC_MAX 3100\r
-#define ICC_RUN_MIN 6000\r
-#define ICC_RUN_MAX 11000 /* typical ICC_RUN is ~0.9mA */\r
-#define ICC_STOP_MIN 250\r
-#define ICC_STOP_MAX 800 /* typical ICC_STOP is 0.6uA */\r
-#define ICC_BIAS_MAX 30 /* ! converter value in decimal ! --> 3.0volts/4036* 30 = 21 mV */\r
-\r
-#define ICC_STBY_MIN 150 /* typical ICC_STAND BY is 0.3 uA */\r
-#define ICC_STBY_MAX 450 \r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macro ------------------------------------------------------------*/\r
-\r
-#define AUTOTEST(a) DATA_EEPROM_Unlock(); DATA_EEPROM_FastProgramByte((uint32_t)&self_test,a ) ; DATA_EEPROM_Lock() \r
- \r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-\r
-void Init_Port (void);\r
-void convert_into_char(uint32_t number, uint16_t *p_tab);\r
-void LPR_init(void);\r
-void Halt_Init(void);\r
-uint16_t Vref_measure(void);\r
-void Icc_measure(void);\r
-float Icc_RUN(void);\r
-float Icc_SLEEP(void);\r
-float Icc_LPRUN(void);\r
-float Icc_LPSLEEP(void);\r
-float Icc_STOP(void);\r
-float Icc_Stop_NoRTC(void);\r
-void Icc_STBY(void);\r
-float Icc_STBY_NoRTC(void);\r
-void auto_test(void);\r
-void Bias_measurement(void);\r
-void test_vdd(void);\r
-void test_icc_Run(void);\r
-void test_icc_STOP(void);\r
-void test_icc_STBY(void);\r
-void display_MuAmp (uint32_t);\r
-void FLASH_ProgramBias(uint8_t) ;\r
-float Vdd_appli(void);\r
-uint16_t wake_up_measurement (void);\r
-void RCC_Configuration(void);\r
-void Init_clocks(void);\r
-void Init_GPIOs (void);\r
-void TimingDelay_Decrement(void);\r
-void Delay(uint32_t nTime);\r
-void ExtraCode_StateMachine(void);\r
-void Config_Systick(void);\r
-void Config_Systick_50ms(void); \r
-void Button_value(void);\r
-void Slider_value(void);\r
-void auto_test_part2(void);\r
-\r
-#endif /* __DISCOVER_FUNCTIONS_H*/\r
-\r
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
/**\r
******************************************************************************\r
- * @file Project/STM32L1xx_StdPeriph_Template/main.h \r
+ * @file Project/STM32L1xx_StdPeriph_Template/main.h\r
* @author MCD Application Team\r
* @version V1.0.3\r
* @date May-2013\r
*\r
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
******************************************************************************\r
- */ \r
- \r
+ */\r
+\r
/* Define to prevent recursive inclusion -------------------------------------*/\r
#ifndef __MAIN_H\r
#define __MAIN_H\r
/* discovery board and specific drivers headers*/\r
#include "discover_board.h"\r
#include "icc_measure.h"\r
-#include "discover_functions.h"\r
#include "stm32l_discovery_lcd.h"\r
\r
\r
/**\r
******************************************************************************\r
- * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h \r
+ * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h\r
* @author MCD Application Team\r
* @version V1.0.3\r
* @date May-2013\r
*\r
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
******************************************************************************\r
- */ \r
+ */\r
\r
/* Define to prevent recursive inclusion -------------------------------------*/\r
#ifndef __STM32L1xx_CONF_H\r
\r
/* Includes ------------------------------------------------------------------*/\r
/* Comment the line below to disable peripheral header file inclusion */\r
-#include "stm32l1xx_adc.h"\r
-#include "stm32l1xx_crc.h"\r
-#include "stm32l1xx_comp.h"\r
-#include "stm32l1xx_dac.h"\r
-#include "stm32l1xx_dbgmcu.h"\r
-#include "stm32l1xx_dma.h"\r
+//#include "stm32l1xx_adc.h"\r
+//#include "stm32l1xx_crc.h"\r
+//#include "stm32l1xx_comp.h"\r
+//#include "stm32l1xx_dac.h"\r
+//#include "stm32l1xx_dbgmcu.h"\r
+//#include "stm32l1xx_dma.h"\r
#include "stm32l1xx_exti.h"\r
-#include "stm32l1xx_flash.h"\r
+//#include "stm32l1xx_flash.h"\r
#include "stm32l1xx_gpio.h"\r
#include "stm32l1xx_syscfg.h"\r
-#include "stm32l1xx_i2c.h"\r
-#include "stm32l1xx_iwdg.h"\r
+//#include "stm32l1xx_i2c.h"\r
+//#include "stm32l1xx_iwdg.h"\r
#include "stm32l1xx_lcd.h"\r
#include "stm32l1xx_pwr.h"\r
#include "stm32l1xx_rcc.h"\r
#include "stm32l1xx_rtc.h"\r
-#include "stm32l1xx_spi.h"\r
+//#include "stm32l1xx_spi.h"\r
#include "stm32l1xx_tim.h"\r
-#include "stm32l1xx_usart.h"\r
-#include "stm32l1xx_wwdg.h"\r
+//#include "stm32l1xx_usart.h"\r
+//#include "stm32l1xx_wwdg.h"\r
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
\r
/* Exported types ------------------------------------------------------------*/\r
/* Exported constants --------------------------------------------------------*/\r
-/* Uncomment the line below to expanse the "assert_param" macro in the \r
+/* Uncomment the line below to expanse the "assert_param" macro in the\r
Standard Peripheral Library drivers code */\r
/* #define USE_FULL_ASSERT 1 */\r
\r
\r
/**\r
* @brief The assert_param macro is used for function's parameters check.\r
- * @param expr: If expr is false, it calls assert_failed function which reports \r
- * the name of the source file and the source line number of the call \r
+ * @param expr: If expr is false, it calls assert_failed function which reports\r
+ * the name of the source file and the source line number of the call\r
* that failed. If expr is true, it returns no value.\r
* @retval None\r
*/\r
/* ST library functions. */\r
#include "stm32l1xx.h"\r
#include "discover_board.h"\r
-#include "discover_functions.h"\r
\r
/*-----------------------------------------------------------*/\r
\r
/* ST library functions. */\r
#include "stm32l1xx.h"\r
#include "discover_board.h"\r
-#include "discover_functions.h"\r
#include "stm32l_discovery_lcd.h"\r
\r
/* Priorities for the demo application tasks. */\r
*/\r
static void prvCheckTimerCallback( xTimerHandle xTimer );\r
\r
+/*\r
+ * Configure the LCD, then write welcome message.\r
+ */\r
+static void prvConfigureLCD( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
void main_full( void )\r
{\r
xTimerHandle xCheckTimer = NULL;\r
\r
+ /* The LCD is only used in the Full demo. */\r
+ prvConfigureLCD();\r
+\r
/* Start all the other standard demo/test tasks. They have not particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static void prvConfigureLCD( void )\r
+{\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Enable necessary clocks. */\r
+ RCC_AHBPeriphClockCmd( RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC, ENABLE );\r
+ RCC_APB1PeriphClockCmd( RCC_APB1Periph_LCD, ENABLE );\r
+ PWR_RTCAccessCmd( ENABLE );\r
+ RCC_LSEConfig( ENABLE );\r
+ RCC_RTCCLKConfig( RCC_RTCCLKSource_LSE );\r
+ RCC_RTCCLKCmd( ENABLE );\r
+\r
+ /* Configure Port A LCD Output pins as alternate function. */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure );\r
+\r
+ /* Select LCD alternate function for Port A LCD Output pins. */\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource1, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource2, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource3, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource8, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource9, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource10, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOA, GPIO_PinSource15, GPIO_AF_LCD );\r
+\r
+ /* Configure Port B LCD Output pins as alternate function */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure );\r
+\r
+ /* Select LCD alternate function for Port B LCD Output pins */\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource3, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource4, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource5, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource8, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource9, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource10, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource11, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource12, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource13, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource14, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOB, GPIO_PinSource15, GPIO_AF_LCD );\r
+\r
+ /* Configure Port C LCD Output pins as alternate function */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure );\r
+\r
+ /* Select LCD alternate function for Port B LCD Output pins */\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource0, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource1, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource2, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource3, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource6, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource7, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource8, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource9, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource10, GPIO_AF_LCD );\r
+ GPIO_PinAFConfig( GPIOC, GPIO_PinSource11, GPIO_AF_LCD );\r
+\r
+ LCD_GLASS_Init();\r
+ LCD_GLASS_DisplayString( "F'RTOS" );\r
+}\r
+\r
/* ST library functions. */\r
#include "stm32l1xx.h"\r
#include "discover_board.h"\r
-#include "discover_functions.h"\r
#include "stm32l_discovery_lcd.h"\r
\r
/* Priorities at which the Rx and Tx tasks are created. */\r
#include "stm32l1xx_it.h"\r
#include "stm32l1xx_exti.h"\r
#include "stm32l1xx_rtc.h"\r
-#include "discover_functions.h"\r
#include "discover_board.h"\r
#include "stm32l_discovery_lcd.h"\r
#include "tsl.h"\r
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