For proper displayport performance, scrambling has to be enabled, but
is turned off on DP501 by default.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+ dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
#ifdef CONFIG_SYS_DP501_VCAPCTRL0
i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);