orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
+#ifdef CONFIG_DEBUG_LL
+ bl setup_lowlevel_debug
+#endif
+
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 36864000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 85, 1, r0, r1
+ set_pinsel 88, 1, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 73728000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CLK_PERI
+ str r1, [r0]
+
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 127, 0, r0, r1
+ set_pinsel 128, 0, r0, r1
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 80000000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 70, 3, r0, r1
+ set_pinsel 71, 3, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE 115200
+#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
+#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
+
+ .macro init_debug_uart, ra, rb, rc
+ addruart \ra, \rb, \rc
+ mov \rb, #UART_LCR_WLEN8
+ strb \rb, [\ra, #0x11]
+ ldr \rb, =DIVISOR
+ str \rb, [\ra, #0x24]
+ .endm