arm: Move MAX_CPUS to Kconfig

Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 2648416629d013112fa362d541fd7b9425244b0a..e8264f54fb951105c5bd2b54b253acbfdba8b97e 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -9,6 +9,17 @@ config LS1_DEEP_SLEEP
        bool "Deep sleep"
        depends on ARCH_LS1021A
 
+config MAX_CPUS
+       int "Maximum number of CPUs permitted for LS102xA"
+       depends on ARCH_LS1021A
+       default 2
+       help
+         Set this number to the maximum number of possible CPUs in the SoC.
+         SoCs may have multiple clusters with each cluster may have multiple
+         ports. If some ports are reserved but higher ports are used for
+         cores, count the reserved ports. This will allocate enough memory
+         in spin table to properly handle all cores.
+
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index d2b1be87f925736a4c0495d6a3f7364054c87328..352d1d316ab88c35d7ce604c7bd6a326609fb204 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -37,4 +37,17 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
        bool "Workaround for PIN MUX erratum A010539"
 
+config MAX_CPUS
+       int "Maximum number of CPUs permitted for Layerscape"
+       default 4 if ARCH_LS1043A
+       default 4 if ARCH_LS1046A
+       default 16 if ARCH_LS2080A
+       default 1
+       help
+         Set this number to the maximum number of possible CPUs in the SoC.
+         SoCs may have multiple clusters with each cluster may have multiple
+         ports. If some ports are reserved but higher ports are used for
+         cores, count the reserved ports. This will allocate enough memory
+         in spin table to properly handle all cores.
+
 endmenu

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index a5c6c4cd267d758004f281ec5323957b7b97949f..572fa9469383dc8a0f5f67f8842d2d0ae7956016 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -30,7 +30,6 @@
 #define CONFIG_SYS_MEM_RESERVE_SECURE  (2048 * 1024)   /* 2MB */
 
 #ifdef CONFIG_LS2080A
-#define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             3
 #define CONFIG_SYS_FSL_HAS_DP_DDR              /* Runtime check to confirm */
@@ -171,7 +170,6 @@
 
 /* SoC related */
 #ifdef CONFIG_LS1043A
-#define CONFIG_MAX_CPUS                                4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
@@ -206,13 +204,11 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_MAX_CPUS                         1
 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
 #elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_MAX_CPUS                                4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index fab87740285c89f48271f01d2c37f1361ac2d39e..70cc7039f2a9f9cf6c22f211630d9f3afef2d443 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -123,7 +123,6 @@
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA
-#define CONFIG_MAX_CPUS                                2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1
 #define CONFIG_SYS_FSL_DDR_VER                 FSL_DDR_VER_5_0