ARM: atmel: sama5d4: can access DDR in interleave mode

The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>

diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
index 44798e612c3b2e04cb456aa1c85b09429baa8ec9..beec13db8c1396d792a74cc7d685e848493c9695 100644 (file)
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
        if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
                return 0;
 #endif