| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
#else
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
+#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000