ARM: AM43xx: GP_EVM: Add support for DDR3

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 1abbb07c961987eddded78dbf1dd44885a633e1f..d05e666a742f5a4e1d6920046d0ab511ebc8b709 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 
-       configure_mr(nr, 0);
-       configure_mr(nr, 1);
+       if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+               configure_mr(nr, 0);
+               configure_mr(nr, 1);
+       }
 }
 
 /**

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 5a3f2858cda7d1d152aae202874acd60a83ab8b0..cd6289b4fca0827e40819be8f7253137c25d8f18 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
                return 0;
 }
 
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
-       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-       return (readl(&emif->emif_sdram_config) &
-               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 {
        u32 mr;

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6af4b84e568bca75c8e3c5dee6fb8a524c08ada4..c1777dfdc9604b63be2e932b86182fe7ff91b54a 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -136,6 +136,14 @@
 #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
 
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
 /**
  * Configure DMM
  */

diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index 13a047fd72e337c96862eeba47a9c826ee449ca9..a1ffd49f795c151b2a40459b0c6e3685c0005da1 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -13,4 +13,16 @@
 #define AM33XX_GPIO2_BASE       0x481AC000
 #define AM33XX_GPIO3_BASE       0x481AE000
 
+#define GPIO_22                        22
+
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT  0
+#define GPIO_CTRL_DISABLEMODULE_MASK   (1 << 0)
+#define GPIO_CTRL_ENABLEMODULE         GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x)              (1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x)             (1 << x)
 #endif /* _GPIO_AM33xx_H */

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index e68c113e2800f7666190ca3afb262fbb9c0680b5..45668ca4dd737f7f0533f8bb363400dbf9f6e57d 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1160,6 +1160,20 @@ static inline u32 get_emif_rev(u32 base)
                >> EMIF_REG_MAJOR_REVISION_SHIFT;
 }
 
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+       return (readl(&emif->emif_sdram_config) &
+               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c) ({ if (!(c)) for (;;); })

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 5a013e3384598d1b4e28fdb7f75b0ac8848ba855..ed87cd97b0d6e7564550223c20973f770b448c8e 100644 (file)
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -16,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
 
@@ -179,10 +180,70 @@ const u32 ext_phy_ctrl_const_base_lpddr2[] = {
        0x08102040
 };
 
+const struct ctrl_ioregs ioregs_ddr3 = {
+       .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
+       .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+       .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+       .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
+       .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
+       .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
+       .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
+       .emif_sdram_config_ext  = 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+       .sdram_config                   = 0x638413B2,
+       .ref_ctrl                       = 0x00000C30,
+       .sdram_tim1                     = 0xEAAAD4DB,
+       .sdram_tim2                     = 0x266B7FDA,
+       .sdram_tim3                     = 0x107F8678,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x50074BE4,
+       .temp_alert_config              = 0x0,
+       .emif_ddr_phy_ctlr_1            = 0x0E084008,
+       .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
+       .emif_rd_wr_lvl_rmp_win         = 0x0,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x0,
+       .emif_rd_wr_lvl_ctl             = 0x0,
+       .emif_rd_wr_exec_thresh         = 0x00000405
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+       0x00400040,
+       0x00350035,
+       0x00350035,
+       0x00350035,
+       0x00350035,
+       0x00350035,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00340034,
+       0x00340034,
+       0x00340034,
+       0x00340034,
+       0x00340034,
+       0x0,
+       0x0,
+       0x40000000,
+       0x08102040
+};
+
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 {
-       *regs = ext_phy_ctrl_const_base_lpddr2;
-       *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+       if (board_is_eposevm()) {
+               *regs = ext_phy_ctrl_const_base_lpddr2;
+               *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+       } else if (board_is_gpevm()) {
+               *regs = ext_phy_ctrl_const_base_ddr3;
+               *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+       }
 
        return;
 }
@@ -280,9 +341,35 @@ void set_mux_conf_regs(void)
        enable_board_pin_mux();
 }
 
+static void enable_vtt_regulator(void)
+{
+       u32 temp;
+
+       /* enable module */
+       writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
+
+       /* enable output for GPIO0_22 */
+       writel(GPIO_SETDATAOUT(GPIO_22),
+              AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
+       temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+       temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
+       writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+}
+
 void sdram_init(void)
 {
-       config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+       /*
+        * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+        * GP EMV has 1GB DDR3 connected to EMIF
+        * along with VTT regulator.
+        */
+       if (board_is_eposevm()) {
+               config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+       } else if (board_is_gpevm()) {
+               enable_vtt_regulator();
+               config_ddr(0, &ioregs_ddr3, NULL, NULL,
+                          &ddr3_emif_regs_400Mhz, 0);
+       }
 }
 #endif
 

diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index a2d72dde5f56246f028a9dcb77e822207a5f7b36..810b1941db9d052321e79bd9987d48d1ad143661 100644 (file)
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = {
        {-1},
 };
 
+static struct module_pin_mux gpio0_22_pin_mux[] = {
+       {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)},       /* GPIO0_22 */
+       {-1},
+};
+
 void enable_uart0_pin_mux(void)
 {
        configure_module_pin_mux(uart0_pin_mux);
@@ -42,6 +47,9 @@ void enable_board_pin_mux(void)
 {
        configure_module_pin_mux(mmc0_pin_mux);
        configure_module_pin_mux(i2c0_pin_mux);
+
+       if (board_is_gpevm())
+               configure_module_pin_mux(gpio0_22_pin_mux);
 }
 
 void enable_i2c0_pin_mux(void)