arm: socfpga: cache: Enable PL310 L2 cache

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index de60bb2f069f36d03673c373ab8597a73bd5d268..c8986d9811d82c287d2e79a5b890a80d6104aa15 100644 (file)
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -27,6 +27,8 @@
 
 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE      32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET