}
#ifdef CONFIG_NAND
dtbsize = 0x20000;
- rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize,
+ rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
NULL, 0x20000, (u_char *)dtbaddr);
#else
char *dtbname = getenv("dtb");
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#ifndef CONFIG_SYS_NO_FLASH
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
printf("\n");
for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
- mtd = &nand_info[nand_dev];
+ mtd = nand_info[nand_dev];
if (!mtd->name || !mtd->size)
continue;
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
- *size = nand_info[num].size;
+ *size = nand_info[num]->size;
return 0;
}
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
struct mtd_info *mtd;
- mtd = &nand_info[id->num];
+ mtd = nand_info[id->num];
return mtd->erasesize;
#else
static int set_dev(int dev)
{
if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[dev].name) {
+ !nand_info[dev]->name) {
puts("No such device\n");
return -1;
}
if (nand_curr_device == dev)
return 0;
- printf("Device %d: %s", dev, nand_info[dev].name);
+ printf("Device %d: %s", dev, nand_info[dev]->name);
puts("... is now current device\n");
nand_curr_device = dev;
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
- board_nand_select_device(nand_info[dev].priv, dev);
+ board_nand_select_device(nand_info[dev]->priv, dev);
#endif
return 0;
{
int ret;
uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
- struct mtd_info *mtd = &nand_info[0];
+ struct mtd_info *mtd = nand_info[0];
char *cmd = argv[1];
if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
/* We don't care about size, or maxsize. */
if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
- MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+ MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
puts("Offset or partition name expected\n");
return 1;
}
static void nand_print_and_set_info(int idx)
{
- struct mtd_info *mtd = &nand_info[idx];
+ struct mtd_info *mtd = nand_info[idx];
struct nand_chip *chip = mtd->priv;
printf("Device %d: ", idx);
/* We grab the nand info object here fresh because this is usually
* called after arg_off_size() which can change the value of dev.
*/
- struct mtd_info *mtd = &nand_info[dev];
+ struct mtd_info *mtd = nand_info[dev];
loff_t maxoffset = offset + *size;
int badblocks = 0;
putc('\n');
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (nand_info[i].name)
+ if (nand_info[i]->name)
nand_print_and_set_info(i);
}
return 0;
* for another device is to be used.
*/
if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[dev].name) {
+ !nand_info[dev]->name) {
puts("\nno devices available\n");
return 1;
}
- mtd = &nand_info[dev];
+ mtd = nand_info[dev];
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", dev);
/* skip first two or three arguments, look for offset and size */
if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev].size) != 0)
+ nand_info[dev]->size) != 0)
return 1;
if (set_dev(dev))
return 1;
- mtd = &nand_info[dev];
+ mtd = nand_info[dev];
memset(&opts, 0, sizeof(opts));
opts.offset = off;
if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev].size))
+ nand_info[dev]->size))
return 1;
if (set_dev(dev))
return 1;
- mtd = &nand_info[dev];
+ mtd = nand_info[dev];
if (argc > 4 && !str2long(argv[4], &pagecount)) {
printf("'%s' is not a number\n", argv[4]);
if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
&size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev].size) != 0)
+ nand_info[dev]->size) != 0)
return 1;
if (set_dev(dev))
rwsize = size;
}
- mtd = &nand_info[dev];
+ mtd = nand_info[dev];
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev].size) < 0)
+ nand_info[dev]->size) < 0)
return 1;
if (set_dev(dev))
return 1;
- if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
+ if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
addr = simple_strtoul(argv[1], NULL, 16);
else
addr = CONFIG_SYS_LOAD_ADDR;
- return nand_load_image(cmdtp, &nand_info[dev->id->num],
+ return nand_load_image(cmdtp, nand_info[dev->id->num],
part->offset, addr, argv[0]);
}
}
idx = simple_strtoul(boot_device, NULL, 16);
- if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
+ if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) {
printf("\n** Device %d not available\n", idx);
bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
return 1;
}
bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
- return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
+ return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
}
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
size_t blocksize, len;
u_char *char_ptr;
- blocksize = nand_info[0].erasesize;
+ blocksize = nand_info[0]->erasesize;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(&nand_info[0], offset)) {
+ if (nand_block_isbad(nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_saved];
- if (nand_write(&nand_info[0], offset, &len, char_ptr))
+ if (nand_write(nand_info[0], offset, &len, char_ptr))
return 1;
offset += blocksize;
int ret = 0;
printf("Erasing %s...\n", location->name);
- if (nand_erase_opts(&nand_info[0], &location->erase_opts))
+ if (nand_erase_opts(nand_info[0], &location->erase_opts))
return 1;
printf("Writing to %s... ", location->name);
size_t blocksize, len;
u_char *char_ptr;
- blocksize = nand_info[0].erasesize;
+ blocksize = nand_info[0]->erasesize;
if (!blocksize)
return 1;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(&nand_info[0], offset)) {
+ if (nand_block_isbad(nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
- if (nand_read_skip_bad(&nand_info[0], offset,
+ if (nand_read_skip_bad(nand_info[0], offset,
&len, NULL,
- nand_info[0].size, char_ptr))
+ nand_info[0]->size, char_ptr))
return 1;
offset += blocksize;
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
- ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+ ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset);
/*
* If unable to read environment offset from NAND OOB then fall through
* to the normal environment reading code below
return -EINVAL;
}
- *mtd = &nand_info[dev->id->num];
+ *mtd = nand_info[dev->id->num];
return 0;
}
#ifdef CONFIG_CMD_NAND
static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
{
- return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
+ return nand_read_skip_bad(nand_info[nand_curr_device], offset,
&read_size, NULL,
- nand_info[nand_curr_device].size,
+ nand_info[nand_curr_device]->size,
(u_char *)bmp_load_addr);
}
#else
Example of new init to be added to the end of an existing driver
init:
- /*
- * devnum is the device number to be used in nand commands
- * and in mtd->name. Must be less than
- * CONFIG_SYS_NAND_MAX_DEVICE.
- */
- mtd = &nand_info[devnum];
-
/* chip is struct nand_chip, and is now provided by the driver. */
- mtd->priv = &chip;
+ mtd = &chip.mtd;
/*
* Fill in appropriate values if this driver uses these fields,
if (nand_scan_tail(mtd))
error out
- if (nand_register(devnum))
+ /*
+ * devnum is the device number to be used in nand commands
+ * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
+ */
+ if (nand_register(devnum, mtd))
error out
In addition to providing more flexibility to the driver, it reduces
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- mtd = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
if (op == DFU_OP_READ) {
ret = nand_read_skip_bad(mtd, start, &count, &actual,
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- mtd = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
memset(&opts, 0, sizeof(opts));
opts.offset = dfu->data.nand.start + dfu->offset +
#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-struct mtd_info nand_info[1];
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
/* Emulate NAND_CMD_READOOB */
}
/* Begin command latch cycle */
- hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_RESET) {
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&nand_info[0]))
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(mtd))
;
return 0;
}
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&nand_info[0], offs & 0xff,
+ hwctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
if (cmd != NAND_CMD_RNDOUT) {
- hwctrl(&nand_info[0], (page_addr & 0xff),
+ hwctrl(mtd, (page_addr & 0xff),
NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
}
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
/* Latch in address */
- hwctrl(&nand_info[0], NAND_CMD_READSTART,
+ hwctrl(mtd, NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
} else if (cmd == NAND_CMD_RNDOUT) {
- hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
}
return 0;
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
NAND_CMD_READOOB);
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
nand_command(block, page, 0, NAND_CMD_READ0);
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], p, eccsize);
+ this->read_buf(mtd, p, eccsize);
nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], oob, eccbytes);
- this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
+ this->read_buf(mtd, oob, eccbytes);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
data_pos += eccsize;
oob_pos += eccbytes;
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
/*
* Init board specific nand support
*/
- nand_info[0].priv = &nand_chip;
+ mtd = &nand_chip.mtd;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], 0);
+ nand_chip.select_chip(mtd, 0);
/* NAND chip may require reset after power-on */
nand_command(0, 0, 0, NAND_CMD_RESET);
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], -1);
+ nand_chip.select_chip(mtd, -1);
}
}
nand->nand_base = arasan_nand_base;
- mtd = &nand_info[0];
+ mtd = &nand_chip->mtd;
nand_chip->priv = nand;
mtd->priv = nand_chip;
goto fail;
}
- if (nand_register(devnum)) {
+ if (nand_register(devnum, mtd)) {
printf("Nand Register Fail\n");
goto fail;
}
#ifdef CONFIG_SPL_BUILD
/* The following code is for SPL */
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
static int nand_command(int block, int page, uint32_t offs, u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
if (cmd == NAND_CMD_READOOB) {
cmd = NAND_CMD_READ0;
}
- hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
- hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
- hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+ hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+ hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+ hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
#endif
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
if (this->ecc.mode != NAND_ECC_SOFT)
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
}
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
for (i = 0; i < ECCTOTAL; i++)
ecc_code[i] = oob_data[nand_ecc_pos[i]];
p = dst;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
return 0;
}
int spl_nand_erase_one(int block, int page)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
int page_addr;
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Row address */
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE | NAND_CTRL_CHANGE);
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE | NAND_CTRL_CHANGE);
#endif
- hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
nand_deselect();
#else
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
nand_command(block, page, 0, NAND_CMD_READ0);
- atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+ atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
return 0;
}
#ifdef CONFIG_ATMEL_NAND_HWECC
#ifdef CONFIG_ATMEL_NAND_HW_PMECC
- ret = atmel_pmecc_nand_init_params(nand, &mtd);
+ ret = atmel_pmecc_nand_init_params(nand, mtd);
#endif
#endif
void nand_init(void)
{
- mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
- mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
+ mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+ mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
+ mtd->priv = &nand_chip;
nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#endif
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
}
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, -1);
+ nand_chip.select_chip(mtd, -1);
}
#else
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
int ret;
- struct mtd_info *mtd = &nand_info[devnum];
struct nand_chip *nand = &nand_chip[devnum];
+ struct mtd_info *mtd = &nand->mtd;
mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
ret = nand_scan_tail(mtd);
if (!ret)
- nand_register(devnum);
+ nand_register(devnum, mtd);
return ret;
}
goto fail;
}
- ret = nand_register(0);
+ ret = nand_register(0, denali->mtd);
fail:
return ret;
* for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
* still provides a "struct mtd_info nand_info" instance.
*/
- denali->mtd = &nand_info[0];
+ denali->mtd = &denali->nand.mtd;
/*
* In the future, these base addresses should be taken from
static int fsl_elbc_chip_init(int devnum, u8 *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *nand;
struct fsl_elbc_mtd *priv;
uint32_t br = 0, or = 0;
}
nand = &priv->chip;
+ mtd = &nand->mtd;
mtd->priv = nand;
elbc_ctrl->chips[priv->bank] = priv;
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, mtd);
if (ret)
return ret;
static int fsl_ifc_chip_init(int devnum, u8 *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *nand;
struct fsl_ifc_mtd *priv;
struct nand_ecclayout *layout;
}
nand = &priv->chip;
+ mtd = &nand->mtd;
mtd->priv = nand;
ifc_ctrl->chips[priv->bank] = priv;
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, mtd);
if (ret)
return ret;
return 0;
* Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
* function, as it doesn't need to switch to a different ECC layout.
*/
- mtd = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
nand = mtd->priv;
/* Setup the ecc configurations again */
{
static int chip_nr;
struct mtd_info *mtd;
- int i;
u32 peripid2 = readl(&fsmc_regs_p->peripid2);
fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
(void __iomem *)CONFIG_SYS_NAND_BASE;
nand->badblockbits = 7;
- mtd = &nand_info[chip_nr++];
+ mtd = &nand->mtd;
mtd->priv = nand;
switch (fsmc_version) {
if (nand_scan_tail(mtd))
return -ENXIO;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- if (nand_register(i))
- return -ENXIO;
+ if (nand_register(chip_nr++, mtd))
+ return -ENXIO;
return 0;
}
void board_nand_init(void)
{
- /* we have only one device anyway */
- struct mtd_info *mtd = &nand_info[0];
- /* chip is struct nand_chip, and is now provided by the driver. */
- mtd->priv = &lpc32xx_chip;
- /* to store return status in case we need to print it */
+ struct mtd_info *mtd = &lpc32xx_chip.mtd;
int ret;
+ mtd->priv = &lpc32xx_chip;
+
/* Set all BOARDSPECIFIC (actually core-specific) fields */
lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
}
/* chip is good, register it */
- ret = nand_register(0);
+ ret = nand_register(0, mtd);
if (ret)
error("nand_register returned %i", ret);
}
int resettime = 0;
int retval = 0;
int rev;
- static int chip_nr = 0;
/*
* Check SoC revision. This driver supports only NFC
return -ENOMEM;
}
- mtd = &nand_info[chip_nr++];
+ mtd = &chip->mtd;
mtd->priv = chip;
chip->priv = prv;
#endif
/* structures must be linked */
- mtd = &host->mtd;
+ mtd = &this->mtd;
mtd->priv = this;
host->nand = this;
#include <nand.h>
#include <malloc.h>
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
/* init mxs nand driver */
board_nand_init(&nand_chip);
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
+ mtd->priv = &nand_chip;
/* set mtd functions */
nand_chip.cmdfunc = mxs_nand_command;
nand_chip.numchips = 1;
/* identify flash device */
puts("NAND : ");
- if (mxs_flash_ident(&mtd)) {
+ if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
}
/* allocate and initialize buffers */
nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
sizeof(*nand_chip.buffers));
- nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+ nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
/* setup flash layout (does not scan as we override that) */
- mtd.size = nand_chip.chipsize;
- nand_chip.scan_bbt(&mtd);
+ mtd->size = nand_chip.chipsize;
+ nand_chip.scan_bbt(mtd);
- printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+ printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
return 0;
}
if (mxs_nand_init())
return -ENODEV;
- chip = mtd.priv;
+ chip = mtd->priv;
page = offs >> chip->page_shift;
- nand_page_per_block = mtd.erasesize / mtd.writesize;
+ nand_page_per_block = mtd->erasesize / mtd->writesize;
debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
- size = roundup(size, mtd.writesize);
+ size = roundup(size, mtd->writesize);
while (sz < size) {
- if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+ if (mxs_read_page_ecc(mtd, buf, page) < 0)
return -1;
- sz += mtd.writesize;
- offs += mtd.writesize;
+ sz += mtd->writesize;
+ offs += mtd->writesize;
page++;
- buf += mtd.writesize;
+ buf += mtd->writesize;
/*
* Check if we have crossed a block boundary, and if so
* Yes, new block. See if this block is good. If not,
* loop until we find a good block.
*/
- while (is_badblock(&mtd, offs, 1)) {
+ while (is_badblock(mtd, offs, 1)) {
page = page + nand_page_per_block;
/* Check i we've reached the end of flash. */
- if (page >= mtd.size >> chip->page_shift)
+ if (page >= mtd->size >> chip->page_shift)
return -ENOMEM;
}
}
int nand_curr_device = -1;
-struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#ifndef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static unsigned long total_nand_size; /* in kiB */
-/* Register an initialized NAND mtd device with the U-Boot NAND command. */
-int nand_register(int devnum)
+int nand_mtd_to_devnum(struct mtd_info *mtd)
{
- struct mtd_info *mtd;
+ int i;
+ for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
+ if (mtd && nand_info[i] == mtd)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+/* Register an initialized NAND mtd device with the U-Boot NAND command. */
+int nand_register(int devnum, struct mtd_info *mtd)
+{
if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
return -EINVAL;
- mtd = &nand_info[devnum];
+ nand_info[devnum] = mtd;
sprintf(dev_name[devnum], "nand%d", devnum);
mtd->name = dev_name[devnum];
#ifndef CONFIG_SYS_NAND_SELF_INIT
static void nand_init_chip(int i)
{
- struct mtd_info *mtd = &nand_info[i];
struct nand_chip *nand = &nand_chip[i];
+ struct mtd_info *mtd = &nand->mtd;
ulong base_addr = base_address[i];
int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
if (nand_scan(mtd, maxchips))
return;
- nand_register(i);
+ nand_register(i, mtd);
}
#endif
/*
* Select the chip in the board/cpu specific driver
*/
- board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+ board_nand_select_device(nand_info[nand_curr_device]->priv,
+ nand_curr_device);
#endif
}
#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv();
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
/* Begin command latch cycle */
- this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
- this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
+ this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+ this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
/* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[28:25] */
#endif
/* Latch in address */
- this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
/* Emulate NAND_CMD_READOOB */
offs >>= 1;
/* Begin command latch cycle */
- hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&mtd, offs & 0xff,
- NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, offs & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
+ NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
/* Latch in address */
- hwctrl(&mtd, NAND_CMD_READSTART,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_READSTART,
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
u_char bb_data[2];
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
* Read one byte (or two if it's a 16 bit chip).
*/
if (this->options & NAND_BUSWIDTH_16) {
- this->read_buf(&mtd, bb_data, 2);
+ this->read_buf(mtd, bb_data, 2);
if (bb_data[0] != 0xff || bb_data[1] != 0xff)
return 1;
} else {
- this->read_buf(&mtd, bb_data, 1);
+ this->read_buf(mtd, bb_data, 1);
if (bb_data[0] != 0xff)
return 1;
}
#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
static int nand_read_page(int block, int page, uchar *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
uint8_t *p = dst;
nand_command(block, page, 0, NAND_CMD_READOOB);
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
nand_command(block, page, 0, NAND_CMD_READ0);
/* Pick the ECC bytes out of the oob data */
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
#else
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd->priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
if (this->ecc.mode != NAND_ECC_SOFT)
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
}
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
/* Pick the ECC bytes out of the oob data */
for (i = 0; i < ECCTOTAL; i++)
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
/*
* Init board specific nand support
*/
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
+ mtd->priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#endif
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
}
/* Unselect after operation */
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, -1);
+ nand_chip.select_chip(mtd, -1);
}
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("nand: error: no NAND devices found\n");
return -ENODEV;
}
- mtd = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
nand = mtd->priv;
nand->options |= NAND_OWN_BUFFERS;
nand->options &= ~NAND_SUBPAGE_READ;
info->variant = pxa3xx_nand_get_variant();
for (cs = 0; cs < pdata->num_cs; cs++) {
- mtd = &nand_info[cs];
chip = (struct nand_chip *)
((u8 *)&info[1] + sizeof(*host) * cs);
+ mtd = &chip->mtd;
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
host->mtd = mtd;
continue;
}
- if (!ret)
- probe_success = 1;
+ if (nand_register(cs, mtd))
+ continue;
+
+ probe_success = 1;
}
if (!probe_success)
ret = pxa3xx_nand_probe(info);
if (ret)
return;
-
- nand_register(0);
}
dm_gpio_set_value(&config->wp_gpio, 1);
- our_mtd = &nand_info[devnum];
+ our_mtd = &nand->mtd;
our_mtd->priv = nand;
ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
if (ret)
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, our_mtd);
if (ret)
return ret;
static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *chip;
struct vf610_nfc *nfc;
int err = 0;
chip = &nfc->chip;
nfc->regs = addr;
+ mtd = &chip->mtd;
mtd->priv = chip;
chip->priv = nfc;
if (err)
return err;
- err = nand_register(devnum);
+ err = nand_register(devnum, mtd);
if (err)
return err;
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+ rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
- ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
- &fw_length, (u_char *)addr);
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+ &fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
CONFIG_CORTINA_FW_ADDR, ret);
}
retlen = NAND_CACHE_SIZE;
- if (nand_read(&nand_info[id->num], nand_cache_off,
+ if (nand_read(nand_info[id->num], nand_cache_off,
&retlen, nand_cache) != 0 ||
retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
u32 counterN = 0;
struct mtdids *id = part->dev->id;
- mtd = nand_info + id->num;
+ mtd = nand_info[id->num];
/* if we are building a list we need to refresh the cache. */
jffs_init_1pass_list(part);
}
}
-extern struct mtd_info nand_info[];
-
void cmd_yaffs_tracemask(unsigned set, unsigned mask)
{
if (set)
dev = calloc(1, sizeof(*dev));
mp = strdup(_mp);
- mtd = &nand_info[flash_dev];
+ mtd = nand_info[flash_dev];
if (!dev || !mp) {
/* Alloc error */
dev = yaffs_next_dev();
if (!dev)
return;
- flash_dev =
- ((unsigned) dev->driver_context - (unsigned) nand_info)/
- sizeof(nand_info[0]);
+ flash_dev = nand_mtd_to_devnum(dev->driver_context);
printf("%-10s %5d 0x%05x 0x%05x %s",
dev->param.name, flash_dev,
dev->param.start_block, dev->param.end_block,
*/
struct nand_chip {
+ struct mtd_info mtd;
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
+int nand_mtd_to_devnum(struct mtd_info *mtd);
+
#ifdef CONFIG_SYS_NAND_SELF_INIT
void board_nand_init(void);
-int nand_register(int devnum);
+int nand_register(int devnum, struct mtd_info *mtd);
#else
extern int board_nand_init(struct nand_chip *nand);
#endif
extern int nand_curr_device;
-extern struct mtd_info nand_info[];
+extern struct mtd_info *nand_info[];
static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
u_char *buf)
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