keystone2: enable OSR clock domain for K2L SoC

This patches enables the On-chip Shared Ram clock domain for K2L SoC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 62081b7efa20a52744ba74a7a4d65f57951b48ee..c2b947839d292a14090e15d951703eb99e517f6e 100644 (file)
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
 #include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
 
 void chip_configuration_unlock(void)
 {
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
        __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+       u32 i;
+       u32 j;
+       u32 val;
+       u32 base = KS2_OSR_CFG_BASE;
+       u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+       /* Enable the OSR clock domain */
+       psc_enable_module(KS2_LPSC_OSR);
+
+       /* Disable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+               val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+                       (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+               writel(val , base + KS2_OSR_ECC_VEC);
+
+               /**
+                * wait till read is done.
+                * Print should be added after earlyprintk support is added.
+                */
+               for (j = 0; j < 10000; j++) {
+                       val = readl(base + KS2_OSR_ECC_VEC);
+                       if (val & KS2_OSR_ECC_VEC_RD_DONE)
+                               break;
+               }
+
+               ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+                                               KS2_OSR_ECC_CTRL_CHK;
+
+               writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+               writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+       }
+
+       /* Reset OSR memory to all zeros */
+       for (i = 0; i < KS2_OSR_SIZE; i += 4)
+               writel(0, KS2_OSR_DATA_BASE + i);
+
+       /* Enable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+               writel(ecc_ctrl[i] |
+                      KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
 int arch_cpu_init(void)
 {
        chip_configuration_unlock();
@@ -32,6 +80,9 @@ int arch_cpu_init(void)
 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
        msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
 #endif
+#ifdef CONFIG_SOC_K2L
+       osr_init();
+#endif
 
        /*
         * just initialise the COM2 port so that TI specific

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index c1fa3afa9d1cedb2d79c31c0ac2ca9338ef70a66..05532ada70d0d21d6beaa5c5ca6209b111a00f83 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -60,6 +60,30 @@
 #define KS2_CIC2_DDR3_ECC_IRQ_NUM      0x0D3
 #define KS2_CIC2_DDR3_ECC_CHAN_NUM     0x01D
 
+/* OSR */
+#define KS2_OSR_DATA_BASE              0x70000000      /* OSR data base */
+#define KS2_OSR_CFG_BASE               0x02348c00      /* OSR config base */
+#define KS2_OSR_ECC_VEC                        0x08            /* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL               0x14            /* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD                BIT(15)         /* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE                BIT(24)         /* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH      0               /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH     16              /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN            BIT(0)          /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK           BIT(1)          /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW           BIT(2)          /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS          4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE                   0x100000
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS                   4
 

diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 295c6b0ea9bd5dc1de52c70531f4d5bc8801d0dd..08a7c7003838dc7cce7042f82f7b61a0e2eaed2a 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -142,6 +142,7 @@ typedef volatile unsigned int   *dv_reg_p;
 
 /* MSMC control */
 #define KS2_MSMC_CTRL_BASE             0x0bc00000
+#define KS2_MSMC_DATA_BASE             0x0c000000
 #define KS2_MSMC_SEGMENT_TETRIS                8
 #define KS2_MSMC_SEGMENT_NETCP         9
 #define KS2_MSMC_SEGMENT_QM_PDSP       10