arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH

The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/README b/README
index 43430576b2eface9929e3a08b5c0c8697ce6a8a1..b6c9d0b0e957da172f365e82c38b9fecc39058eb 100644 (file)
--- a/README
+++ b/README
@@ -420,6 +420,12 @@ The following options need to be configured:
                XWAY SoCs for booting from NOR flash. The U-Boot image needs to
                be swapped if a flash programmer is used.
 
+- ARM options:
+               CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+               Select high exception vectors of the ARM core, e.g., do not
+               clear the V bit of the c1 register of CP15.
+
 - Linux Kernel Interface:
                CONFIG_CLOCKS_IN_MHZ
 

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index b39ed8a123779f2b6de7b61605bc1f7a24d81299..525c1122c96b5a005f5ca47d3901be20bb46a627 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -372,8 +372,13 @@ flush_dcache:
         * disable MMU and D cache, and enable I cache
         */
        mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
+       bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
        bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+       orr     r0, r0, #0x00002000     /* set bit 13 (--V- ----) */
+#else
+       bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
+#endif
        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
        mcr     p15, 0, r0, c1, c0, 0

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 51a5a09a7272ffc67da7a4151e08dccc4d80d27b..8e0293dedfca920f51e5873ab0b4c307267bf64a 100644 (file)
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -37,6 +37,7 @@
 #define CONFIG_ARM926EJS               /* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
 #define CONFIG_SOC_DA850               /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE

diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 98421795b4e31b6175ab1b5140d937034fb43dec..053cfa472bd379f25cb8b1fa6f4251a596242aee 100644 (file)
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -40,6 +40,7 @@
 #define CONFIG_ARM926EJS               /* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
 #define CONFIG_SOC_DA850               /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE

diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 21f7b9b7e318425ab987d4a2abe4a7c58febf2e9..c310c733824419c0af009abb00b9956453df1437 100644 (file)
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -35,6 +35,7 @@
 #define CONFIG_ARM926EJS               /* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
 #define CONFIG_SOC_DA850               /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE