LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
-int testdram (void)
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
+#ifdef CONFIG_LXT971_NO_SLEEP
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
#endif
+}
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ $(CPLD) \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
/*
* Setup and enable EEPROM write protection
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
return (0);
}
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
break;
}
}
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
+#if defined(CFG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
+#endif
#include <fat.h>
#include <part.h>
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#else
+ rc = -1;
#endif
}
if (rc != 0) {
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+ break;
+ case NAND_CTL_CLRCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+ break;
+ case NAND_CTL_SETALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+ break;
+ case NAND_CTL_CLRALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+ break;
+ case NAND_CTL_SETNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+ break;
+ case NAND_CTL_CLRNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+ break;
+ }
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+ return 1;
+ return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /*
+ * Set NAND-FLASH GPIO signals to defaults
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Initialize nand_chip structure
+ */
+ nand->hwcontrol = esd405ep_nand_hwcontrol;
+ nand->dev_ready = esd405ep_nand_device_ready;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ return 0;
+}
+#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Reset touch-screen controller
*/
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, val);
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* check board type and setup AP power
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#define FPGA_DEBUG
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
int index;
int i;
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active)
-{
- if (au_active) {
- printf("\n Dies ist die board-funktion: Updating!!!\n");
- } else {
- printf("\n Dies ist die board-funktion: Updating done!!!\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
}
}
#endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+ /*cmd_boot.c*/
+ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
+#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP)
#include <rtc.h>
#endif
#include <hush.h>
#endif
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
#ifdef CFG_INIT_RAM_LOCK
#include <asm/cache.h>
#endif
static void *zalloc(void *, unsigned, unsigned);
static void zfree(void *, void *, unsigned);
-#if defined(CONFIG_CMD_IMI)
+#if (CONFIG_COMMANDS & CFG_CMD_IMI)
static int image_info (unsigned long addr);
#endif
-#if defined(CONFIG_CMD_IMLS)
+#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
#include <flash.h>
extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
static boot_os_Fcn do_bootm_netbsd;
static boot_os_Fcn do_bootm_rtems;
-#if defined(CONFIG_CMD_ELF)
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
static boot_os_Fcn do_bootm_vxworks;
static boot_os_Fcn do_bootm_qnxelf;
int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
-#endif
+#endif /* CFG_CMD_ELF */
#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
static boot_os_Fcn do_bootm_artos;
#endif
addr = simple_strtoul(argv[1], NULL, 16);
}
- show_boot_progress (1);
+ SHOW_BOOT_PROGRESS (1);
printf ("## Booting image at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
#endif /* __I386__ */
{
puts ("Bad Magic Number\n");
- show_boot_progress (-1);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
}
- show_boot_progress (2);
+ SHOW_BOOT_PROGRESS (2);
data = (ulong)&header;
len = sizeof(image_header_t);
if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
- show_boot_progress (-2);
+ SHOW_BOOT_PROGRESS (-2);
return 1;
}
- show_boot_progress (3);
+ SHOW_BOOT_PROGRESS (3);
#ifdef CONFIG_HAS_DATAFLASH
if (addr_dataflash(addr)){
puts (" Verifying Checksum ... ");
if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
- show_boot_progress (-3);
+ SHOW_BOOT_PROGRESS (-3);
return 1;
}
puts ("OK\n");
}
- show_boot_progress (4);
+ SHOW_BOOT_PROGRESS (4);
len_ptr = (ulong *)data;
#endif
{
printf ("Unsupported Architecture 0x%x\n", hdr->ih_arch);
- show_boot_progress (-4);
+ SHOW_BOOT_PROGRESS (-4);
return 1;
}
- show_boot_progress (5);
+ SHOW_BOOT_PROGRESS (5);
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE:
data += 4;
break;
default: printf ("Wrong Image Type for %s command\n", cmdtp->name);
- show_boot_progress (-5);
+ SHOW_BOOT_PROGRESS (-5);
return 1;
}
- show_boot_progress (6);
+ SHOW_BOOT_PROGRESS (6);
/*
* We have reached the point of no return: we are going to
if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
(uchar *)data, &len) != 0) {
puts ("GUNZIP ERROR - must RESET board to recover\n");
- show_boot_progress (-6);
+ SHOW_BOOT_PROGRESS (-6);
do_reset (cmdtp, flag, argc, argv);
}
break;
CFG_MALLOC_LEN < (4096 * 1024), 0);
if (i != BZ_OK) {
printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
- show_boot_progress (-6);
+ SHOW_BOOT_PROGRESS (-6);
+ udelay(100000);
do_reset (cmdtp, flag, argc, argv);
}
break;
if (iflag)
enable_interrupts();
printf ("Unimplemented compression type %d\n", hdr->ih_comp);
- show_boot_progress (-7);
+ SHOW_BOOT_PROGRESS (-7);
return 1;
}
puts ("OK\n");
- show_boot_progress (7);
+ SHOW_BOOT_PROGRESS (7);
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE:
if (iflag)
enable_interrupts();
printf ("Can't boot image type %d\n", hdr->ih_type);
- show_boot_progress (-8);
+ SHOW_BOOT_PROGRESS (-8);
return 1;
}
- show_boot_progress (8);
+ SHOW_BOOT_PROGRESS (8);
switch (hdr->ih_os) {
default: /* handled by (original) Linux case */
addr, len_ptr, verify);
break;
-#if defined(CONFIG_CMD_ELF)
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
case IH_OS_VXWORKS:
do_bootm_vxworks (cmdtp, flag, argc, argv,
addr, len_ptr, verify);
do_bootm_qnxelf (cmdtp, flag, argc, argv,
addr, len_ptr, verify);
break;
-#endif
+#endif /* CFG_CMD_ELF */
#ifdef CONFIG_ARTOS
case IH_OS_ARTOS:
do_bootm_artos (cmdtp, flag, argc, argv,
#endif
}
- show_boot_progress (-9);
+ SHOW_BOOT_PROGRESS (-9);
#ifdef DEBUG
puts ("\n## Control returned to monitor - resetting...\n");
do_reset (cmdtp, flag, argc, argv);
#endif
if (argc >= 3) {
debug ("Not skipping initrd\n");
- show_boot_progress (9);
+ SHOW_BOOT_PROGRESS (9);
addr = simple_strtoul(argv[2], NULL, 16);
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
puts ("Bad Magic Number\n");
- show_boot_progress (-10);
+ SHOW_BOOT_PROGRESS (-10);
do_reset (cmdtp, flag, argc, argv);
}
if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
- show_boot_progress (-11);
+ SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
}
- show_boot_progress (10);
+ SHOW_BOOT_PROGRESS (10);
print_image_hdr (hdr);
if (csum != ntohl(hdr->ih_dcrc)) {
puts ("Bad Data CRC\n");
- show_boot_progress (-12);
+ SHOW_BOOT_PROGRESS (-12);
do_reset (cmdtp, flag, argc, argv);
}
puts ("OK\n");
}
- show_boot_progress (11);
+ SHOW_BOOT_PROGRESS (11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_PPC) ||
(hdr->ih_type != IH_TYPE_RAMDISK) ) {
puts ("No Linux PPC Ramdisk Image\n");
- show_boot_progress (-13);
+ SHOW_BOOT_PROGRESS (-13);
do_reset (cmdtp, flag, argc, argv);
}
u_long tail = ntohl(len_ptr[0]) % 4;
int i;
- show_boot_progress (13);
+ SHOW_BOOT_PROGRESS (13);
/* skip kernel length and terminator */
data = (ulong)(&len_ptr[2]);
/*
* no initrd image
*/
- show_boot_progress (14);
+ SHOW_BOOT_PROGRESS (14);
len = data = 0;
}
if(argc > 3) {
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
hdr = (image_header_t *)of_flat_tree;
-#if defined(CONFIG_OF_FLAT_TREE)
- if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+#if defined(CONFIG_OF_LIBFDT)
+ if (fdt_check_header(of_flat_tree) == 0) {
#else
- if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+ if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
#endif
#ifndef CFG_NO_FLASH
if (addr2info((ulong)of_flat_tree) != NULL)
of_data = (ulong)of_flat_tree;
#endif
} else if (ntohl(hdr->ih_magic) == IH_MAGIC) {
- printf("## Flat Device Tree at %08lX\n", hdr);
+ printf("## Flat Device Tree Image at %08lX\n", hdr);
print_image_hdr(hdr);
if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) &&
((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) {
- puts ("ERROR: fdt overwritten - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("ERROR: Load address overwrites Flat Device Tree uImage\n");
+ return;
}
- puts (" Verifying Checksum ... ");
+ printf(" Verifying Checksum ... ");
memmove (&header, (char *)hdr, sizeof(image_header_t));
checksum = ntohl(header.ih_hcrc);
header.ih_hcrc = 0;
if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) {
- puts ("ERROR: fdt header checksum invalid - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf("ERROR: Flat Device Tree header checksum is invalid\n");
+ return;
}
checksum = ntohl(hdr->ih_dcrc);
addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t));
if(checksum != crc32(0, (uchar *)addr, ntohl(hdr->ih_size))) {
- puts ("ERROR: fdt checksum invalid - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf("ERROR: Flat Device Tree checksum is invalid\n");
+ return;
}
- puts ("OK\n");
+ printf("OK\n");
if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) {
- puts ("ERROR: uImage is not a fdt - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("ERROR: uImage not Flat Device Tree type\n");
+ return;
}
if (ntohl(hdr->ih_comp) != IH_COMP_NONE) {
- puts ("ERROR: uImage is compressed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf("ERROR: uImage is not uncompressed\n");
+ return;
}
-#if defined(CONFIG_OF_FLAT_TREE)
- if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+#if defined(CONFIG_OF_LIBFDT)
+ if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) {
#else
- if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+ if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
#endif
- puts ("ERROR: uImage data is not a fdt - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("ERROR: uImage data is not a flat device tree\n");
+ return;
}
memmove((void *)ntohl(hdr->ih_load),
ntohl(hdr->ih_size));
of_flat_tree = (char *)ntohl(hdr->ih_load);
} else {
- puts ("Did not find a flat Flat Device Tree.\n"
- "Must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree);
+ return;
}
- printf (" Booting using the fdt at 0x%x\n",
+ printf (" Booting using flat device tree at 0x%x\n",
of_flat_tree);
} else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1]) && (len_ptr[2])) {
u_long tail = ntohl(len_ptr[0]) % 4;
of_data += 4 - tail;
}
-#if defined(CONFIG_OF_FLAT_TREE)
- if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+#if defined(CONFIG_OF_LIBFDT)
+ if (fdt_check_header((void *)of_data) != 0) {
#else
- if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+ if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
#endif
- puts ("ERROR: image is not a fdt - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("ERROR: image is not a flat device tree\n");
+ return;
}
-#if defined(CONFIG_OF_FLAT_TREE)
- if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
-#else
+#if defined(CONFIG_OF_LIBFDT)
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
+#else
+ if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
#endif
- puts ("ERROR: fdt size != image size - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("ERROR: flat device tree size does not agree with image\n");
+ return;
}
}
#endif
initrd_start = nsp;
}
- show_boot_progress (12);
+ SHOW_BOOT_PROGRESS (12);
debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
data, data + len - 1, len, len);
initrd_end = 0;
}
-#ifdef CFG_BOOTMAPSZ
- /*
- * The blob must be within CFG_BOOTMAPSZ,
- * so we flag it to be copied if it is
- */
- if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
- of_data = of_flat_tree;
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong)kernel);
+
+ SHOW_BOOT_PROGRESS (15);
+
+#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
+ unlock_ram_in_cache();
#endif
#if defined(CONFIG_OF_LIBFDT)
ulong of_start, of_len;
of_len = be32_to_cpu(fdt_totalsize(of_data));
-
- /* position on a 4K boundary before the kbd */
- of_start = (ulong)kbd - of_len;
+ /* position on a 4K boundary before the initrd/kbd */
+ if (initrd_start)
+ of_start = initrd_start - of_len;
+ else
+ of_start = (ulong)kbd - of_len;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
of_flat_tree = (char *)of_start;
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
- err = fdt_open_into((void *)of_data, (void *)of_start, of_len);
+ err = fdt_open_into((void *)of_start, (void *)of_data, of_len);
if (err != 0) {
- puts ("ERROR: fdt move failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
+ printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__);
+ }
+ /*
+ * Add the chosen node if it doesn't exist, add the env and bd_t
+ * if the user wants it (the logic is in the subroutines).
+ */
+ if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
+ printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
+ return;
}
- }
- /*
- * Add the chosen node if it doesn't exist, add the env and bd_t
- * if the user wants it (the logic is in the subroutines).
- */
- if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
- puts ("ERROR: /chosen node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
#ifdef CONFIG_OF_HAS_UBOOT_ENV
- if (fdt_env(of_flat_tree) < 0) {
- puts ("ERROR: /u-boot-env node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_env(of_flat_tree) < 0) {
+ printf("Failed creating the /u-boot-env node, aborting.\n");
+ return;
+ }
#endif
#ifdef CONFIG_OF_HAS_BD_T
- if (fdt_bd_t(of_flat_tree) < 0) {
- puts ("ERROR: /bd_t node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_bd_t(of_flat_tree) < 0) {
+ printf("Failed creating the /bd_t node, aborting.\n");
+ return;
+ }
#endif
-#ifdef CONFIG_OF_BOARD_SETUP
- /* Call the board-specific fixup routine */
- ft_board_setup(of_flat_tree, gd->bd);
+ }
#endif
-#endif /* CONFIG_OF_LIBFDT */
#if defined(CONFIG_OF_FLAT_TREE)
/* move of_flat_tree if needed */
if (of_data) {
ulong of_start, of_len;
of_len = ((struct boot_param_header *)of_data)->totalsize;
-
/* provide extra 8k pad */
- of_start = (ulong)kbd - of_len - 8192;
+ if (initrd_start)
+ of_start = initrd_start - of_len - 8192;
+ else
+ of_start = (ulong)kbd - of_len - 8192;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
of_start, of_start + of_len - 1);
memmove ((void *)of_start, (void *)of_data, of_len);
}
- /*
- * Create the /chosen node and modify the blob with board specific
- * values as needed.
- */
- ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
- /* ft_dump_blob(of_flat_tree); */
-#endif
- debug ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong)kernel);
-
- show_boot_progress (15);
-
-#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
- unlock_ram_in_cache();
#endif
-#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
- if (of_flat_tree) { /* device tree; boot new style */
- /*
- * Linux Kernel Parameters (passing device tree):
- * r3: pointer to the fdt, followed by the board info data
- * r4: physical pointer to the kernel itself
- * r5: NULL
- * r6: NULL
- * r7: NULL
- */
- (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
- /* does not return */
- }
-#endif
/*
* Linux Kernel Parameters (passing board info data):
* r3: ptr to board info data
* r6: Start of command line string
* r7: End of command line string
*/
- (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
- /* does not return */
+#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
+ if (!of_flat_tree) /* no device tree; boot old style */
+#endif
+ (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+ /* does not return */
+
+#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
+ /*
+ * Linux Kernel Parameters (passing device tree):
+ * r3: ptr to OF flat tree, followed by the board info data
+ * r4: physical pointer to the kernel itself
+ * r5: NULL
+ * r6: NULL
+ * r7: NULL
+ */
+#if defined(CONFIG_OF_FLAT_TREE)
+ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
+ /* ft_dump_blob(of_flat_tree); */
+#endif
+#if defined(CONFIG_OF_LIBFDT)
+ if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
+ printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
+ return;
+ }
+#ifdef CONFIG_OF_HAS_UBOOT_ENV
+ if (fdt_env(of_flat_tree) < 0) {
+ printf("Failed creating the /u-boot-env node, aborting.\n");
+ return;
+ }
+#endif
+#ifdef CONFIG_OF_HAS_BD_T
+ if (fdt_bd_t(of_flat_tree) < 0) {
+ printf("Failed creating the /bd_t node, aborting.\n");
+ return;
+ }
+#endif
+#endif /* if defined(CONFIG_OF_LIBFDT) */
+
+ (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
+#endif
}
#endif /* CONFIG_PPC */
printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
(ulong)loader);
- show_boot_progress (15);
+ SHOW_BOOT_PROGRESS (15);
/*
* NetBSD Stage-2 Loader Parameters:
#endif
-#if defined(CONFIG_CMD_BOOTD)
+#if (CONFIG_COMMANDS & CFG_CMD_BOOTD)
int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
#endif
-#if defined(CONFIG_CMD_IMI)
+#if (CONFIG_COMMANDS & CFG_CMD_IMI)
int do_iminfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int arg;
" image contents (magic number, header and payload checksums)\n"
);
-#endif
+#endif /* CFG_CMD_IMI */
-#if defined(CONFIG_CMD_IMLS)
+#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
/*-----------------------------------------------------------------------
* List all images found in flash.
*/
" - Prints information about all images found at sector\n"
" boundaries in flash.\n"
);
-#endif
+#endif /* CFG_CMD_IMLS */
void
print_image_hdr (image_header_t *hdr)
{
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
+#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP)
time_t timestamp = (time_t)ntohl(hdr->ih_time);
struct rtc_time tm;
#endif
printf (" Image Name: %.*s\n", IH_NMLEN, hdr->ih_name);
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
+#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP)
to_tm (timestamp, &tm);
printf (" Created: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec);
-#endif
+#endif /* CFG_CMD_DATE, CONFIG_TIMESTAMP */
puts (" Image Type: "); print_type(hdr);
printf ("\n Data Size: %d Bytes = ", ntohl(hdr->ih_size));
print_size (ntohl(hdr->ih_size), "\n");
printf ("## Transferring control to RTEMS (at address %08lx) ...\n",
(ulong)entry_point);
- show_boot_progress (15);
+ SHOW_BOOT_PROGRESS (15);
/*
* RTEMS Parameters:
(*entry_point ) ( gd->bd );
}
-#if defined(CONFIG_CMD_ELF)
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
static void
do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong *len_ptr, int verify)
local_args[1] = str; /* and provide it via the arguments */
do_bootelf(cmdtp, 0, 2, local_args);
}
-#endif
+#endif /* CFG_CMD_ELF */
#ifdef CONFIG_LYNXKDI
static void
ulong offset, ulong addr, char *cmd)
{
int r;
- char *ep;
+ char *ep, *s;
ulong cnt;
image_header_t *hdr;
+ int jffs2 = 0;
+
+ s = strchr(cmd, '.');
+ if (s != NULL &&
+ (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")))
+ jffs2 = 1;
printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
cnt = nand->oobblock;
- r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ if (jffs2) {
+ nand_read_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = cnt;
+ opts.offset = offset;
+ opts.quiet = 1;
+ r = nand_read_opts(nand, &opts);
+ } else {
+ r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ }
+
if (r) {
puts("** Read error\n");
show_boot_progress (-56);
print_image_hdr(hdr);
cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
+ if (jffs2) {
+ nand_read_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = cnt;
+ opts.offset = offset;
+ opts.quiet = 1;
+ r = nand_read_opts(nand, &opts);
+ } else {
+ r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ }
- r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
show_boot_progress (-58);
if (argc > 3)
goto usage;
if (argc == 3)
- addr = simple_strtoul(argv[2], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
else
addr = CFG_LOAD_ADDR;
return nand_load_image(cmdtp, &nand_info[dev->id->num],
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
"nboot - boot from NAND device\n",
- "[partition] | [[[loadAddr] dev] offset]\n");
+ "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
#endif
{NAND_MFR_NATIONAL, "National"},
{NAND_MFR_RENESAS, "Renesas"},
{NAND_MFR_STMICRO, "ST Micro"},
+ {NAND_MFR_MICRON, "Micron"},
{0x0, "Unknown"}
};
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
#define CONFIG_CMD_EEPROM
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SUPPORT_VFAT
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_SUPPORT_VFAT
-#define CFG_NAND_LEGACY
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-#define CFG_NAND_LEGACY
-
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
#undef CONFIG_WATCHDOG /* watchdog disabled */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
-#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#if 1 /* test-only */
+
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_MICRON 0x2c
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
extern int nand_curr_device;
extern nand_info_t nand_info[];
+extern void nand_init(void);
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
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