]> git.sur5r.net Git - u-boot/commitdiff
Merge with git://www.denx.de/git/u-boot.git
authorStefan Roese <sr@denx.de>
Wed, 15 Aug 2007 19:06:27 +0000 (21:06 +0200)
committerStefan Roese <sr@denx.de>
Wed, 15 Aug 2007 19:06:27 +0000 (21:06 +0200)
17 files changed:
1  2 
board/esd/ash405/ash405.c
board/esd/common/auto_update.c
board/esd/common/esd405ep_nand.c
board/esd/wuh405/wuh405.c
common/cmd_nand.c
drivers/nand/nand_ids.c
include/configs/ASH405.h
include/configs/CMS700.h
include/configs/CPCI405.h
include/configs/CPCI4052.h
include/configs/CPCI405AB.h
include/configs/CPCI405DT.h
include/configs/HH405.h
include/configs/HUB405.h
include/configs/PLU405.h
include/configs/VOH405.h
include/configs/WUH405.h

index 0151d740c7ec1143d45f56004571f5900b05c35c,f41eb7b22cfb0176a6317f4a08114cde555f0866..8a5b03bcedb3d35a8ac79e247028a2cb2f27dea8
@@@ -219,13 -228,25 +219,12 @@@ long int initdram (int board_type
  
  /* ------------------------------------------------------------------------- */
  
 -int testdram (void)
 +void reset_phy(void)
  {
 -      /* TODO: XXX XXX XXX */
 -      printf ("test: 16 MB - ok\n");
 -
 -      return (0);
 -}
 -
 -/* ------------------------------------------------------------------------- */
 -
 -#if defined(CONFIG_CMD_NAND)
 -#include <linux/mtd/nand_legacy.h>
 -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 -
 -void nand_init(void)
 -{
 -      nand_probe(CFG_NAND_BASE);
 -      if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 -              print_size(nand_dev_desc[0].totlen, "\n");
 -      }
 -}
 +#ifdef CONFIG_LXT971_NO_SLEEP
 +      /*
 +       * Disable sleep mode in LXT971
 +       */
 +      lxt971_no_sleep();
  #endif
 +}
Simple merge
index 7ac4b835a77cc6d1dd9adb654fc3c5b74e17451e,0000000000000000000000000000000000000000..7bf68473d28372256ed13b5a64902d82945713f2
mode 100644,000000..100644
--- /dev/null
@@@ -1,87 -1,0 +1,87 @@@
- #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 +/*
 + * (C) Copyright 2007
 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +#include <common.h>
 +
- #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
++#if defined(CONFIG_CMD_NAND)
 +#include <asm/io.h>
 +#include <nand.h>
 +
 +/*
 + * hardware specific access to control-lines
 + */
 +static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
 +{
 +      switch(cmd) {
 +      case NAND_CTL_SETCLE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
 +              break;
 +      case NAND_CTL_CLRCLE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
 +              break;
 +      case NAND_CTL_SETALE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
 +              break;
 +      case NAND_CTL_CLRALE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
 +              break;
 +      case NAND_CTL_SETNCE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
 +              break;
 +      case NAND_CTL_CLRNCE:
 +              out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
 +              break;
 +      }
 +}
 +
 +
 +/*
 + * read device ready pin
 + */
 +static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
 +{
 +      if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
 +              return 1;
 +      return 0;
 +}
 +
 +
 +int board_nand_init(struct nand_chip *nand)
 +{
 +      /*
 +       * Set NAND-FLASH GPIO signals to defaults
 +       */
 +      out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
 +      out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
 +
 +      /*
 +       * Initialize nand_chip structure
 +       */
 +      nand->hwcontrol = esd405ep_nand_hwcontrol;
 +      nand->dev_ready = esd405ep_nand_device_ready;
 +      nand->eccmode = NAND_ECC_SOFT;
 +      nand->chip_delay = NAND_BIG_DELAY_US;
 +      nand->options = NAND_SAMSUNG_LP_OPTIONS;
 +      return 0;
 +}
++#endif
index 5fde8d65096377ef5ffcaf78aab9c4f96c42eeaf,61d1d6c0ce66ab868355261b3d99975e000b025b..dba3ce88840e2f629955a1fd069e48c17eb426b1
@@@ -212,7 -218,35 +212,5 @@@ long int initdram (int board_type
        mtdcr(memcfga, mem_mb0cf);
        val = mfdcr(memcfgd);
  
 -#if 0
 -      printf("\nmb0cf=%x\n", val); /* test-only */
 -      printf("strap=%x\n", mfdcr(strap)); /* test-only */
 -#endif
 -
        return (4*1024*1024 << ((val & 0x000e0000) >> 17));
  }
 -
 -/* ------------------------------------------------------------------------- */
 -
 -int testdram (void)
 -{
 -      /* TODO: XXX XXX XXX */
 -      printf ("test: 16 MB - ok\n");
 -
 -      return (0);
 -}
--
--/* ------------------------------------------------------------------------- */
 -
 -#if defined(CONFIG_CMD_NAND)
 -#include <linux/mtd/nand_legacy.h>
 -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 -
 -void nand_init(void)
 -{
 -      nand_probe(CFG_NAND_BASE);
 -      if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 -              print_size(nand_dev_desc[0].totlen, "\n");
 -      }
 -}
 -#endif
index 9ef31d456d66604716d47efffe25b5543f8cbe6d,c72612d0d6f3c828271d48ab5b4a053cb121576f..254a7755fcf440ad93d35653e6678e1bf6038da2
@@@ -489,23 -475,13 +481,24 @@@ static int nand_load_image(cmd_tbl_t *c
        printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
  
        cnt = nand->oobblock;
 -      r = nand_read(nand, offset, &cnt, (u_char *) addr);
 +      if (jffs2) {
 +              nand_read_options_t opts;
 +              memset(&opts, 0, sizeof(opts));
 +              opts.buffer     = (u_char*) addr;
 +              opts.length     = cnt;
 +              opts.offset     = offset;
 +              opts.quiet      = 1;
 +              r = nand_read_opts(nand, &opts);
 +      } else {
 +              r = nand_read(nand, offset, &cnt, (u_char *) addr);
 +      }
 +
        if (r) {
                puts("** Read error\n");
-               SHOW_BOOT_PROGRESS(-1);
+               show_boot_progress (-56);
                return 1;
        }
+       show_boot_progress (56);
  
        hdr = (image_header_t *) addr;
  
        print_image_hdr(hdr);
  
        cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
 +      if (jffs2) {
 +              nand_read_options_t opts;
 +              memset(&opts, 0, sizeof(opts));
 +              opts.buffer     = (u_char*) addr;
 +              opts.length     = cnt;
 +              opts.offset     = offset;
 +              opts.quiet      = 1;
 +              r = nand_read_opts(nand, &opts);
 +      } else {
 +              r = nand_read(nand, offset, &cnt, (u_char *) addr);
 +      }
  
 -      r = nand_read(nand, offset, &cnt, (u_char *) addr);
        if (r) {
                puts("** Read error\n");
-               SHOW_BOOT_PROGRESS(-1);
+               show_boot_progress (-58);
                return 1;
        }
+       show_boot_progress (58);
  
        /* Loading ok, update default load address */
  
@@@ -632,9 -604,9 +631,9 @@@ usage
  
  U_BOOT_CMD(nboot, 4, 1, do_nandboot,
        "nboot   - boot from NAND device\n",
 -      "[partition] | [[[loadAddr] dev] offset]\n");
 +      "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
  
- #endif                                /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+ #endif
  
  #else /* CFG_NAND_LEGACY */
  /*
Simple merge
Simple merge
index 96952118c0fcc6544ff64619e046577391ba862c,08ef9b5da6ba330cd760c0b929526f126e8c2b3d..1fd2b53974b071f7caaf488500e069e4600c5287
  #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  
- #define CONFIG_BOOTP_MASK     (CONFIG_BOOTP_DEFAULT | \
-                                CONFIG_BOOTP_DNS | \
-                                CONFIG_BOOTP_DNS2 | \
-                                CONFIG_BOOTP_SEND_HOSTNAME )
- #define CONFIG_COMMANDS             ( CONFIG_CMD_DFL  | \
-                               CFG_CMD_DHCP    | \
-                               CFG_CMD_BSP     | \
-                               CFG_CMD_PCI     | \
-                               CFG_CMD_IRQ     | \
-                               CFG_CMD_ELF     | \
-                               CFG_CMD_NAND    | \
-                               CFG_CMD_I2C     | \
-                               CFG_CMD_DATE    | \
-                               CFG_CMD_MII     | \
-                               CFG_CMD_PING    | \
-                               CFG_CMD_EEPROM  )
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
+ /*
+  * BOOTP options
+  */
+ #define CONFIG_BOOTP_SUBNETMASK
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_HOSTNAME
+ #define CONFIG_BOOTP_BOOTPATH
+ #define CONFIG_BOOTP_DNS
+ #define CONFIG_BOOTP_DNS2
+ #define CONFIG_BOOTP_SEND_HOSTNAME
+ /*
+  * Command line configuration.
+  */
+ #include <config_cmd_default.h>
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_BSP
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_IRQ
+ #define CONFIG_CMD_ELF
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_MII
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_EEPROM
  
 -#define CFG_NAND_LEGACY
 -
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_SDRAM_BANK0    1       /* init onboard SDRAM bank 0    */
index 9c0412932a0573f042b802bab82cc6dc75a687a3,0a4e1e9d30d1fd67f224366c78942e8201ce26ff..1b948f6382a2cc6b4119544fda76d98c1b3ea906
@@@ -80,9 -92,8 +92,6 @@@
  
  #define CONFIG_SUPPORT_VFAT
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
 -#define CFG_NAND_LEGACY
--
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_SDRAM_BANK0    1       /* init onboard SDRAM bank 0    */
index 2a328a63a37bc4d2126503b1698951e238c5b722,ceeba6e122e9368ca1956444adeec04f2e348c40..fb71c5fb040fe89a0182107adb2ad77ee4252de3
  #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
  #endif
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
 -#define CFG_NAND_LEGACY
--
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_SDRAM_BANK0    1       /* init onboard SDRAM bank 0    */
index 69466862b7a1c0252cc55fe35c6c3af3e7cbc18a,1aefbbac686e3f4b7d5441ac0284902993525229..49943195b72234abc47cd519de3f2df2a86a411d
  
  #define CONFIG_SUPPORT_VFAT
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
 -#define CFG_NAND_LEGACY
 -
--
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_SDRAM_BANK0    1       /* init onboard SDRAM bank 0    */
index 4ae240e915ad2ce6780e9397bb29099d0068f7c6,e2652e6aa6e130473399f8b16ca6958cb2ac0059..29f9292447871fed426c0d2ee4dba894c66fb7ab
  
  #undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
 -#define CFG_NAND_LEGACY
--
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_SDRAM_BANK0    1       /* init onboard SDRAM bank 0    */
index f36777a12d3728ce28ad94fed6a7de69cc10cd8b,00f481c4b52d0bc5ba3e0492bd19cb37bc397152..ea8e61a764bf25d25e60de0fc160aac6d75a9d8d
  #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
  #undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
 -#define CFG_NAND_LEGACY
--
  #undef  CONFIG_BZIP2   /* include support for bzip2 compressed images */
  #undef  CONFIG_WATCHDOG                       /* watchdog disabled            */
  
Simple merge
index ef5ecba220f38a39d38faf2c92443dd43426e195,54703731af7467fe673ca1f3e87fa1dcca138f70..4acbcd5e1ca7d2e59028ce7e98e50c807675c78a
  #define CONFIG_SUPPORT_VFAT
  
  #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 -#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
  
- /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
- #include <cmd_confdefs.h>
  #undef        CONFIG_WATCHDOG                 /* watchdog disabled            */
  
  #define CONFIG_RTC_MC146818           /* DS1685 is MC146818 compatible*/
Simple merge
Simple merge