#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
-#ifdef CONFIG_BOOTCOUNT_LIMIT
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
#include <asm/immap_qe.h>
#include <asm/io.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE))
+ (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
#include <asm/immap_qe.h>
void fdt_fixup_muram (void *blob)
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+ (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
fdt_fixup_muram (blob);
#endif
}
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ids8247.o
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
+ /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
+#if defined(CONFIG_SYS_I2C_SOFT)
+ /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
+ /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+ /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
+#endif
+ /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
+ /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
+ /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
+ /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
+ /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
+ /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
+ /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
+ /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
+ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
+ /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
+ /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
+ /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
+ /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
+ /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
+ /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
+ /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
+ /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
+ /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
+ /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
+ /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
+#endif
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
+ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
+ /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+ puts ("Board: IDS 8247\n");
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+ ulong orx, volatile uchar * base)
+{
+ volatile uchar c = 0xff;
+ volatile uint *sdmr_ptr;
+ volatile uint *orx_ptr;
+ ulong maxsize, size;
+ int i;
+
+ /* We must be able to test a location outsize the maximum legal size
+ * to find out THAT we are outside; but this address still has to be
+ * mapped by the controller. That means, that the initial mapping has
+ * to be (at least) twice as large as the maximum expected size.
+ */
+ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+ sdmr_ptr = &memctl->memc_psdmr;
+ orx_ptr = &memctl->memc_or2;
+
+ *orx_ptr = orx;
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+ */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_PREA;
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_MRW;
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *base = c;
+
+ size = get_ram_size((long *)base, maxsize);
+ *orx_ptr = orx | ~(size - 1);
+
+ return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+
+ long psize;
+
+ psize = 16 * 1024 * 1024;
+
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ /* 60x SDRAM setup:
+ */
+ psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ icache_enable ();
+
+ return (psize);
+}
+
+int misc_init_r (void)
+{
+ gd->bd->bi_flashstart = 0xff800000;
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <asm/io.h>
+
+static u8 hwctl;
+
+static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE ) {
+ hwctl |= 0x1;
+ writeb(0x00, (this->IO_ADDR_W + 0x0a));
+ } else {
+ hwctl &= ~0x1;
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if ( ctrl & NAND_ALE ) {
+ hwctl |= 0x2;
+ writeb(0x00, (this->IO_ADDR_W + 0x09));
+ } else {
+ hwctl &= ~0x2;
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if ( (ctrl & NAND_NCE) != NAND_NCE)
+ writeb(0x00, (this->IO_ADDR_W + 0x0c));
+ else
+ writeb(0x00, (this->IO_ADDR_W + 0x08));
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+
+}
+
+static u_char ids_nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *this = mtd->priv;
+
+ return readb(this->IO_ADDR_R);
+}
+
+static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ writeb(buf[i], (nand->IO_ADDR_W + 0x02));
+ else if (hwctl & 0x2)
+ writeb(buf[i], (nand->IO_ADDR_W + 0x01));
+ else
+ writeb(buf[i], nand->IO_ADDR_W);
+ }
+}
+
+static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ buf[i] = readb(this->IO_ADDR_R);
+ }
+}
+
+static int ids_nand_dev_ready(struct mtd_info *mtd)
+{
+ /* constant delay (see also tR in the datasheet) */
+ udelay(12);
+ return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+
+ /* Reference hardware control function */
+ nand->cmd_ctrl = ids_nand_hwctrl;
+ nand->read_byte = ids_nand_read_byte;
+ nand->write_buf = ids_nand_write_buf;
+ nand->read_buf = ids_nand_read_buf;
+ nand->dev_ready = ids_nand_dev_ready;
+ nand->chip_delay = 12;
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup( blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ids8313.o
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/** CPLD contains the info about:
+ * - board type: *pCpld & 0xF0
+ * - hw-revision: *pCpld & 0x0F
+ * - cpld-revision: *pCpld+1
+ */
+int checkboard(void)
+{
+ char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
+ u8 u8Vers = readb(pcpld);
+ u8 u8Revs = readb(pcpld + 1);
+
+ printf("Board: ");
+ switch (u8Vers & 0xF0) {
+ case '\x40':
+ printf("CU73X");
+ break;
+ case '\x50':
+ printf("CC73X");
+ break;
+ default:
+ printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
+ return 0;
+ }
+ printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
+ u8Vers & 0x0F, u8Revs & 0xFF);
+ return 0;
+}
+
+/*
+ * fixed sdram init
+ */
+int fixed_sdram(unsigned long config)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+ sync();
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ udelay(50000);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], config);
+
+ /* currently we use only one CS, so disable the other banks */
+ out_be32(&im->ddr.cs_config[1], 0);
+ out_be32(&im->ddr.cs_config[2], 0);
+ out_be32(&im->ddr.cs_config[3], 0);
+
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ sync();
+ udelay(300);
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ /* now check the real size */
+ disable_addr_trans();
+ msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans();
+#endif
+ return msize;
+}
+
+static int setup_sdram(void)
+{
+ u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+ long int size_01, size_02;
+
+ size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+ size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
+
+ if (size_01 > size_02)
+ msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+ else
+ msize = size_02;
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ fsl_lbc_t *lbc = &im->im_lbc;
+ u32 msize = 0;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ msize = setup_sdram();
+
+ out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ sync();
+
+ return msize;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+/* gpio mask for spi_cs */
+#define IDSCPLD_SPI_CS_MASK 0x00000001
+/* spi_cs multiplexed through cpld */
+#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
+
+#if defined(CONFIG_MISC_INIT_R)
+/* srp umcr mask for rts */
+#define IDSUMCR_RTS_MASK 0x04
+int misc_init_r(void)
+{
+ /*srp*/
+ duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
+ duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
+
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* deactivate spi_cs channels */
+ out_8(spi_base, 0);
+ /* deactivate the spi_cs */
+ setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
+ /*srp - deactivate rts*/
+ out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
+ out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
+
+
+ gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* select the spi_cs channel */
+ out_8(spi_base, 1 << slave->cs);
+ /* activate the spi_cs */
+ clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* select the spi_cs channel */
+ out_8(spi_base, 1 << slave->cs);
+ /* deactivate the spi_cs */
+ setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+#endif /* CONFIG_HARD_SPI */
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ids8247.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <libfdt_env.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
- /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
-#else /* normal I/O port pins */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
-#endif
- /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
- /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
- /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
- /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
- /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
- /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
- /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
- /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
- /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
- /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
- /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
- /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
- /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- puts ("Board: IDS 8247\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- long psize;
-
- psize = 16 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-int misc_init_r (void)
-{
- gd->bd->bi_flashstart = 0xff800000;
- return 0;
-}
-
-#if defined(CONFIG_CMD_NAND)
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-#include <asm/io.h>
-
-static u8 hwctl;
-
-static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE ) {
- hwctl |= 0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x0a));
- } else {
- hwctl &= ~0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( ctrl & NAND_ALE ) {
- hwctl |= 0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x09));
- } else {
- hwctl &= ~0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( (ctrl & NAND_NCE) != NAND_NCE)
- writeb(0x00, (this->IO_ADDR_W + 0x0c));
- else
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
-}
-
-static u_char ids_nand_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
-
- return readb(this->IO_ADDR_R);
-}
-
-static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *nand = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- if (hwctl & 0x1)
- writeb(buf[i], (nand->IO_ADDR_W + 0x02));
- else if (hwctl & 0x2)
- writeb(buf[i], (nand->IO_ADDR_W + 0x01));
- else
- writeb(buf[i], nand->IO_ADDR_W);
- }
-}
-
-static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- buf[i] = readb(this->IO_ADDR_R);
- }
-}
-
-static int ids_nand_dev_ready(struct mtd_info *mtd)
-{
- /* constant delay (see also tR in the datasheet) */
- udelay(12);
- return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-
- /* Reference hardware control function */
- nand->cmd_ctrl = ids_nand_hwctrl;
- nand->read_byte = ids_nand_read_byte;
- nand->write_buf = ids_nand_write_buf;
- nand->read_buf = ids_nand_read_buf;
- nand->dev_ready = ids_nand_dev_ready;
- nand->chip_delay = 12;
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
-Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * Sergej Stepanov <ste@ids.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC831x
+#define CONFIG_MPC8313
+#define CONFIG_IDS8313
+
+#define CONFIG_FSL_ELBC
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
+#define CONFIG_AUTOBOOT_DELAY_STR "ids"
+#define CONFIG_BOOT_RETRY_TIME 900
+#define CONFIG_BOOT_RETRY_MIN 30
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR 0xF0000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.000MHz, then
+ * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_8BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_MII |\
+ HRCWH_TSEC2M_IN_MII |\
+ HRCWH_BIG_ENDIAN)
+
+#define CONFIG_SYS_SICRH 0x00000000
+#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
+ HID0_ENABLE_INSTRUCTION_CACHE |\
+ HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
+
+/*
+ * Definitions for initial stack pointer and data area (in DCACHE )
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
+ (0xFF << LBCR_BMT_SHIFT) |\
+ 0xF)
+
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
+
+/*
+ * Internal Definitions
+ */
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters,
+ * as this board has not the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
+ 0x00010000 |\
+ CSCONFIG_ROW_BIT_13 |\
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
+ CSCONFIG_BANK_BIT_3)
+
+#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
+#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
+ (3 << TIMING_CFG0_WRT_SHIFT) |\
+ (3 << TIMING_CFG0_RRT_SHIFT) |\
+ (3 << TIMING_CFG0_WWT_SHIFT) |\
+ (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
+ (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
+ (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
+ (7 << TIMING_CFG1_CASLAT_SHIFT) |\
+ (4 << TIMING_CFG1_REFREC_SHIFT) |\
+ (4 << TIMING_CFG1_WRREC_SHIFT) |\
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
+ (2 << TIMING_CFG1_WRTORD_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
+ (5 << TIMING_CFG2_CPO_SHIFT) |\
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
+ (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
+ (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
+ (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+
+#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
+ (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
+ SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
+ SDRAM_CFG_DBW_32 |\
+ SDRAM_CFG_SDRAM_TYPE_DDR2)
+
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
+ (0x0242 << SDRAM_MODE_SD_SHIFT))
+#define CONFIG_SYS_DDR_MODE_2 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
+ DDRCDR_PZ_NOMZ |\
+ DDRCDR_NZ_NOMZ |\
+ DDRCDR_ODT |\
+ DDRCDR_M_ODR |\
+ DDRCDR_Q_DRN)
+
+/*
+ * on-board devices
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_HARD_SPI
+#define CONFIG_HARD_I2C
+
+/*
+ * NOR FLASH setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_FLASH_SHOW_PROGRESS 50
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE 0xFF800000
+#define CONFIG_SYS_FLASH_SIZE 8
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
+ BR_PS_8 |\
+ BR_MS_GPCM |\
+ BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+ OR_GPCM_SCY_10 |\
+ OR_GPCM_EHTR |\
+ OR_GPCM_TRLX |\
+ OR_GPCM_CSNT |\
+ OR_GPCM_EAD)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+/*
+ * NAND FLASH setup
+ */
+#define CONFIG_SYS_NAND_BASE 0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define NAND_CACHE_PAGES 64
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
+ (2<<BR_DECC_SHIFT) |\
+ BR_PS_8 |\
+ BR_MS_FCM |\
+ BR_V)
+
+#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
+ OR_FCM_PGS |\
+ OR_FCM_CSCT |\
+ OR_FCM_CST |\
+ OR_FCM_CHT |\
+ OR_FCM_SCY_4 |\
+ OR_FCM_TRLX |\
+ OR_FCM_EHTR |\
+ OR_FCM_RST)
+
+/*
+ * MRAM setup
+ */
+#define CONFIG_SYS_MRAM_BASE 0xE2000000
+#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
+ BR_PS_8 |\
+ BR_MS_GPCM |\
+ BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
+
+/*
+ * CPLD setup
+ */
+#define CONFIG_SYS_CPLD_BASE 0xE3000000
+#define CONFIG_SYS_CPLD_SIZE 0x8000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
+ BR_PS_8 |\
+ BR_MS_GPCM |\
+ BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
+
+/*
+ * HW-Watchdog
+ */
+#define CONFIG_WATCHDOG 1
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+/*
+ * I2C setup
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/*
+ * SPI setup
+ */
+#ifdef CONFIG_HARD_SPI
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0x00000001
+#define CONFIG_SYS_GPIO1_DAT 0x00000001
+#endif
+
+/*
+ * Ethernet setup
+ */
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 0x3
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM 3
+
+/*
+ * BAT's
+ */
+#define CONFIG_HIGH_BATS
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
+ BATL_PP_10)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
+ BATU_BL_256M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* Initial RAM @ 0xFD000000 */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
+ BATL_PP_10 |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
+ BATU_BL_256K |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* FLASH @ 0xFF800000 */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
+ BATL_PP_10 |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
+ BATU_BL_8M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
+ BATL_PP_10 |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/* IMMRBAR @ 0xF0000000 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
+ BATL_PP_10 |\
+ BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
+ BATU_BL_128M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
+#define CONFIG_SYS_IBAT6L (0xE0000000 |\
+ BATL_PP_10 |\
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (0xE0000000 |\
+ BATU_BL_256M |\
+ BATU_VS |\
+ BATU_VP)
+#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+/*
+ * U-Boot environment setup
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
+ + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+
+#define CONFIG_NETDEV eth1
+#define CONFIG_HOSTNAME ids8313
+#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
+#define CONFIG_BOOTFILE "ids8313/uImage"
+#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
+#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
+#define CONFIG_LOADADDR 0x400000
+#define CONFIG_CMD_ENV_FLAGS
+#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_HZ 1000
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x00C00000
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_MII
+#define CONFIG_LOADS_ECHO
+#define CONFIG_TIMESTAMP
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run nfsboot\\\" " \
+ "to mount root filesystem over NFS;echo"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "run boot_cramfs"
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV "0"
+
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
+#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \
+ "768k(BOOT-BIN)," \
+ "128k(BOOT-ENV),128k(BOOT-REDENV);" \
+ "e1000000.flash:-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" __stringify(CONFIG_NETDEV) "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +${filesize}; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +${filesize}; " \
+ "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " ${filesize}; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +${filesize}; " \
+ "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " ${filesize}\0" \
+ "console=ttyS0\0" \
+ "fdtaddr=0x780000\0" \
+ "kernel_addr=ff800000\0" \
+ "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
+ "setbootargs=setenv bootargs " \
+ "root=${rootdev} rw console=${console}," \
+ "${baudrate} ${othbootargs}\0" \
+ "setipargs=setenv bootargs root=${rootdev} rw " \
+ "nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off " \
+ "console=${console},${baudrate} ${othbootargs}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setipargs;run addmtd;" \
+ "tftp ${loadaddr} ${bootfile};" \
+ "tftp ${fdtaddr} ${fdtfile};" \
+ "fdt addr ${fdtaddr};" \
+ "bootm ${loadaddr} - ${fdtaddr}"
+
+/* UBI Support */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+
+/* bootcount support */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_I2C
+#define CONFIG_BOOTCOUNT_ALEN 1
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
+
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_FIT
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_CMD_FDT
+#define CONFIG_CMD_HASH
+#define CONFIG_RSA
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+#define CONFIG_OF_CONTROL
+
+#endif /* __CONFIG_H */
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