]> git.sur5r.net Git - u-boot/commitdiff
ARMV7: Versatile Express Coretile CortexA9x4 support
authorMatt Waddel <matt.waddel@linaro.org>
Thu, 7 Oct 2010 21:48:45 +0000 (15:48 -0600)
committerWolfgang Denk <wd@denx.de>
Wed, 13 Oct 2010 07:59:39 +0000 (09:59 +0200)
Adds support for the ARM quad-core Cortex-A9 processor

This system includes a motherboard(Versatile Express), daughterboard
(Coretile), and SOC(Cortex-A9 quad core).  The serial port, ethernet,
and flash systems work with these additions.  The naming convention
is:
   SOC -> CortexA9 quad core = ca9x4
   daughterboard -> Coretile = ct
   motherboard -> Versatile Express = vxp
This gives ca9x4_ct_vxp.c as the board support file.

Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
MAINTAINERS
MAKEALL
arch/arm/include/asm/arch-armv7/sysctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-armv7/systimer.h [new file with mode: 0644]
arch/arm/include/asm/arch-armv7/wdt.h [new file with mode: 0644]
board/armltd/vexpress/Makefile [new file with mode: 0644]
board/armltd/vexpress/ca9x4_ct_vxp.c [new file with mode: 0644]
board/armltd/vexpress/config.mk [new file with mode: 0644]
board/armltd/vexpress/u-boot.lds [new file with mode: 0644]
boards.cfg
include/configs/ca9x4_ct_vxp.h [new file with mode: 0644]

index 785fccf56cce31d735f6b82d1871b997d3e4c820..a394ac942308c3731d509e42ec29569c743351ed 100644 (file)
@@ -800,6 +800,10 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
        SFFSDR          ARM926EJS
 
+Matt Waddel <matt.waddel@linaro.org>
+
+       ca9x4_ct_vxp    ARM ARMV7 (Quad Core)
+
 Prafulla Wadaskar <prafulla@marvell.com>
 
        mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
diff --git a/MAKEALL b/MAKEALL
index 1b506d679fde3413922645d222fa9ba0afbb1afc..abceccd838648a7c850f973931c74b35bfa1f22d 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -489,6 +489,7 @@ LIST_ARM11="                        \
 #########################################################################
 LIST_ARMV7="           \
        am3517_evm              \
+       ca9x4_ct_vxp            \
        devkit8000              \
        mx51evk                 \
        omap3_beagle            \
diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h
new file mode 100644 (file)
index 0000000..4e45167
--- /dev/null
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYSCTRL_H_
+#define _SYSCTRL_H_
+
+/* System controller (SP810) register definitions */
+#define SP810_TIMER0_ENSEL     (1 << 15)
+#define SP810_TIMER1_ENSEL     (1 << 17)
+#define SP810_TIMER2_ENSEL     (1 << 19)
+#define SP810_TIMER3_ENSEL     (1 << 21)
+
+struct sysctrl {
+       u32 scctrl;             /* 0x000 */
+       u32 scsysstat;
+       u32 scimctrl;
+       u32 scimstat;
+       u32 scxtalctrl;
+       u32 scpllctrl;
+       u32 scpllfctrl;
+       u32 scperctrl0;
+       u32 scperctrl1;
+       u32 scperen;
+       u32 scperdis;
+       u32 scperclken;
+       u32 scperstat;
+       u32 res1[0x006];
+       u32 scflashctrl;        /* 0x04c */
+       u32 res2[0x3a4];
+       u32 scsysid0;           /* 0xee0 */
+       u32 scsysid1;
+       u32 scsysid2;
+       u32 scsysid3;
+       u32 scitcr;
+       u32 scitir0;
+       u32 scitir1;
+       u32 scitor;
+       u32 sccntctrl;
+       u32 sccntdata;
+       u32 sccntstep;
+       u32 res3[0x32];
+       u32 scperiphid0;        /* 0xfe0 */
+       u32 scperiphid1;
+       u32 scperiphid2;
+       u32 scperiphid3;
+       u32 scpcellid0;
+       u32 scpcellid1;
+       u32 scpcellid2;
+       u32 scpcellid3;
+};
+#endif /* _SYSCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h
new file mode 100644 (file)
index 0000000..e745e37
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYSTIMER_H_
+#define _SYSTIMER_H_
+
+/* AMBA timer register base address */
+#define SYSTIMER_BASE          0x10011000
+
+#define SYSHZ_CLOCK            1000000         /* Timers -> 1Mhz */
+#define SYSTIMER_RELOAD                0xFFFFFFFF
+#define SYSTIMER_EN            (1 << 7)
+#define SYSTIMER_32BIT         (1 << 1)
+
+struct systimer {
+       u32 timer0load;         /* 0x00 */
+       u32 timer0value;
+       u32 timer0control;
+       u32 timer0intclr;
+       u32 timer0ris;
+       u32 timer0mis;
+       u32 timer0bgload;
+       u32 timer1load;         /* 0x20 */
+       u32 timer1value;
+       u32 timer1control;
+       u32 timer1intclr;
+       u32 timer1ris;
+       u32 timer1mis;
+       u32 timer1bgload;
+};
+#endif /* _SYSTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h
new file mode 100644 (file)
index 0000000..ee74c38
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* Watchdog timer (SP805) register base address */
+#define WDT_BASE       0x100E5000
+
+#define WDT_EN         0x2
+#define WDT_RESET_LOAD 0x0
+
+struct wdt {
+       u32 wdogload;           /* 0x000 */
+       u32 wdogvalue;
+       u32 wdogcontrol;
+       u32 wdogintclr;
+       u32 wdogris;
+       u32 wdogmis;
+       u32 res1[0x2F9];
+       u32 wdoglock;           /* 0xC00 */
+       u32 res2[0xBE];
+       u32 wdogitcr;           /* 0xF00 */
+       u32 wdogitop;
+       u32 res3[0x35];
+       u32 wdogperiphid0;      /* 0xFE0 */
+       u32 wdogperiphid1;
+       u32 wdogperiphid2;
+       u32 wdogperiphid3;
+       u32 wdogpcellid0;
+       u32 wdogpcellid1;
+       u32 wdogpcellid2;
+       u32 wdogpcellid3;
+};
+
+#endif /* _WDT_H_ */
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
new file mode 100644 (file)
index 0000000..ee5c0d8
--- /dev/null
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := ca9x4_ct_vxp.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c
new file mode 100644 (file)
index 0000000..48dfc8c
--- /dev/null
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+       printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+       __asm__ volatile ("1:\n"
+               "subs %0, %1, #1\n"
+               "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+       gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+       gd->flags = 0;
+
+       icache_enable();
+       flash__init();
+       vexpress_timer_init();
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC911X
+       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+       return rc;
+}
+
+static void flash__init(void)
+{
+       /* Setup the sytem control register to allow writing to flash */
+       writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+              &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = get_ram_size(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+}
+
+int timer_init(void)
+{
+       return 0;
+}
+
+/*
+ * Start timer:
+ *    Setup a 32 bit timer, running at 1KHz
+ *    Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+       /*
+        * Set clock frequency in system controller:
+        *   VEXPRESS_REFCLK is 32KHz
+        *   VEXPRESS_TIMCLK is 1MHz
+        */
+       writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+              SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+              readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+       /*
+        * Set Timer0 to be:
+        *   Enabled, free running, no interrupt, 32-bit, wrapping
+        */
+       writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+       writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+       writel(SYSTIMER_EN | SYSTIMER_32BIT | \
+              readl(&systimer_base->timer0control), \
+              &systimer_base->timer0control);
+
+       reset_timer_masked();
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(ulong addr)
+{
+       writeb(WDT_EN, &wdt_base->wdogcontrol);
+       writel(WDT_RESET_LOAD, &wdt_base->wdogload);
+       while (1)
+               ;
+}
+
+/*
+ * Delay x useconds AND perserve advance timstamp value
+ *     assumes timer is ticking at 1 msec
+ */
+void udelay(ulong usec)
+{
+       ulong tmo, tmp;
+
+       tmo = usec / 1000;
+       tmp = get_timer(0);     /* get current timestamp */
+
+       /*
+        * If setting this forward will roll time stamp then
+        * reset "advancing" timestamp to 0 and set lastdec value
+        * otherwise set the advancing stamp to the wake up time
+        */
+       if ((tmo + tmp + 1) < tmp)
+               reset_timer_masked();
+       else
+               tmo += tmp;
+
+       while (get_timer_masked() < tmo)
+               ; /* loop till wakeup event */
+}
+
+ulong get_timer(ulong base)
+{
+       return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+       lastdec = readl(&systimer_base->timer0value) / 1000;
+       timestamp = 0;
+}
+
+void reset_timer(void)
+{
+       reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+       ulong now = readl(&systimer_base->timer0value) / 1000;
+
+       if (lastdec >= now) {   /* normal mode (non roll) */
+               timestamp += lastdec - now;
+       } else {                /* count down timer overflowed */
+               /*
+                * nts = ts + ld - now
+                * ts = old stamp, ld = time before passing through - 1
+                * now = amount of time after passing though - 1
+                * nts = new "advancing time stamp"
+                */
+               timestamp += lastdec + SYSTIMER_RELOAD - now;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+       return readl((u32 *)SYS_ID);
+}
diff --git a/board/armltd/vexpress/config.mk b/board/armltd/vexpress/config.mk
new file mode 100644 (file)
index 0000000..2d797d7
--- /dev/null
@@ -0,0 +1,23 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Linux-Kernel is expected to be at 0x60008000
+#
+TEXT_BASE = 0x60800000
+LDSCRIPT := $(SRCTREE)/board/armltd/vexpress/u-boot.lds
diff --git a/board/armltd/vexpress/u-boot.lds b/board/armltd/vexpress/u-boot.lds
new file mode 100644 (file)
index 0000000..5ac62f2
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+       . = ALIGN(4);
+       .text   :
+       {
+               arch/arm/cpu/armv7/start.o      (.text)
+               *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
+
+       . = ALIGN(4);
+       .data : { *(.data)
+       __datarel_start = .;
+               *(.data.rel)
+       __datarelrolocal_start = .;
+               *(.data.rel.ro.local)
+       __datarellocal_start = .;
+               *(.data.rel.local)
+       __datarelro_start = .;
+               *(.data.rel.ro)
+       }
+
+       __got_start = .;
+       . = ALIGN(4);
+       .got : { *(.got) }
+       __got_end = .;
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
index 62ffa420ee0c48028a0eeffab5c2d009a5e07256..38fa5703092df11a0723ce4c860e825a5e54c209 100644 (file)
@@ -252,6 +252,7 @@ imx27lite   arm     arm926ejs       imx27lite       logicpd         mx27
 magnesium      arm     arm926ejs       imx27lite       logicpd         mx27
 omap5912osk    arm     arm926ejs       -               ti              omap
 edminiv2       arm     arm926ejs       -               LaCie           orion5x
+ca9x4_ct_vxp   arm     armv7           vexpress        armltd
 omap3_overo    arm     armv7           overo           -               omap3
 omap3_pandora  arm     armv7           pandora         -               omap3
 omap3_zoom1    arm     armv7           zoom1           logicpd         omap3
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
new file mode 100644 (file)
index 0000000..5547d55
--- /dev/null
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board info register */
+#define SYS_ID                         0x10000000
+#define CONFIG_REVISION_TAG            1
+
+/* High Level Configuration Options */
+#define CONFIG_ARMV7                   1
+
+#define CONFIG_SYS_MEMTEST_START       0x60000000
+#define CONFIG_SYS_MEMTEST_END         0x20000000
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_L2_OFF                  1
+#define CONFIG_INITRD_TAG              1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE       128
+
+#define SCTL_BASE                      0x10001000
+#define VEXPRESS_FLASHPROG_FLVPPEN     (1 << 0)
+
+/* SMSC9115 Ethernet from SMSC9118 family */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X                 1
+#define CONFIG_SMC911X_32_BIT          1
+#define CONFIG_SMC911X_BASE            0x4E000000
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK             24000000
+#define CONFIG_PL01x_PORTS             {(void *)CONFIG_SYS_SERIAL0, \
+                                        (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX              0
+
+#define CONFIG_BAUDRATE                        38400
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0             0x10009000
+#define CONFIG_SYS_SERIAL1             0x1000A000
+
+/* Command line configuration */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_RUN
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION           1
+#define CONFIG_MMC                     1
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR           0x60008000      /* load address */
+#define LINUX_BOOT_PARAM_ADDR          0x60000200
+#define CONFIG_BOOTDELAY               2
+
+/* Stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE               (128 * 1024)    /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ           (4 * 1024)      /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ           (4 * 1024)      /* FIQ stack */
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           2
+#define PHYS_SDRAM_1                   0x60000000      /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2                   0x80000000      /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE              0x20000000      /* 512 MB */
+#define PHYS_SDRAM_2_SIZE              0x20000000      /* 512 MB */
+
+/* additions for new relocation code */
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_END                0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_SDRAM_BASE + \
+                                        CONFIG_SYS_INIT_RAM_END - \
+                                        CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Basic environment settings */
+#define CONFIG_BOOTCOMMAND             "run bootflash;"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+               "loadaddr=0x80008000\0" \
+               "initrd=0x61000000\0" \
+               "kerneladdr=0x44100000\0" \
+               "initrdaddr=0x44800000\0" \
+               "maxinitrd=0x1800000\0" \
+               "console=ttyAMA0,38400n8\0" \
+               "dram=1024M\0" \
+               "root=/dev/sda1 rw\0" \
+               "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
+                       "24M@0x2000000(initrd)\0" \
+               "flashargs=setenv bootargs root=${root} console=${console} " \
+                       "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
+                       "devtmpfs.mount=0  vmalloc=256M\0" \
+               "bootflash=run flashargs; " \
+                       "cp ${initrdaddr} ${initrd} ${maxinitrd}; " \
+                       "bootm ${kerneladdr} ${initrd}\0"
+
+/* FLASH and environment organization */
+#define PHYS_FLASH_SIZE                        0x04000000      /* 64MB */
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_FLASH_CFI_DRIVER                1
+#define CONFIG_SYS_FLASH_SIZE          0x04000000
+#define CONFIG_SYS_MAX_FLASH_BANKS     2
+#define CONFIG_SYS_FLASH_BASE0         0x40000000
+#define CONFIG_SYS_FLASH_BASE1         0x44000000
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE0
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT      259             /* Max sectors */
+#define FLASH_MAX_SECTOR_SIZE          0x00040000      /* 256 KB sectors */
+
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE                        FLASH_MAX_SECTOR_SIZE
+
+/*
+ * Amount of flash used for environment:
+ * We don't know which end has the small erase blocks so we use the penultimate
+ * sector location for the environment
+ */
+#define CONFIG_ENV_SECT_SIZE           FLASH_MAX_SECTOR_SIZE
+#define CONFIG_ENV_OVERWRITE           1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_IN_FLASH         1
+#define CONFIG_ENV_OFFSET              (PHYS_FLASH_SIZE - \
+                                       (2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE1 + \
+                                        CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_PROTECTION    /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE0, \
+                                         CONFIG_SYS_FLASH_BASE1 }
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT              "VExpress# "
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMD_SOURCE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING         1
+#define CONFIG_SYS_MAXARGS             16      /* max command args */
+
+#endif