]> git.sur5r.net Git - u-boot/commitdiff
mmc: sdhci: Read capabilities register1 and update host caps
authorSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Thu, 19 Apr 2018 07:07:08 +0000 (12:37 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 11 May 2018 08:22:26 +0000 (10:22 +0200)
This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/mmc/sdhci.c
include/sdhci.h

index efc5a62e619fb5407413f97f73687e630e857111..8971a1122c932dd6011cd9fc75463e610452d4d4 100644 (file)
@@ -557,7 +557,7 @@ static const struct mmc_ops sdhci_ops = {
 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
                u32 f_max, u32 f_min)
 {
-       u32 caps, caps_1;
+       u32 caps, caps_1 = 0;
 
        caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 
@@ -638,6 +638,32 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
                cfg->host_caps &= ~MMC_MODE_HS_52MHz;
        }
 
+       if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
+               caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+
+       if (!(cfg->voltages & MMC_VDD_165_195) ||
+           (host->quirks & SDHCI_QUIRK_NO_1_8_V))
+               caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+                           SDHCI_SUPPORT_DDR50);
+
+       if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+                     SDHCI_SUPPORT_DDR50))
+               cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
+
+       if (caps_1 & SDHCI_SUPPORT_SDR104) {
+               cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
+               /*
+                * SD3.0: SDR104 is supported so (for eMMC) the caps2
+                * field can be promoted to support HS200.
+                */
+               cfg->host_caps |= MMC_CAP(MMC_HS_200);
+       } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
+               cfg->host_caps |= MMC_CAP(UHS_SDR50);
+       }
+
+       if (caps_1 & SDHCI_SUPPORT_DDR50)
+               cfg->host_caps |= MMC_CAP(UHS_DDR50);
+
        if (host->host_caps)
                cfg->host_caps |= host->host_caps;
 
index 8ca632f3e0beba23c4b5b77ff878189729e46269..bef37df982e4e9e17d3a223d4c81377812f4bb13 100644 (file)
 #define  SDHCI_CAN_64BIT       BIT(28)
 
 #define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_SUPPORT_SDR50   0x00000001
+#define  SDHCI_SUPPORT_SDR104  0x00000002
+#define  SDHCI_SUPPORT_DDR50   0x00000004
+#define  SDHCI_USE_SDR50_TUNING        0x00002000
+
 #define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT 16
 
 #define SDHCI_QUIRK_BROKEN_HISPD_MODE  BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD      (1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8          (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V           (1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;