]> git.sur5r.net Git - u-boot/commitdiff
sunxi: dram: Improve DQS gate data training error handling
authorSiarhei Siamashka <siarhei.siamashka@gmail.com>
Sun, 3 Aug 2014 02:32:49 +0000 (05:32 +0300)
committerHans de Goede <hdegoede@redhat.com>
Tue, 12 Aug 2014 06:42:33 +0000 (08:42 +0200)
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
arch/arm/cpu/armv7/sunxi/dram.c
arch/arm/include/asm/arch-sunxi/dram.h

index 6f98c6a3bb512f1e0698fe243c8564f079f00b99..47017d2df18bf1a4c4b9ef3709823694db118cae 100644 (file)
@@ -357,9 +357,7 @@ static int dramc_scan_readpipe(void)
        u32 reg_val;
 
        /* data training trigger */
-#ifdef CONFIG_SUN7I
        clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
-#endif
        setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
        /* check whether data training process has completed */
index 3c2925625d17c51fd5c3043e9aac20c167518d44..11e35077f438eef2897a97385c523a6cf4ed3130 100644 (file)
@@ -133,7 +133,9 @@ struct dram_para {
 #define DRAM_DCR_MODE_SEQ 0x0
 #define DRAM_DCR_MODE_INTERLEAVE 0x1
 
-#define DRAM_CSR_FAILED (0x1 << 20)
+#define DRAM_CSR_DTERR  (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
 
 #define DRAM_DRR_TRFC(n) ((n) & 0xff)
 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)