/*
* Set endianess and reset lcd controller 0 (small)
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
+
+ /* set reset to low */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST);
udelay(10); /* wait 10us */
- if (config == 1)
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
- else
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+ if (config == 1) {
+ /* big-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+ } else {
+ /* little-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+ }
udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
+ /* set reset to high */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_LCD0_RST);
} else {
/*
* Set endianess and reset lcd controller 1 (big)
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
+
+ /* set reset to low */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST);
udelay(10); /* wait 10us */
- if (config == 1)
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
- else
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+ if (config == 1) {
+ /* big-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+ } else {
+ /* little-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+ }
udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
+ /* set reset to high */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_LCD1_RST);
}
/*
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
}
#endif /* CFG_LCD_ENDIAN */
-void lcd_bmp(uchar *logo_bmp)
+int lcd_bmp(uchar *logo_bmp)
{
int i;
uchar *ptr;
len = CFG_VIDEO_LOGO_MAX_SIZE;
dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
- printf("Error: malloc in gunzip failed!\n");
- return;
+ printf("Error: malloc for gunzip failed!\n");
+ return 1;
+ }
+ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
+ (uchar *)logo_bmp, &len) != 0) {
+ free(dst);
+ return 1;
+ }
+ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ printf("Image could be truncated"
+ " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
}
- if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0)
- return;
- if (len == CFG_VIDEO_LOGO_MAX_SIZE)
- printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
/*
* Check for bmp mark 'BM'
if (*(ushort *)dst != 0x424d) {
printf("LCD: Unknown image format!\n");
free(dst);
- return;
+ return 1;
}
} else {
/*
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
free(dst);
- return;
+ return 1;
}
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
if (bpp == 24) {
for (x = 0; x < width; x++) {
/*
- * Generate epson 16bpp fb-format from 24bpp image
+ * Generate epson 16bpp fb-format
+ * from 24bpp image
*/
b = *bmp++ >> 3;
g = *bmp++ >> 2;
r = *bmp++ >> 3;
- val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+ val = ((r & 0x1f) << 11) |
+ ((g & 0x3f) << 5) |
+ (b & 0x1f);
*ptr2++ = val;
}
} else if (bpp == 8) {
for (x = 0; x < line_size; x++) {
/* query rgb value from palette */
- ptr = (unsigned char *)(dst + 14 + 40) ;
+ ptr = (unsigned char *)(dst + 14 + 40);
ptr += (*bmp++) << 2;
b = *ptr++ >> 3;
g = *ptr++ >> 2;
r = *ptr++ >> 3;
- val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+ val = ((r & 0x1f) << 11) |
+ ((g & 0x3f) << 5) |
+ (b & 0x1f);
*ptr2++ = val;
}
}
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
free(dst);
+ return 0;
}
-void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
- uchar *logo_bmp, ulong len)
+int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+ uchar *logo_bmp, ulong len)
{
int i;
ushort s1dReg;
lcd_reg += 0x10000; /* add offset for 705 regs */
puts("LCD: S1D13705");
} else {
- puts("LCD: No controller detected!\n");
- return;
+ out_8(&lcd_reg[0x1a], 0x00);
+ udelay(1000);
+ if (in_8(&lcd_reg[1]) == 0x0c) {
+ /*
+ * S1D13505 detected
+ */
+ reg_byte_swap = TRUE;
+ palette_index = 0x25;
+ palette_value = 0x27;
+ lcd_depth = 16;
+
+ puts("LCD: S1D13505");
+ } else {
+ puts("LCD: No controller detected!\n");
+ return 1;
+ }
}
/*
s1dReg &= ~0x0001;
}
s1dValue = regs[i].Value;
- lcd_reg[s1dReg] = s1dValue;
+ out_8(&lcd_reg[s1dReg], s1dValue);
}
/*
/*
* Display bmp image
*/
- lcd_bmp(logo_bmp);
+ return lcd_bmp(logo_bmp);
}
-#if defined(CONFIG_VIDEO_SM501)
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
+#ifdef CONFIG_VIDEO_SM501
char *str;
-
+#endif
if (argc != 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
+#ifdef CONFIG_VIDEO_SM501
str = getenv("bd_type");
if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
/*
* SM501 available, use standard bmp command
*/
- return (video_display_bitmap(addr, 0, 0));
+ return video_display_bitmap(addr, 0, 0);
} else {
/*
* No SM501 available, use esd epson bmp command
*/
- lcd_bmp((uchar *)addr);
- return 0;
+ return lcd_bmp((uchar *)addr);
}
+#else
+ return lcd_bmp((uchar *)addr);
+#endif
}
U_BOOT_CMD(
"esdbmp - display BMP image\n",
"<imageAddr> - display image\n"
);
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
+ * Memory: DRAM (MCLK=40.000 MHz)
+ */
+static S1D_REGS regs_13505_640_480_16bpp[] =
+{
+ {0x1B,0x00}, /* Miscellaneous Register */
+ {0x23,0x20}, /* Performance Enhancement Register 1 */
+ {0x01,0x30}, /* Memory Configuration Register */
+ {0x22,0x24}, /* Performance Enhancement Register 0 */
+ {0x02,0x25}, /* Panel Type Register */
+ {0x03,0x00}, /* MOD Rate Register */
+ {0x04,0x4F}, /* Horizontal Display Width Register */
+ {0x05,0x0c}, /* Horizontal Non-Display Period Register */
+ {0x06,0x00}, /* HRTC/FPLINE Start Position Register */
+ {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
+ {0x08,0xDF}, /* Vertical Display Height Register 0 */
+ {0x09,0x01}, /* Vertical Display Height Register 1 */
+ {0x0A,0x3E}, /* Vertical Non-Display Period Register */
+ {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
+ {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
+ {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
+ {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
+ {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
+ {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
+ {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
+ {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
+ {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
+ {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
+ {0x16,0x80}, /* Memory Address Offset Register 0 */
+ {0x17,0x02}, /* Memory Address Offset Register 1 */
+ {0x18,0x00}, /* Pixel Panning Register */
+ {0x19,0x01}, /* Clock Configuration Register */
+ {0x1A,0x00}, /* Power Save Configuration Register */
+ {0x1C,0x00}, /* MD Configuration Readback Register 0 */
+ {0x1E,0x06}, /* General IO Pins Configuration Register 0 */
+ {0x1F,0x00}, /* General IO Pins Configuration Register 1 */
+ {0x20,0x00}, /* General IO Pins Control Register 0 */
+ {0x21,0x00}, /* General IO Pins Control Register 1 */
+ {0x23,0x20}, /* Performance Enhancement Register 1 */
+ {0x0D,0x15}, /* Display Mode Register */
+};
+
projects / u-boot / commitdiff