mx5 clocks: Fix get_lp_apm()

If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index fe0c0d3cb7d6c1287528f6db4365bd30c96bc639..8c71a51e8b0969d2c29729dc06342accbd2a8aa7 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -221,6 +221,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
        return ret;
 }
 
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+       u32 mult;
+       u32 ccr = readl(&mxc_ccm->ccr);
+
+       if (ccr & MXC_CCM_CCR_FPM_MULT)
+               mult = 1024;
+       else
+               mult = 512;
+
+       return MXC_CLK32 * mult;
+}
+#endif
+
 /*
  * Get mcu main rate
  */
@@ -326,7 +344,11 @@ static u32 get_lp_apm(void)
        u32 ccsr = readl(&mxc_ccm->ccsr);
 
        if (ccsr & MXC_CCM_CCSR_LP_APM)
-               ret_val = MXC_CLK32 * 1024;
+#if defined(CONFIG_MX51)
+               ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+               ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
        else
                ret_val = MXC_HCLK;
 

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 56dceb4d0cfeaa7e29744fa0e3fc5fa5f9d9524b..ddfab709b5f08b7c8838acfa6c91e2f55f6f4158 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,21 @@ struct mxc_ccm_reg {
        u32 cmeor;
 };
 
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN                    (0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT                   (0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN                   (0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN                   (0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN                     (0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET               0
+#define MXC_CCM_CCR_OSCNT_MASK                 0xFF
+#define MXC_CCM_CCR_OSCNT(v)                   ((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r)                        ((r) & 0xFF)
+
 /* Define the bits in register CCSR */
 #if defined(CONFIG_MX51)
 #define MXC_CCM_CCSR_LP_APM                    (0x1 << 9)