;
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
        u32 clkmode, clksel, div_m2;
 
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+       clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
        writel(clksel, &cmwkup->clkseldpllddr);
 
        div_m2 = div_m2 & CLK_DIV_SEL;
        mpu_pll_config();
        core_pll_config();
        per_pll_config();
-       ddr_pll_config();
 
        /* Enable the required interconnect clocks */
        enable_interface_clocks();
 
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 
        enable_emif_clocks();
 
        if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+               ddr_pll_config(266);
                config_vtp();
 
                config_cmd_ctrl(&ddr2_cmd_ctrl_data);