#define MT41J256M8HX15E_IOCTRL_VALUE           0x18B
 
 /* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY    0x100006
-#define MT41K256M16HA125E_EMIF_TIM1            0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2            0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3            0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG           0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF           0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY    0x100007
+#define MT41K256M16HA125E_EMIF_TIM1            0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2            0x26437FDA
+#define MT41K256M16HA125E_EMIF_TIM3            0x501F83FF
+#define MT41K256M16HA125E_EMIF_SDCFG           0x61C052B2
+#define MT41K256M16HA125E_EMIF_SDREF           0xC30
 #define MT41K256M16HA125E_ZQ_CFG               0x50074BE4
 #define MT41K256M16HA125E_DLL_LOCK_DIFF                0x1
-#define MT41K256M16HA125E_RATIO                        0x40
+#define MT41K256M16HA125E_RATIO                        0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT                0x0
-#define MT41K256M16HA125E_RD_DQS               0x3C
-#define MT41K256M16HA125E_WR_DQS               0x45
-#define MT41K256M16HA125E_PHY_WR_DATA          0x7F
+#define MT41K256M16HA125E_RD_DQS               0x3A
+#define MT41K256M16HA125E_WR_DQS               0x42
+#define MT41K256M16HA125E_PHY_WR_DATA          0x7E
 #define MT41K256M16HA125E_PHY_FIFO_WE          0x9B
 #define MT41K256M16HA125E_IOCTRL_VALUE         0x18B
 
 
                config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
                           &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
        else if (board_is_bone_lt())
-               config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
+               config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
                           &ddr3_beagleblack_data,
                           &ddr3_beagleblack_cmd_ctrl_data,
                           &ddr3_beagleblack_emif_reg_data, 0);