++commit 5f6c732affea9647762d27a4617a2ae64c52dceb
++Author: Wolfgang Denk <wd@denx.de>
++Date: Wed Apr 18 16:17:46 2007 +0200
++
++ Update CHANGELOG
++
+commit ad4eb555671d97f96dc56eab55103b1f86874b01
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Apr 18 14:30:39 2007 +0200
+
+ MCC200 board: remove warning which is obsolete after PSoC firmware changes
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3747a3f010b2b1442dec3e871c69788b6017aaae
+Author: Domen Puncer <domen.puncer@telargo.com>
+Date: Wed Apr 18 12:11:05 2007 +0200
+
+ [PATCH] icecube/lite5200b: document wakeup from low-power support
+
+ Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
+
+commit e673226ff9d6aa91b47ceac74b8c13770b06bb37
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Apr 18 12:07:47 2007 +0200
+
+ ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Apr 18 12:05:59 2007 +0200
+
+ ppc4xx: Add output for bootrom location to 405EZ ports
+
+ Now 405EZ ports also show upon bootup from which boot device
+ they are configured to boot:
+
+ U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)
+
+ CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
+ Bootstrap Option E - Boot ROM Location EBC (32 bits)
+ 16 kB I-Cache 16 kB D-Cache
+ Board: Acadia - AMCC PPC405EZ Evaluation Board
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d3832e8fe1b214ec62424eac36cfda9fc56d21b3
+Author: Domen Puncer <domen.puncer@telargo.com>
+Date: Mon Apr 16 14:00:13 2007 +0200
+
+ [PATCH] icecube/lite5200b: wakeup from low-power support
+
+ U-Boot part of Lite5200b low power mode support.
+ Puts SDRAM out of self-refresh and transfers control to
+ address saved at physical 0x0.
+
+ Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
+ Acked-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 8048cdd56f04a756eeea4951f402bf5cc33785db
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Apr 14 21:16:54 2007 +0200
+
+ Update CHANGELOG
+
+commit 37403005cfe6bb13964d450f6a48a0b0f2f7017e
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date: Sat Apr 14 05:26:48 2007 +0200
+
+ [Fix] Set the LED status register on the UC101 for the LXT971 PHY.
+ clear the Display after reset.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 7882751c78b7ecabfd49b0eff8de27661c71f16c
+Author: Denis Peter <d.peter@mpl.ch>
+Date: Fri Apr 13 09:13:33 2007 +0200
+
+ [PATCH] Fix bugs in cmd_ide.c and cmd_scsi.c
+
+ Fix bug introduced by "Fix get_partition_info() parameter error in all
+ other calls" from 2005-03-04 in cmd_ide.c and cmd_scsi.c, which prevented
+ to use diskboot or scsiboot form another device than 0.
+
+ Signed-off-by: Denis Peter <d.peter@mpl.ch>
+
+commit 0b94504d22e70f537c17a0d38c87edb6e370977d
+Author: Greg Lopp <lopp@pobox.com>
+Date: Fri Apr 13 08:02:24 2007 +0200
+
+ [PATCH] Fix use of "void *" for block dev read/write buffer pointers
+
+ Signed-of-by: Greg Lopp <lopp@pobox.com>
+ Acked-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13
+Author: Jeffrey Mann <mannj@embeddedplanet.com>
+Date: Thu Apr 12 14:15:59 2007 +0200
+
+ ppc4xx: Fix i2c divisor calcularion for PPC4xx
+
+ This patch fixes changes the i2c_init(...) function to use the function
+ get_OPB_freq() rather than calculating the OPB speed by
+ sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is
+ specific per processor. The prior method was not and so was calculating
+ the wrong speed for some PPC4xx processors.
+
+ Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6c9ba919375db977aaad9146bf320c7afd07ae7a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Apr 11 17:25:01 2007 +0200
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 51056dd9863e6a1bc363afbbe1775c58cd967418
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Apr 11 17:22:55 2007 +0200
--- /dev/null
- // pr_debug("%x\n", data);
+ /*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+ #include <common.h>
+
+ #ifdef CONFIG_MMC
+
+ #include <part.h>
+ #include <mmc.h>
+
+ #include <asm/io.h>
+ #include <asm/errno.h>
+ #include <asm/byteorder.h>
+ #include <asm/arch/clk.h>
+ #include <asm/arch/memory-map.h>
+
+ #include "atmel_mci.h"
+
+ #ifdef DEBUG
+ #define pr_debug(fmt, args...) printf(fmt, ##args)
+ #else
+ #define pr_debug(...) do { } while(0)
+ #endif
+
+ #ifndef CFG_MMC_CLK_OD
+ #define CFG_MMC_CLK_OD 150000
+ #endif
+
+ #ifndef CFG_MMC_CLK_PP
+ #define CFG_MMC_CLK_PP 5000000
+ #endif
+
+ #ifndef CFG_MMC_OP_COND
+ #define CFG_MMC_OP_COND 0x00100000
+ #endif
+
+ #define MMC_DEFAULT_BLKLEN 512
+ #define MMC_DEFAULT_RCA 1
+
+ static unsigned int mmc_rca;
+ static block_dev_desc_t mmc_blkdev;
+
+ block_dev_desc_t *mmc_get_dev(int dev)
+ {
+ return &mmc_blkdev;
+ }
+
+ static void mci_set_mode(unsigned long hz, unsigned long blklen)
+ {
+ unsigned long bus_hz;
+ unsigned long clkdiv;
+
+ bus_hz = get_mci_clk_rate();
+ clkdiv = (bus_hz / hz) / 2 - 1;
+
+ pr_debug("mmc: setting clock %lu Hz, block size %lu\n",
+ hz, blklen);
+
+ if (clkdiv & ~255UL) {
+ clkdiv = 255;
+ printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
+ hz);
+ }
+
+ blklen &= 0xfffc;
+ mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
+ | MMCI_BF(BLKLEN, blklen)));
+ }
+
+ #define RESP_NO_CRC 1
+ #define R1 MMCI_BF(RSPTYP, 1)
+ #define R2 MMCI_BF(RSPTYP, 2)
+ #define R3 (R1 | RESP_NO_CRC)
+ #define R6 R1
+ #define NID MMCI_BF(MAXLAT, 0)
+ #define NCR MMCI_BF(MAXLAT, 1)
+ #define TRCMD_START MMCI_BF(TRCMD, 1)
+ #define TRDIR_READ MMCI_BF(TRDIR, 1)
+ #define TRTYP_BLOCK MMCI_BF(TRTYP, 0)
+ #define INIT_CMD MMCI_BF(SPCMD, 1)
+ #define OPEN_DRAIN MMCI_BF(OPDCMD, 1)
+
+ #define ERROR_FLAGS (MMCI_BIT(DTOE) \
+ | MMCI_BIT(RDIRE) \
+ | MMCI_BIT(RENDE) \
+ | MMCI_BIT(RINDE) \
+ | MMCI_BIT(RTOE))
+
+ static int
+ mmc_cmd(unsigned long cmd, unsigned long arg,
+ void *resp, unsigned long flags)
+ {
+ unsigned long *response = resp;
+ int i, response_words = 0;
+ unsigned long error_flags;
+ u32 status;
+
+ pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n",
+ cmd, arg, flags);
+
+ error_flags = ERROR_FLAGS;
+ if (!(flags & RESP_NO_CRC))
+ error_flags |= MMCI_BIT(RCRCE);
+
+ flags &= ~MMCI_BF(CMDNB, ~0UL);
+
+ if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
+ response_words = 1;
+ else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
+ response_words = 4;
+
+ mmci_writel(ARGR, arg);
+ mmci_writel(CMDR, cmd | flags);
+ do {
+ udelay(40);
+ status = mmci_readl(SR);
+ } while (!(status & MMCI_BIT(CMDRDY)));
+
+ pr_debug("mmc: status 0x%08lx\n", status);
+
+ if (status & ERROR_FLAGS) {
+ printf("mmc: command %lu failed (status: 0x%08lx)\n",
+ cmd, status);
+ return -EIO;
+ }
+
+ if (response_words)
+ pr_debug("mmc: response:");
+
+ for (i = 0; i < response_words; i++) {
+ response[i] = mmci_readl(RSPR);
+ pr_debug(" %08lx", response[i]);
+ }
+ pr_debug("\n");
+
+ return 0;
+ }
+
+ static int mmc_acmd(unsigned long cmd, unsigned long arg,
+ void *resp, unsigned long flags)
+ {
+ unsigned long aresp[4];
+ int ret;
+
+ /*
+ * Seems like the APP_CMD part of an ACMD has 64 cycles max
+ * latency even though the ACMD part doesn't. This isn't
+ * entirely clear in the SD Card spec, but some cards refuse
+ * to work if we attempt to use 5 cycles max latency here...
+ */
+ ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
+ R1 | NCR | (flags & OPEN_DRAIN));
+ if (ret)
+ return ret;
+ if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
+ return -ENODEV;
+
+ ret = mmc_cmd(cmd, arg, resp, flags);
+ return ret;
+ }
+
+ static unsigned long
+ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+ unsigned long *buffer)
+ {
+ int ret, i = 0;
+ unsigned long resp[4];
+ unsigned long card_status, data;
+ unsigned long wordcount;
+ u32 status;
+
+ if (blkcnt == 0)
+ return 0;
+
+ pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n",
+ dev, start, blkcnt);
+
+ /* Put the device into Transfer state */
+ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
+ if (ret) goto fail;
+
+ /* Set block length */
+ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
+ if (ret) goto fail;
+
+ pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
+
+ for (i = 0; i < blkcnt; i++, start++) {
+ ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
+ start * mmc_blkdev.blksz, resp,
+ (R1 | NCR | TRCMD_START | TRDIR_READ
+ | TRTYP_BLOCK));
+ if (ret) goto fail;
+
+ ret = -EIO;
+ wordcount = 0;
+ do {
+ do {
+ status = mmci_readl(SR);
+ if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
+ goto fail;
+ } while (!(status & MMCI_BIT(RXRDY)));
+
+ if (status & MMCI_BIT(RXRDY)) {
+ data = mmci_readl(RDR);
++ /* pr_debug("%x\n", data); */
+ *buffer++ = data;
+ wordcount++;
+ }
+ } while(wordcount < (512 / 4));
+
+ pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount);
+
+ do {
+ status = mmci_readl(SR);
+ } while (!(status & MMCI_BIT(BLKE)));
+
+ putc('.');
+ }
+
+ out:
+ /* Put the device back into Standby state */
+ mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
+ return i;
+
+ fail:
+ mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
+ printf("mmc: bread failed, card status = ", card_status);
+ goto out;
+ }
+
+ static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+ {
+ cid->mid = resp[0] >> 24;
+ cid->oid = (resp[0] >> 8) & 0xffff;
+ cid->pnm[0] = resp[0];
+ cid->pnm[1] = resp[1] >> 24;
+ cid->pnm[2] = resp[1] >> 16;
+ cid->pnm[3] = resp[1] >> 8;
+ cid->pnm[4] = resp[1];
+ cid->pnm[5] = resp[2] >> 24;
+ cid->pnm[6] = 0;
+ cid->prv = resp[2] >> 16;
+ cid->psn = (resp[2] << 16) | (resp[3] >> 16);
+ cid->mdt = resp[3] >> 8;
+ }
+
+ static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+ {
+ cid->mid = resp[0] >> 24;
+ cid->oid = (resp[0] >> 8) & 0xffff;
+ cid->pnm[0] = resp[0];
+ cid->pnm[1] = resp[1] >> 24;
+ cid->pnm[2] = resp[1] >> 16;
+ cid->pnm[3] = resp[1] >> 8;
+ cid->pnm[4] = resp[1];
+ cid->pnm[5] = 0;
+ cid->pnm[6] = 0;
+ cid->prv = resp[2] >> 24;
+ cid->psn = (resp[2] << 8) | (resp[3] >> 24);
+ cid->mdt = (resp[3] >> 8) & 0x0fff;
+ }
+
+ static void mmc_dump_cid(const struct mmc_cid *cid)
+ {
+ printf("Manufacturer ID: %02lX\n", cid->mid);
+ printf("OEM/Application ID: %04lX\n", cid->oid);
+ printf("Product name: %s\n", cid->pnm);
+ printf("Product Revision: %lu.%lu\n",
+ cid->prv >> 4, cid->prv & 0x0f);
+ printf("Product Serial Number: %lu\n", cid->psn);
+ printf("Manufacturing Date: %02lu/%02lu\n",
+ cid->mdt >> 4, cid->mdt & 0x0f);
+ }
+
+ static void mmc_dump_csd(const struct mmc_csd *csd)
+ {
+ unsigned long *csd_raw = (unsigned long *)csd;
+ printf("CSD data: %08lx %08lx %08lx %08lx\n",
+ csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]);
+ printf("CSD structure version: 1.%u\n", csd->csd_structure);
+ printf("MMC System Spec version: %u\n", csd->spec_vers);
+ printf("Card command classes: %03x\n", csd->ccc);
+ printf("Read block length: %u\n", 1 << csd->read_bl_len);
+ if (csd->read_bl_partial)
+ puts("Supports partial reads\n");
+ else
+ puts("Does not support partial reads\n");
+ printf("Write block length: %u\n", 1 << csd->write_bl_len);
+ if (csd->write_bl_partial)
+ puts("Supports partial writes\n");
+ else
+ puts("Does not support partial writes\n");
+ if (csd->wp_grp_enable)
+ printf("Supports group WP: %u\n", csd->wp_grp_size + 1);
+ else
+ puts("Does not support group WP\n");
+ printf("Card capacity: %u bytes\n",
+ (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) *
+ (1 << csd->read_bl_len));
+ printf("File format: %u/%u\n",
+ csd->file_format_grp, csd->file_format);
+ puts("Write protection: ");
+ if (csd->perm_write_protect)
+ puts(" permanent");
+ if (csd->tmp_write_protect)
+ puts(" temporary");
+ putc('\n');
+ }
+
+ static int mmc_idle_cards(void)
+ {
+ int ret;
+
+ /* Reset and initialize all cards */
+ ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
+ if (ret)
+ return ret;
+
+ /* Keep the bus idle for 74 clock cycles */
+ return mmc_cmd(0, 0, NULL, INIT_CMD);
+ }
+
+ static int sd_init_card(struct mmc_cid *cid, int verbose)
+ {
+ unsigned long resp[4];
+ int i, ret = 0;
+
+ mmc_idle_cards();
+ for (i = 0; i < 1000; i++) {
+ ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND,
+ resp, R3 | NID);
+ if (ret || (resp[0] & 0x80000000))
+ break;
+ ret = -ETIMEDOUT;
+ }
+
+ if (ret)
+ return ret;
+
+ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
+ if (ret)
+ return ret;
+ sd_parse_cid(cid, resp);
+ if (verbose)
+ mmc_dump_cid(cid);
+
+ /* Get RCA of the card that responded */
+ ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
+ if (ret)
+ return ret;
+
+ mmc_rca = resp[0] >> 16;
+ if (verbose)
+ printf("SD Card detected (RCA %u)\n", mmc_rca);
+ return 0;
+ }
+
+ static int mmc_init_card(struct mmc_cid *cid, int verbose)
+ {
+ unsigned long resp[4];
+ int i, ret = 0;
+
+ mmc_idle_cards();
+ for (i = 0; i < 1000; i++) {
+ ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
+ R3 | NID | OPEN_DRAIN);
+ if (ret || (resp[0] & 0x80000000))
+ break;
+ ret = -ETIMEDOUT;
+ }
+
+ if (ret)
+ return ret;
+
+ /* Get CID of all cards. FIXME: Support more than one card */
+ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
+ if (ret)
+ return ret;
+ mmc_parse_cid(cid, resp);
+ if (verbose)
+ mmc_dump_cid(cid);
+
+ /* Set Relative Address of the card that responded */
+ ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
+ R1 | NCR | OPEN_DRAIN);
+ return ret;
+ }
+
+ int mmc_init(int verbose)
+ {
+ struct mmc_cid cid;
+ struct mmc_csd csd;
+ int ret;
+
+ /* Initialize controller */
+ mmci_writel(CR, MMCI_BIT(SWRST));
+ mmci_writel(CR, MMCI_BIT(MCIEN));
+ mmci_writel(DTOR, 0x5f);
+ mmci_writel(IDR, ~0UL);
+ mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+
+ ret = sd_init_card(&cid, verbose);
+ if (ret) {
+ mmc_rca = MMC_DEFAULT_RCA;
+ ret = mmc_init_card(&cid, verbose);
+ }
+ if (ret)
+ return ret;
+
+ /* Get CSD from the card */
+ ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR);
+ if (ret)
+ return ret;
+ if (verbose)
+ mmc_dump_csd(&csd);
+
+ /* Initialize the blockdev structure */
+ mmc_blkdev.if_type = IF_TYPE_MMC;
+ mmc_blkdev.part_type = PART_TYPE_DOS;
+ mmc_blkdev.block_read = mmc_bread;
+ sprintf((char *)mmc_blkdev.vendor,
+ "Man %02x%04x Snr %08x",
+ cid.mid, cid.oid, cid.psn);
+ strncpy((char *)mmc_blkdev.product, cid.pnm,
+ sizeof(mmc_blkdev.product));
+ sprintf((char *)mmc_blkdev.revision, "%x %x",
+ cid.prv >> 4, cid.prv & 0x0f);
+ mmc_blkdev.blksz = 1 << csd.read_bl_len;
+ mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2));
+
+ mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
+
+ #if 0
+ if (fat_register_device(&mmc_blkdev, 1))
+ printf("Could not register MMC fat device\n");
+ #else
+ init_part(&mmc_blkdev);
+ #endif
+
+ return 0;
+ }
+
+ int mmc_read(ulong src, uchar *dst, int size)
+ {
+ return -ENOSYS;
+ }
+
+ int mmc_write(uchar *src, ulong dst, int size)
+ {
+ return -ENOSYS;
+ }
+
+ int mmc2info(ulong addr)
+ {
+ return 0;
+ }
+
+ #endif /* CONFIG_MMC */
--- /dev/null
-
+ /*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+ #ifndef __ASM_AVR32_ARCH_GPIO_H__
+ #define __ASM_AVR32_ARCH_GPIO_H__
+
+ #include <asm/arch/memory-map.h>
+
+ #define NR_GPIO_CONTROLLERS 5
+
+ /*
+ * Pin numbers identifying specific GPIO pins on the chip.
+ */
+ #define GPIO_PIOA_BASE (0)
+ #define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
+ #define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
+ #define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
+ #define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
+ #define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
+ #define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
+ #define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
+ #define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
+ #define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
+ #define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
+ #define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
+ #define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
+ #define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
+ #define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
+ #define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
+ #define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
+ #define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
+ #define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
+ #define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
+ #define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
+ #define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
+ #define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
+ #define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
+ #define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
+ #define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
+ #define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
+ #define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
+ #define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
+ #define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
+ #define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
+ #define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
+ #define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
+
+ #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
+ #define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
+ #define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
+ #define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
+ #define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
+ #define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
+ #define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
+ #define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
+ #define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
+ #define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
+ #define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
+ #define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
+ #define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
+ #define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
+ #define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
+ #define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
+ #define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
+ #define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
+ #define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
+ #define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
+ #define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
+ #define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
+ #define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
+ #define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
+ #define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
+ #define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
+ #define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
+ #define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
+ #define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
+ #define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
+ #define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
+ #define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
+
+ #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
+ #define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
+ #define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
+ #define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
+ #define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
+ #define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
+ #define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
+ #define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
+ #define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
+ #define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
+ #define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
+ #define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
+ #define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
+ #define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
+ #define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
+ #define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
+ #define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
+ #define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
+ #define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
+ #define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
+ #define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
+ #define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
+ #define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
+ #define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
+ #define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
+ #define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
+ #define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
+ #define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
+ #define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
+ #define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
+ #define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
+ #define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
+ #define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
+
+ #define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+ #define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
+ #define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
+ #define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
+ #define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
+ #define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
+ #define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
+ #define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
+ #define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
+ #define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
+ #define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
+ #define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
+ #define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
+ #define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
+ #define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
+ #define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
+ #define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
+ #define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
+ #define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
+
+ #define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
+ #define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
+ #define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
+ #define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
+ #define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
+ #define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
+ #define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
+ #define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
+ #define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
+ #define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
+ #define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
+ #define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
+ #define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
+ #define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
+ #define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
+ #define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
+ #define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
+ #define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
+ #define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
+ #define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
+ #define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
+ #define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
+ #define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
+ #define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
+ #define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
+ #define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
+ #define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
+ #define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+
+ static inline void *gpio_pin_to_addr(unsigned int pin)
+ {
+ switch (pin >> 5) {
+ case 0:
+ return (void *)PIOA_BASE;
+ case 1:
+ return (void *)PIOB_BASE;
+ case 2:
+ return (void *)PIOC_BASE;
+ case 3:
+ return (void *)PIOD_BASE;
+ case 4:
+ return (void *)PIOE_BASE;
+ default:
+ return NULL;
+ }
+ }
+
+ void gpio_select_periph_A(unsigned int pin, int use_pullup);
+ void gpio_select_periph_B(unsigned int pin, int use_pullup);
+
+ void gpio_enable_ebi(void);
+ void gpio_enable_usart0(void);
+ void gpio_enable_usart1(void);
+ void gpio_enable_usart2(void);
+ void gpio_enable_usart3(void);
+ void gpio_enable_macb0(void);
+ void gpio_enable_macb1(void);
+ void gpio_enable_mmci(void);
+
+ #endif /* __ASM_AVR32_ARCH_GPIO_H__ */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
+
+ #define CONFIG_BOOTCOMMAND \
+ "fsload; bootm $(fileaddr)"
+
+ /*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+ #define CONFIG_BOOTDELAY 2
+ #define CONFIG_AUTOBOOT 1
+ #define CONFIG_AUTOBOOT_KEYED 1
+ #define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n"
++ "Press SPACE to abort autoboot in %d seconds\n"
+ #define CONFIG_AUTOBOOT_DELAY_STR "d"
+ #define CONFIG_AUTOBOOT_STOP_STR " "
+
+ /*
+ * These are "locally administered ethernet addresses" generated by
+ * ./tools/gen_eth_addr
+ *
+ * After booting the board for the first time, new addresses should be
+ * generated and assigned to the environment variables "ethaddr" and
+ * "eth1addr".
+ */
+ #define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
+ #define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+ #define CONFIG_NET_MULTI 1
+
+ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \
+ | CONFIG_BOOTP_GATEWAY)
#define CONFIG_COMMANDS (CFG_CMD_BDI \
| CFG_CMD_LOADS \
--- /dev/null
-#define MII_BMCR 0x00 /* Basic mode control register */
-#define MII_BMSR 0x01 /* Basic mode status register */
-#define MII_PHYSID1 0x02 /* PHYS ID 1 */
-#define MII_PHYSID2 0x03 /* PHYS ID 2 */
-#define MII_ADVERTISE 0x04 /* Advertisement control reg */
-#define MII_LPA 0x05 /* Link partner ability reg */
-#define MII_EXPANSION 0x06 /* Expansion register */
-#define MII_DCOUNTER 0x12 /* Disconnect counter */
-#define MII_FCSCOUNTER 0x13 /* False carrier counter */
-#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
-#define MII_RERRCOUNTER 0x15 /* Receive error counter */
-#define MII_SREVISION 0x16 /* Silicon revision */
-#define MII_RESV1 0x17 /* Reserved... */
-#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
-#define MII_PHYADDR 0x19 /* PHY address */
-#define MII_RESV2 0x1a /* Reserved... */
-#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
-#define MII_NCONFIG 0x1c /* Network interface config */
+ /*
+ * linux/mii.h: definitions for MII-compatible transceivers
+ * Originally drivers/net/sunhme.h.
+ *
+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
+ */
+
+ #ifndef __LINUX_MII_H__
+ #define __LINUX_MII_H__
+
+ /* Generic MII registers. */
+
-#define BMCR_RESV 0x003f /* Unused... */
-#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
-#define BMCR_CTST 0x0080 /* Collision test */
-#define BMCR_FULLDPLX 0x0100 /* Full duplex */
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
-#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
-#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
-#define BMCR_RESET 0x8000 /* Reset the DP83840 */
++#define MII_BMCR 0x00 /* Basic mode control register */
++#define MII_BMSR 0x01 /* Basic mode status register */
++#define MII_PHYSID1 0x02 /* PHYS ID 1 */
++#define MII_PHYSID2 0x03 /* PHYS ID 2 */
++#define MII_ADVERTISE 0x04 /* Advertisement control reg */
++#define MII_LPA 0x05 /* Link partner ability reg */
++#define MII_EXPANSION 0x06 /* Expansion register */
++#define MII_DCOUNTER 0x12 /* Disconnect counter */
++#define MII_FCSCOUNTER 0x13 /* False carrier counter */
++#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
++#define MII_RERRCOUNTER 0x15 /* Receive error counter */
++#define MII_SREVISION 0x16 /* Silicon revision */
++#define MII_RESV1 0x17 /* Reserved... */
++#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
++#define MII_PHYADDR 0x19 /* PHY address */
++#define MII_RESV2 0x1a /* Reserved... */
++#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
++#define MII_NCONFIG 0x1c /* Network interface config */
+
+ /* Basic mode control register. */
-#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
-#define BMSR_JCD 0x0002 /* Jabber detected */
-#define BMSR_LSTATUS 0x0004 /* Link status */
-#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
-#define BMSR_RFAULT 0x0010 /* Remote fault detected */
-#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
-#define BMSR_RESV 0x07c0 /* Unused... */
-#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
-#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
-#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
++#define BMCR_RESV 0x003f /* Unused... */
++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
++#define BMCR_CTST 0x0080 /* Collision test */
++#define BMCR_FULLDPLX 0x0100 /* Full duplex */
++#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
++#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
++#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
++#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
++#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
++#define BMCR_RESET 0x8000 /* Reset the DP83840 */
+
+ /* Basic mode status register. */
-#define ADVERTISE_SLCT 0x001f /* Selector bits */
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
-#define ADVERTISE_RESV 0x1c00 /* Unused... */
-#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
-#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
-#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
++#define BMSR_JCD 0x0002 /* Jabber detected */
++#define BMSR_LSTATUS 0x0004 /* Link status */
++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
++#define BMSR_RFAULT 0x0010 /* Remote fault detected */
++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
++#define BMSR_RESV 0x07c0 /* Unused... */
++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
++#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
+
+ /* Advertisement control register. */
- ADVERTISE_100HALF | ADVERTISE_100FULL)
++#define ADVERTISE_SLCT 0x001f /* Selector bits */
++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
++#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
++#define ADVERTISE_RESV 0x1c00 /* Unused... */
++#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
++#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
++#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
+
+ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+ ADVERTISE_CSMA)
+ #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-#define LPA_SLCT 0x001f /* Same as advertise selector */
-#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
-#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
-#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
-#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
-#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
-#define LPA_RESV 0x1c00 /* Unused... */
-#define LPA_RFAULT 0x2000 /* Link partner faulted */
-#define LPA_LPACK 0x4000 /* Link partner acked us */
-#define LPA_NPAGE 0x8000 /* Next page bit */
++ ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+ /* Link partner ability register. */
-#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
-#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
-#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
-#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
-#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
-#define EXPANSION_RESV 0xffe0 /* Unused... */
++#define LPA_SLCT 0x001f /* Same as advertise selector */
++#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
++#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
++#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
++#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
++#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
++#define LPA_RESV 0x1c00 /* Unused... */
++#define LPA_RFAULT 0x2000 /* Link partner faulted */
++#define LPA_LPACK 0x4000 /* Link partner acked us */
++#define LPA_NPAGE 0x8000 /* Next page bit */
+
+ #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
+ #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+ /* Expansion register for auto-negotiation. */
-#define NWAYTEST_RESV1 0x00ff /* Unused... */
-#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
-#define NWAYTEST_RESV2 0xfe00 /* Unused... */
++#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
++#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
++#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
++#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
++#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
++#define EXPANSION_RESV 0xffe0 /* Unused... */
+
+ /* N-way test register. */
- * 100T4 this is fine. If your phy places 100T4 elsewhere in the
++#define NWAYTEST_RESV1 0x00ff /* Unused... */
++#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
++#define NWAYTEST_RESV2 0xfe00 /* Unused... */
+
+
+ /**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u. We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half. If your phy does not support
++ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+ static inline unsigned int mii_nway_result (unsigned int negotiated)
+ {
+ unsigned int ret;
+
+ if (negotiated & LPA_100FULL)
+ ret = LPA_100FULL;
+ else if (negotiated & LPA_100BASE4)
+ ret = LPA_100BASE4;
+ else if (negotiated & LPA_100HALF)
+ ret = LPA_100HALF;
+ else if (negotiated & LPA_10FULL)
+ ret = LPA_10FULL;
+ else
+ ret = LPA_10HALF;
+
+ return ret;
+ }
+
+ /**
+ * mii_duplex
+ * @duplex_lock: Non-zero if duplex is locked at full
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * A small helper function for a common case. Returns one
+ * if the media is operating or locked at full duplex, and
+ * returns zero otherwise.
+ */
+ static inline unsigned int mii_duplex (unsigned int duplex_lock,
+ unsigned int negotiated)
+ {
+ if (duplex_lock)
+ return 1;
+ if (mii_nway_result(negotiated) & LPA_DUPLEX)
+ return 1;
+ return 0;
+ }
+
+
+ #endif /* __LINUX_MII_H__ */
extern "C" {
#endif
--#define S_IFMT 00170000 /* type of file */
++#define S_IFMT 00170000 /* type of file */
#define S_IFSOCK 0140000 /* named socket */
#define S_IFLNK 0120000 /* symbolic link */
#define S_IFREG 0100000 /* regular */
ino_t st_ino; /* file id */
mode_t st_mode; /* ownership/protection */
nlink_t st_nlink; /* number of links */
-- uid_t st_uid; /* user id */
-- gid_t st_gid; /* group id */
++ uid_t st_uid; /* user id */
++ gid_t st_gid; /* group id */
dev_t st_rdev;
off_t st_size; /* file size in # of bytes */
-- unsigned long st_blksize; /* block size */
-- unsigned long st_blocks; /* file size in # of blocks */
-- unsigned long st_atime; /* time file was last accessed */
-- unsigned long __unused1;
-- unsigned long st_mtime; /* time file was last modified */
-- unsigned long __unused2;
-- unsigned long st_ctime; /* time file status was last changed */
-- unsigned long __unused3;
-- unsigned long __unused4;
-- unsigned long __unused5;
++ unsigned long st_blksize; /* block size */
++ unsigned long st_blocks; /* file size in # of blocks */
++ unsigned long st_atime; /* time file was last accessed */
++ unsigned long __unused1;
++ unsigned long st_mtime; /* time file was last modified */
++ unsigned long __unused2;
++ unsigned long st_ctime; /* time file status was last changed */
++ unsigned long __unused3;
++ unsigned long __unused4;
++ unsigned long __unused5;
};
#endif /* __PPC__ */
#if defined (__MIPS__)
struct stat {
-- dev_t st_dev;
-- long st_pad1[3];
-- ino_t st_ino;
-- mode_t st_mode;
-- nlink_t st_nlink;
-- uid_t st_uid;
-- gid_t st_gid;
-- dev_t st_rdev;
-- long st_pad2[2];
-- off_t st_size;
-- long st_pad3;
++ dev_t st_dev;
++ long st_pad1[3];
++ ino_t st_ino;
++ mode_t st_mode;
++ nlink_t st_nlink;
++ uid_t st_uid;
++ gid_t st_gid;
++ dev_t st_rdev;
++ long st_pad2[2];
++ off_t st_size;
++ long st_pad3;
/*
* Actually this should be timestruc_t st_atime, st_mtime and st_ctime
* but we don't have it under Linux.
*/
-- time_t st_atime;
-- long reserved0;
-- time_t st_mtime;
-- long reserved1;
-- time_t st_ctime;
-- long reserved2;
-- long st_blksize;
-- long st_blocks;
-- long st_pad4[14];
++ time_t st_atime;
++ long reserved0;
++ time_t st_mtime;
++ long reserved1;
++ time_t st_ctime;
++ long reserved2;
++ long st_blksize;
++ long st_blocks;
++ long st_pad4[14];
};
#endif /* __MIPS__ */
- unsigned long st_dev;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned long st_rdev;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
+ #if defined(__AVR32__)
+
+ struct stat {
++ unsigned long st_dev;
++ unsigned long st_ino;
++ unsigned short st_mode;
++ unsigned short st_nlink;
++ unsigned short st_uid;
++ unsigned short st_gid;
++ unsigned long st_rdev;
++ unsigned long st_size;
++ unsigned long st_blksize;
++ unsigned long st_blocks;
++ unsigned long st_atime;
++ unsigned long st_atime_nsec;
++ unsigned long st_mtime;
++ unsigned long st_mtime_nsec;
++ unsigned long st_ctime;
++ unsigned long st_ctime_nsec;
++ unsigned long __unused4;
++ unsigned long __unused5;
+ };
+
+ #endif /* __AVR32__ */
+
#ifdef __cplusplus
}
#endif
extern int tsec_initialize(bd_t*, int, char *);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
+extern int bfin_EMAC_initialize(bd_t *);
+ extern int atstk1000_eth_initialize(bd_t *);
static struct eth_device *eth_devices, *eth_current;
#if defined(CONFIG_RTL8169)
rtl8169_initialize(bis);
#endif
+#if defined(CONFIG_BF537)
+ bfin_EMAC_initialize(bis);
+#endif
+ #if defined(CONFIG_ATSTK1000)
+ atstk1000_eth_initialize(bis);
+ #endif
if (!eth_devices) {
puts ("No ethernet found.\n");
projects / u-boot / commitdiff