]> git.sur5r.net Git - u-boot/commitdiff
Documentation: gpio: fix bindings document
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Thu, 12 Feb 2015 09:49:33 +0000 (18:49 +0900)
committerSimon Glass <sjg@chromium.org>
Thu, 19 Feb 2015 13:19:19 +0000 (06:19 -0700)
[ imported from Linux Kernel, commit 74981fb81d83 ]
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
doc/device-tree-bindings/gpio/gpio.txt

index b9bd1d64cfa696c216d8891502bab2263b5319bd..f7a158d858620f73133aded14765f042742a3fb4 100644 (file)
@@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
 ----------------------------------
 
 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
-high or active-low. If it does, the follow best practices should be followed:
+high or active-low. If it does, the following best practices should be
+followed:
 
 The gpio-specifier's polarity flag should represent the physical level at the
 GPIO controller that achieves (or represents, for inputs) a logically asserted
@@ -147,7 +148,7 @@ contains information structures as follows:
        numeric-gpio-range ::=
                        <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
        named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
-       gpio-phandle : phandle to pin controller node.
+       pinctrl-phandle : phandle to pin controller node
        gpio-base : Base GPIO ID in the GPIO controller
        pinctrl-base : Base pinctrl pin ID in the pin controller
        count : The number of GPIOs/pins in this range