]> git.sur5r.net Git - u-boot/commitdiff
arm: omap5: don't enable misc_init_r by default
authorFelipe Balbi <balbi@ti.com>
Thu, 6 Nov 2014 14:28:42 +0000 (08:28 -0600)
committerTom Rini <trini@ti.com>
Thu, 4 Dec 2014 16:04:12 +0000 (11:04 -0500)
Out of all OMAP5-like boards, only one of them
needs CONFIG_MISC_INIT_R, so it's best to enable
that for that particular board only, instead of
enabling for all boards unconditionally.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
board/ti/dra7xx/evm.c
include/configs/cm_t54.h
include/configs/omap5_uevm.h
include/configs/ti_omap5_common.h

index 37df7b2cadf55790f0c9a5101bc297e89677a01b..65222419ebbdb9b0e3a2c120fa27b56a9138a779 100644 (file)
@@ -96,18 +96,6 @@ int board_late_init(void)
        return 0;
 }
 
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
-       return 0;
-}
-
 static void do_set_mux32(u32 base,
                         struct pad_conf_entry const *array, int size)
 {
index 641ab48c2c81d5fd7203905d18c6efec619d05d5..92ce1e17dac6821f31e4ea93d235aa03cb600fb3 100644 (file)
@@ -16,7 +16,6 @@
 
 #include <configs/ti_omap5_common.h>
 
-#undef CONFIG_MISC_INIT_R
 #undef CONFIG_SPL_OS_BOOT
 
 /* Enable Generic board */
index e8dc462f146653fcf5acfbb8013e76caed83786e..e07795f9210c627ff2480854d69282ca67550581 100644 (file)
@@ -23,6 +23,7 @@
 #define CONFIG_SYS_NS16550_COM3                UART3_BASE
 #define CONFIG_BAUDRATE                        115200
 
+#define CONFIG_MISC_INIT_R
 /* MMC ENV related defines */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV         1       /* SLOT2: eMMC(1) */
index 3166392c780e7423df87e048c479c83dbe42b918..5b03fb182e6bf94d5cec41a00e37819b212e5150 100644 (file)
@@ -19,7 +19,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_R
 #define CONFIG_ARCH_CPU_INIT
 
 #define CONFIG_SYS_CACHELINE_SIZE      64