the second reset prevents other registers to be written.
This will prevent to have the correct signal levels for
SCLK before writing to the config reg in spi_xchg_single.
Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
        reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
                MXC_CSPICTRL_POSTDIV(post_div);
 
-       /* We need to disable SPI before changing registers */
-       reg_ctrl &= ~MXC_CSPICTRL_EN;
-
        if (mode & SPI_CS_HIGH)
                ss_pol = 1;