#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
#define DRA722_ES2_0 0x07220200
+#define DRA722_ES2_1 0x07220210
/*
* silicon device type
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*ctrl = &dra7xx_ctrl;
*regs = &ioregs_dra72x_es1;
break;
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*regs = &ioregs_dra72x_es2;
break;
case DRA722_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA722_ES2_0;
break;
+ case DRA722_CONTROL_ID_CODE_ES2_1:
+ *omap_si_rev = DRA722_ES2_1;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
break;
case DRA762_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
break;
case DRA752_ES2_0:
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
default:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2;
switch (omap_revision()) {
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
if (board_is_dra71x_evm()) {