{
char *id_str =
NULL;
- volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
return -1;
k = (immr << 16) |
- immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
+ in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
m = 0;
suf = "";
/* do we have a FEC (860T/P or 852/859/866/885)? */
- immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
- if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
+ out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
+ if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
printf (" FEC present");
- }
if (!m) {
puts (cpu_warning);
int checkicache (void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
-
- u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+ /* probe in flash memoryarea */
+ u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
int checkdcache (void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
-
- u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+ /* probe in flash memoryarea */
+ u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
{
uint i;
uint addr = 0;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
for (i = 0; i < size; i++) {
- memctl->memc_mdr = table[i]; /* (16-15) */
- memctl->memc_mcr = addr | upm; /* (16-16) */
+ out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
+ out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
addr++;
}
}
{
ulong msr, addr;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
- immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
+ /* Checkstop Reset enable */
+ setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
unsigned long get_tbclk (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
- volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;
- if (immap->im_clkrst.car_sccr & SCCR_TBS) {
+ if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
return (gd->cpu_clk / 16);
- }
- pll = immap->im_clkrst.car_plprcr;
+ pll = in_be32(&immap->im_clkrst.car_plprcr);
#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
oscclk = gd->cpu_clk / factor;
- if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
+ if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
+ factor > 2)
return (oscclk / 4);
- }
+
return (oscclk / 16);
}
{
int re_enable = disable_interrupts ();
- reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
+ reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
#if defined(CONFIG_WATCHDOG)
-void reset_8xx_watchdog (volatile immap_t * immr)
+void reset_8xx_watchdog(immap_t __iomem *immr)
{
/*
* All other boards use the MPC8xx Internal Watchdog
*/
- immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
- immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
+ out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
+ out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
}
#endif /* CONFIG_WATCHDOG */
#include <mpc8xx.h>
#include <commproc.h>
+#include <asm/io.h>
/*
* Breath some life into the CPU...
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (volatile immap_t * immr)
+void cpu_init_f(immap_t __iomem *immr)
{
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-# ifdef CONFIG_SYS_PLPRCR
- ulong mfmask;
-# endif
+ memctl8xx_t __iomem *memctl = &immr->im_memctl;
ulong reg;
/* SYPCR - contains watchdog control (11-9) */
- immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
+ out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
#endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */
- immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
+ setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
/* initialize timebase status and control register (11-26) */
/* unlock TBSCRK */
- immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
- immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
+ out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
+ out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR);
/* initialize the PIT (11-31) */
- immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
+ out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
+ out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
/* System integration timers. Don't change EBDF! (15-27) */
- immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
- reg = immr->im_clkrst.car_sccr;
- reg &= SCCR_MASK;
- reg |= CONFIG_SYS_SCCR;
- immr->im_clkrst.car_sccr = reg;
+ out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
+ clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
+ CONFIG_SYS_SCCR);
/* PLL (CPU clock) settings (15-30) */
- immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
#ifdef CONFIG_SYS_PLPRCR
- mfmask = PLPRCR_MFACT_MSK;
-
- if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
- reg = CONFIG_SYS_PLPRCR; /* reset control bits */
- else {
- reg = immr->im_clkrst.car_plprcr;
- reg &= mfmask; /* isolate MF-related fields */
- reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
- }
- immr->im_clkrst.car_plprcr = reg;
+ if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
+ out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
+ else /* isolate MF-related fields and reset control bits */
+ clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
+ CONFIG_SYS_PLPRCR);
#endif
/*
* Memory Controller:
*/
- /* perform BR0 reset that MPC850 Rev. A can't guarantee */
- reg = memctl->memc_br0;
- reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
- reg |= BR_V; /* then add just the "Bank Valid" bit */
- memctl->memc_br0 = reg;
+ /* Clear everything except Port Size bits & add the "Bank Valid" bit */
+ clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
*/
#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
+ out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
#endif
#if defined(CONFIG_SYS_OR5_REMAP)
- memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
+ out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
+ out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+ out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
#endif
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+ out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
+ out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+ out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
+ out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
- memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+ out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
+ out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
- memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
+ out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
+ out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
- memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
+ out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
+ out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
- memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
+ out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
+ out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
#endif
/*
* Reset CPM
*/
- immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
- do { /* Spin until command processed */
- __asm__ ("eieio");
- } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
+ /* Spin until command processed */
+ while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
+ ;
}
/*
#include <commproc.h>
#include <malloc.h>
#include <net.h>
+#include <asm/io.h>
#include <phy.h>
* Provide for Double Buffering
*/
-typedef volatile struct CommonBufferDescriptor {
+struct common_buf_desc {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
-} RTXBD;
+};
-static RTXBD *rtx = NULL;
+static struct common_buf_desc __iomem *rtx;
static int fec_send(struct eth_device *dev, void *packet, int length);
static int fec_recv(struct eth_device* dev);
{
int j, rc;
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
/* section 16.9.23.3
* Wait for ready
*/
j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+ while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
+ (j < TOUT_LOOP)) {
udelay(1);
j++;
}
printf("TX not ready\n");
}
- rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
- rtx->txbd[txIdx].cbd_datlen = length;
- rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
- __asm__ ("eieio");
+ out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
+ out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
+ setbits_be16(&rtx->txbd[txIdx].cbd_sc,
+ BD_ENET_TX_READY | BD_ENET_TX_LAST);
/* Activate transmit Buffer Descriptor polling */
- fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_x_des_active, 0x01000000);
j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+ while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
+ (j < TOUT_LOOP)) {
udelay(1);
j++;
}
printf("TX timeout\n");
}
/* return only status bits */;
- rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
+ rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
txIdx = (txIdx + 1) % TX_BUF_CNT;
static int fec_recv (struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp =
- (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int length;
for (;;) {
/* section 16.9.23.2 */
- if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
- length = rtx->rxbd[rxIdx].cbd_datlen;
+ length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
- if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
- } else {
+ if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
uchar *rx = net_rx_packets[rxIdx];
length -= 4;
}
/* Give the buffer back to the FEC. */
- rtx->rxbd[rxIdx].cbd_datlen = 0;
+ out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
- (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+ out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
+ BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
- rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
rxIdx++;
}
- __asm__ ("eieio");
-
/* Try to fill Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_r_des_active, 0x01000000);
}
return length;
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
+ setbits_be32(&immr->im_cpm.cp_cptr, mask);
}
static inline void fec_100Mbps(struct eth_device *dev)
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
+ clrbits_be32(&immr->im_cpm.cp_cptr, mask);
}
#endif
static inline void fec_full_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
- fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
+ clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
+ setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
}
static inline void fec_half_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
- fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
+ setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
+ clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
}
static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/*
* Set MII speed to 2.5 MHz or slightly below.
*
* All MII configuration is done via FEC1 registers:
*/
- immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
+ out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
+ ((bd->bi_intfreq + 4999999) / 5000000) << 1);
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
- immr->im_ioport.iop_pdpar |= 0x0080;
- immr->im_ioport.iop_pddir &= ~0x0080;
+ setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
+ clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
#endif
if (fecidx == 0) {
#if !defined(CONFIG_RMII)
- immr->im_ioport.iop_papar |= 0xf830;
- immr->im_ioport.iop_padir |= 0x0830;
- immr->im_ioport.iop_padir &= ~0xf000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
+ setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
- immr->im_cpm.cp_pbpar |= 0x00001001;
- immr->im_cpm.cp_pbdir &= ~0x00001001;
+ setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
+ clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
- immr->im_ioport.iop_pcpar |= 0x000c;
- immr->im_ioport.iop_pcdir &= ~0x000c;
+ setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
+ clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
- immr->im_cpm.cp_pepar |= 0x00000003;
- immr->im_cpm.cp_pedir |= 0x00000003;
- immr->im_cpm.cp_peso &= ~0x00000003;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
- immr->im_cpm.cp_cptr &= ~0x00000100;
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
#else
#if !defined(CONFIG_FEC1_PHY_NORXERR)
- immr->im_ioport.iop_papar |= 0x1000;
- immr->im_ioport.iop_padir &= ~0x1000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
#endif
- immr->im_ioport.iop_papar |= 0xe810;
- immr->im_ioport.iop_padir |= 0x0810;
- immr->im_ioport.iop_padir &= ~0xe000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
+ setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
- immr->im_cpm.cp_pbpar |= 0x00000001;
- immr->im_cpm.cp_pbdir &= ~0x00000001;
+ setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
+ clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
- immr->im_cpm.cp_cptr |= 0x00000100;
- immr->im_cpm.cp_cptr &= ~0x00000050;
+ setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
#endif /* !CONFIG_RMII */
/*
* Configure all of port D for MII.
*/
- immr->im_ioport.iop_pdpar = 0x1fff;
-
- immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
+ out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
+ out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
#endif
#endif /* CONFIG_ETHER_ON_FEC1 */
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
- immr->im_cpm.cp_pepar |= 0x0003fffc;
- immr->im_cpm.cp_pedir |= 0x0003fffc;
- immr->im_cpm.cp_peso &= ~0x000087fc;
- immr->im_cpm.cp_peso |= 0x00037800;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
+ setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
- immr->im_cpm.cp_cptr &= ~0x00000080;
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
#else
#if !defined(CONFIG_FEC2_PHY_NORXERR)
- immr->im_cpm.cp_pepar |= 0x00000010;
- immr->im_cpm.cp_pedir |= 0x00000010;
- immr->im_cpm.cp_peso &= ~0x00000010;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
#endif
- immr->im_cpm.cp_pepar |= 0x00039620;
- immr->im_cpm.cp_pedir |= 0x00039620;
- immr->im_cpm.cp_peso |= 0x00031000;
- immr->im_cpm.cp_peso &= ~0x00008620;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
+ setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
- immr->im_cpm.cp_cptr |= 0x00000080;
- immr->im_cpm.cp_cptr &= ~0x00000028;
+ setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
#endif /* CONFIG_RMII */
#endif /* CONFIG_MPC885_FAMILY */
}
}
-static int fec_reset(volatile fec_t *fecp)
+static int fec_reset(fec_t __iomem *fecp)
{
int i;
* still in progress.
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
+ for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
+ (i < FEC_RESET_DELAY); ++i)
udelay (1);
- }
+
if (i == FEC_RESET_DELAY)
return -1;
static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp =
- (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* We use strictly polling mode only
*/
- fecp->fec_imask = 0;
+ out_be32(&fecp->fec_imask, 0);
/* Clear any pending interrupt
*/
- fecp->fec_ievent = 0xffc0;
+ out_be32(&fecp->fec_ievent, 0xffc0);
/* No need to set the IVEC register */
/* Set station address
*/
#define ea dev->enetaddr
- fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
+ out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
+ (ea[2] << 8) | ea[3]);
+ out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
#undef ea
#if defined(CONFIG_CMD_CDP)
/*
* Turn on multicast address hash table
*/
- fecp->fec_hash_table_high = 0xffffffff;
- fecp->fec_hash_table_low = 0xffffffff;
+ out_be32(&fecp->fec_hash_table_high, 0xffffffff);
+ out_be32(&fecp->fec_hash_table_low, 0xffffffff);
#else
/* Clear multicast address hash table
*/
- fecp->fec_hash_table_high = 0;
- fecp->fec_hash_table_low = 0;
+ out_be32(&fecp->fec_hash_table_high, 0);
+ out_be32(&fecp->fec_hash_table_low, 0);
#endif
/* Set maximum receive buffer size.
*/
- fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
+ out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
/* Set maximum frame length
*/
- fecp->fec_r_hash = PKT_MAXBUF_SIZE;
+ out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
/*
* Setup Buffers and Buffer Desriptors
txIdx = 0;
if (!rtx)
- rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
+ rtx = (struct common_buf_desc __iomem *)
+ (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
- rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx->rxbd[i].cbd_datlen = 0; /* Reset */
- rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
+ out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
+ out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
+ out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
}
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+ setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
- rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
- rtx->txbd[i].cbd_datlen = 0; /* Reset */
- rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
+ out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
+ out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
+ out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
}
- rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+ setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
/* Set receive and transmit descriptor base
*/
- fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
- fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
+ out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
+ out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
/* Enable MII mode
*/
/* Half duplex mode */
- fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl = 0;
+ out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
+ out_be32(&fecp->fec_x_cntrl, 0);
/* Enable big endian and don't care about SDMA FC.
*/
- fecp->fec_fun_code = 0x78000000;
+ out_be32(&fecp->fec_fun_code, 0x78000000);
/*
* Setup the pin configuration of the FEC
/*
* Now enable the transmit and receive processing
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
if (efis->phy_addr == -1) {
#ifdef CONFIG_SYS_DISCOVER_PHY
#endif
/* And last, try to fill Rx Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_r_des_active, 0x01000000);
efis->initialized = 1;
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
/* avoid halt if initialized; mii gets stuck otherwise */
* still in progress.
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
+ for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
+ (i < FEC_RESET_DELAY); ++i)
udelay (1);
- }
+
if (i == FEC_RESET_DELAY) {
printf ("FEC_RESET_DELAY timeout\n");
return;
mii_send(uint mii_cmd)
{
uint mii_reply;
- volatile fec_t *ep;
+ fec_t __iomem *ep;
int cnt;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
+ ep = &immr->im_cpm.cp_fec;
- ep->fec_mii_data = mii_cmd; /* command to phy */
+ out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
/* wait for mii complete */
cnt = 0;
- while (!(ep->fec_ievent & FEC_ENET_MII)) {
+ while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
if (++cnt > 1000) {
printf("mii_send STUCK!\n");
break;
}
}
- mii_reply = ep->fec_mii_data; /* result from phy */
- ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
+ mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
+ out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
return (mii_reply & 0xffff); /* data read from phy */
}
#endif
*/
static void __mii_init(void)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
if (fec_reset(fecp) < 0)
printf ("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
- fecp->fec_imask = 0;
+ out_be32(&fecp->fec_imask, 0);
/* Clear any pending interrupt
*/
- fecp->fec_ievent = 0xffc0;
+ out_be32(&fecp->fec_ievent, 0xffc0);
/* Now enable the transmit and receive processing
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
}
void mii_init (void)
#include <asm/8xx_immap.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int
do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-
- printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
- printf ("SWT = %08x\n", sc->sc_swt);
- printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
- printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
- printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
+
+ printf("SIUMCR= %08x SYPCR = %08x\n",
+ in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr));
+ printf("SWT = %08x\n", in_be32(&sc->sc_swt));
+ printf("SIPEND= %08x SIMASK= %08x\n",
+ in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask));
+ printf("SIEL = %08x SIVEC = %08x\n",
+ in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec));
+ printf("TESR = %08x SDCR = %08x\n",
+ in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr));
return 0;
}
int
do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
int nbanks = 8;
- volatile uint *p = &memctl->memc_br0;
+ uint __iomem *p = &memctl->memc_br0;
int i;
- for (i = 0; i < nbanks; i++, p += 2) {
- if (i < 10) {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- } else {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- }
- }
-
- printf ("MAR = %08x", memctl->memc_mar);
- printf (" MCR = %08x\n", memctl->memc_mcr);
- printf ("MAMR = %08x MBMR = %08x",
- memctl->memc_mamr, memctl->memc_mbmr);
- printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
- printf ("MPTPR = %04x MDR = %08x\n",
- memctl->memc_mptpr, memctl->memc_mdr);
+ for (i = 0; i < nbanks; i++, p += 2)
+ printf("BR%-2d = %08x OR%-2d = %08x\n",
+ i, in_be32(p), i, in_be32(p + 1));
+
+ printf("MAR = %08x", in_be32(&memctl->memc_mar));
+ printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr));
+ printf("MAMR = %08x MBMR = %08x",
+ in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr));
+ printf("\nMSTAT = %04x\n", in_be16(&memctl->memc_mstat));
+ printf("MPTPR = %04x MDR = %08x\n",
+ in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr));
return 0;
}
int
do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile car8xx_t *car = &immap->im_clkrst;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ car8xx_t __iomem *car = &immap->im_clkrst;
- printf ("SCCR = %08x\n", car->car_sccr);
- printf ("PLPRCR= %08x\n", car->car_plprcr);
- printf ("RSR = %08x\n", car->car_rsr);
+ printf("SCCR = %08x\n", in_be32(&car->car_sccr));
+ printf("PLPRCR= %08x\n", in_be32(&car->car_plprcr));
+ printf("RSR = %08x\n", in_be32(&car->car_rsr));
return 0;
}
int
do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile ushort *l, *r;
- volatile uint *R;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ iop8xx_t __iomem *iop = &immap->im_ioport;
+ ushort __iomem *l, *r;
+ uint __iomem *R;
counter = 0;
header ();
l = &iop->iop_padir;
R = &immap->im_cpm.cp_pbdir;
- binary ("PA_DIR", *l++, PA_NBITS);
- binary ("PB_DIR", *R++, PB_NBITS);
- binary ("PA_PAR", *l++, PA_NBITS);
- binary ("PB_PAR", *R++, PB_NBITS);
- binary ("PA_ODR", *l++, PA_NB_ODR);
- binary ("PB_ODR", *R++, PB_NB_ODR);
- binary ("PA_DAT", *l++, PA_NBITS);
- binary ("PB_DAT", *R++, PB_NBITS);
+ binary("PA_DIR", in_be16(l++), PA_NBITS);
+ binary("PB_DIR", in_be32(R++), PB_NBITS);
+ binary("PA_PAR", in_be16(l++), PA_NBITS);
+ binary("PB_PAR", in_be32(R++), PB_NBITS);
+ binary("PA_ODR", in_be16(l++), PA_NB_ODR);
+ binary("PB_ODR", in_be32(R++), PB_NB_ODR);
+ binary("PA_DAT", in_be16(l++), PA_NBITS);
+ binary("PB_DAT", in_be32(R++), PB_NBITS);
header ();
l = &iop->iop_pcdir;
r = &iop->iop_pddir;
- binary ("PC_DIR", *l++, PC_NBITS);
- binary ("PD_DIR", *r++, PD_NBITS);
- binary ("PC_PAR", *l++, PC_NBITS);
- binary ("PD_PAR", *r++, PD_NBITS);
- binary ("PC_SO ", *l++, PC_NBITS);
- binary (" ", 0, 0);
+ binary("PC_DIR", in_be16(l++), PC_NBITS);
+ binary("PD_DIR", in_be16(r++), PD_NBITS);
+ binary("PC_PAR", in_be16(l++), PC_NBITS);
+ binary("PD_PAR", in_be16(r++), PD_NBITS);
+ binary("PC_SO ", in_be16(l++), PC_NBITS);
+ binary(" ", 0, 0);
r++;
- binary ("PC_DAT", *l++, PC_NBITS);
- binary ("PD_DAT", *r++, PD_NBITS);
- binary ("PC_INT", *l++, PC_NBITS);
+ binary("PC_DAT", in_be16(l++), PC_NBITS);
+ binary("PD_DAT", in_be16(r++), PD_NBITS);
+ binary("PC_INT", in_be16(l++), PC_NBITS);
header ();
return 0;
int
do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile uint *p = &cp->cp_brgc1;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immap->im_cpm;
+ uint __iomem *p = &cp->cp_brgc1;
int i = 1;
while (i <= 4)
- prbrg (i++, *p++);
+ prbrg(i++, in_be32(p++));
return 0;
}
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <commproc.h>
/************************************************************************/
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
/* disable all interrupts */
- immr->im_siu_conf.sc_simask = 0;
+ out_be32(&immr->im_siu_conf.sc_simask, 0);
/* Configure CPM interrupts */
cpm_interrupt_init ();
*/
void external_interrupt (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
int irq;
- ulong simask, newmask;
+ ulong simask;
ulong vec, v_bit;
/*
* read the SIVEC register and shift the bits down
* to get the irq number
*/
- vec = immr->im_siu_conf.sc_sivec;
+ vec = in_be32(&immr->im_siu_conf.sc_sivec);
irq = vec >> 26;
v_bit = 0x80000000UL >> irq;
/*
* Read Interrupt Mask Register and Mask Interrupts
*/
- simask = immr->im_siu_conf.sc_simask;
- newmask = simask & (~(0xFFFF0000 >> irq));
- immr->im_siu_conf.sc_simask = newmask;
+ simask = in_be32(&immr->im_siu_conf.sc_simask);
+ clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
if (!(irq & 0x1)) { /* External Interrupt ? */
ulong siel;
/*
* Read Interrupt Edge/Level Register
*/
- siel = immr->im_siu_conf.sc_siel;
+ siel = in_be32(&immr->im_siu_conf.sc_siel);
if (siel & v_bit) { /* edge triggered interrupt ? */
/*
* Rewrite SIPEND Register to clear interrupt
*/
- immr->im_siu_conf.sc_sipend = v_bit;
+ out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
}
}
/*
* Re-Enable old Interrupt Mask
*/
- immr->im_siu_conf.sc_simask = simask;
+ out_be32(&immr->im_siu_conf.sc_simask, simask);
}
/************************************************************************/
*/
static void cpm_interrupt (void *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint vec;
/*
* Get the vector by setting the ACK bit
* and then reading the register.
*/
- immr->im_cpic.cpic_civr = 1;
- vec = immr->im_cpic.cpic_civr;
+ out_be16(&immr->im_cpic.cpic_civr, 1);
+ vec = in_be16(&immr->im_cpic.cpic_civr);
vec >>= 11;
if (cpm_vecs[vec].handler != NULL) {
(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
} else {
- immr->im_cpic.cpic_cimr &= ~(1 << vec);
+ clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
}
/*
* After servicing the interrupt,
* we have to remove the status indicator.
*/
- immr->im_cpic.cpic_cisr |= (1 << vec);
+ setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
}
/*
void irq_install_handler (int vec, interrupt_handler_t * handler,
void *arg)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
}
cpm_vecs[vec].handler = handler;
cpm_vecs[vec].arg = arg;
- immr->im_cpic.cpic_cimr |= (1 << vec);
+ setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
} else {
/* SIU interrupt */
if (irq_vecs[vec].handler != NULL) {
}
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
- immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
+ setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
}
}
void irq_free_handler (int vec)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
vec &= 0xffff;
- immr->im_cpic.cpic_cimr &= ~(1 << vec);
+ clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
cpm_vecs[vec].handler = NULL;
cpm_vecs[vec].arg = NULL;
} else {
/* SIU interrupt */
- immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
+ clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
}
static void cpm_interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ uint cicr;
/*
* Initialize the CPM interrupt controller.
*/
- immr->im_cpic.cpic_cicr =
- (CICR_SCD_SCC4 |
- CICR_SCC_SCC3 |
- CICR_SCB_SCC2 |
- CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
+ cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
+ ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
- immr->im_cpic.cpic_cimr = 0;
+ out_be32(&immr->im_cpic.cpic_cicr, cicr);
+ out_be32(&immr->im_cpic.cpic_cimr, 0);
/*
* Install the error handler.
*/
irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
- immr->im_cpic.cpic_cicr |= CICR_IEN;
+ setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
/*
* Install the cpm interrupt handler
*/
void timer_interrupt_cpu (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* Reset Timer Expired and Timers Interrupt Status */
- immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
__asm__ ("nop");
/*
Clear TEXPS (and TMIST on older chips). SPLSS (on older
to itself. If a bit value should be preserved, read the
register, ZERO the bit and write, not OR, the result back.
*/
- immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
+ setbits_be32(&immr->im_clkrst.car_plprcr, 0);
}
/************************************************************************/
#include <common.h>
#include <mpc8xx.h>
+#include <asm/io.h>
void mpc8xx_reginfo(void)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
- volatile sit8xx_t *timers = &immap->im_sit;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
+ sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
+ sit8xx_t __iomem *timers = &immap->im_sit;
/* Hopefully more PowerPC knowledgable people will add code to display
* other useful registers
*/
printf ("\nSystem Configuration registers\n"
-
"\tIMMR\t0x%08X\n", get_immr(0));
- printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
- printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
+ printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
+ printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
- printf("\tSWT\t0x%08X", sysconf->sc_swt);
- printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
+ printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
+ printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
- sysconf->sc_sipend, sysconf->sc_simask);
+ in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
- sysconf->sc_siel, sysconf->sc_sivec);
+ in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
- sysconf->sc_tesr, sysconf->sc_sdcr);
-
- printf ("Memory Controller Registers\n"
+ in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
- "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
- printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
- printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
- printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
- printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
- printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
- printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
- printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
- printf ("\n"
- "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
- memctl->memc_mamr, memctl->memc_mbmr );
- printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
- memctl->memc_mstat, memctl->memc_mptpr );
- printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
+ printf("Memory Controller Registers\n");
+ printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
+ in_be32(&memctl->memc_or0));
+ printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
+ in_be32(&memctl->memc_or1));
+ printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
+ in_be32(&memctl->memc_or2));
+ printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
+ in_be32(&memctl->memc_or3));
+ printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
+ in_be32(&memctl->memc_or4));
+ printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
+ in_be32(&memctl->memc_or5));
+ printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
+ in_be32(&memctl->memc_or6));
+ printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
+ in_be32(&memctl->memc_or7));
+ printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
+ in_be32(&memctl->memc_mbmr));
+ printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
+ in_be16(&memctl->memc_mptpr));
+ printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
- printf ("\nSystem Integration Timers\n"
- "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
- timers->sit_tbscr, timers->sit_rtcsc);
- printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
+ printf("\nSystem Integration Timers\n");
+ printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
+ in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
+ printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
/*
* May be some CPM info here?
#define SMC_INDEX 0
#define PROFF_SMC PROFF_SMC1
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
+#define IOPINS 0xc0
#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
#define SMC_INDEX 1
#define PROFF_SMC PROFF_SMC2
#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
+#define IOPINS 0xc00
#endif /* CONFIG_8xx_CONS_SMCx */
#endif
#endif
-typedef volatile struct serialbuffer {
+struct serialbuffer {
cbd_t rxbd; /* Rx BD */
cbd_t txbd; /* Tx BD */
uint rxindex; /* index for next character to read */
- volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
- volatile uchar txbuf; /* tx buffers */
-} serialbuffer_t;
+ uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
+ uchar txbuf; /* tx buffers */
+};
-static void serial_setdivisor(volatile cpm8xx_t *cp)
+static void serial_setdivisor(cpm8xx_t __iomem *cp)
{
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
#endif
- if(divisor<=0x1000) {
- cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
- } else {
- cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
- }
+ if (divisor <= 0x1000)
+ out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
+ else
+ out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
+ CPM_BRG_DIV16);
}
/*
static void smc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = &(im->im_cpm);
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &(im->im_cpm);
/* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
* Wire BRG1 to SMCx
*/
- cp->cp_simode = 0x00000000;
+ out_be32(&cp->cp_simode, 0);
serial_setdivisor(cp);
}
static int smc_init (void)
{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile smc_t *sp;
- volatile smc_uart_t *up;
- volatile cpm8xx_t *cp = &(im->im_cpm);
- uint dpaddr;
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ smc_t __iomem *sp;
+ smc_uart_t __iomem *up;
+ cpm8xx_t __iomem *cp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
/* initialize pointers to SMC */
- sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
- up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+ sp = cp->cp_smc + SMC_INDEX;
+ up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
/* Disable relocation */
- up->smc_rpbase = 0;
+ out_be16(&up->smc_rpbase, 0);
/* Disable transmitter/receiver. */
- sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+ clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
/* Enable SDMA. */
- im->im_siu_conf.sc_sdcr = 1;
+ out_be32(&im->im_siu_conf.sc_sdcr, 1);
/* clear error conditions */
#ifdef CONFIG_SYS_SDSR
- im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
+ out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
#else
- im->im_sdma.sdma_sdsr = 0x83;
+ out_8(&im->im_sdma.sdma_sdsr, 0x83);
#endif
/* clear SDMA interrupt mask */
#ifdef CONFIG_SYS_SDMR
- im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
+ out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
#else
- im->im_sdma.sdma_sdmr = 0x00;
+ out_8(&im->im_sdma.sdma_sdmr, 0x00);
#endif
-#if defined(CONFIG_8xx_CONS_SMC1)
- /* Use Port B for SMC1 instead of other functions. */
- cp->cp_pbpar |= 0x000000c0;
- cp->cp_pbdir &= ~0x000000c0;
- cp->cp_pbodr &= ~0x000000c0;
-#else /* CONFIG_8xx_CONS_SMC2 */
- /* Use Port B for SMC2 instead of other functions.
- */
- cp->cp_pbpar |= 0x00000c00;
- cp->cp_pbdir &= ~0x00000c00;
- cp->cp_pbodr &= ~0x00000c00;
-#endif
+ /* Use Port B for SMCx instead of other functions. */
+ setbits_be32(&cp->cp_pbpar, IOPINS);
+ clrbits_be32(&cp->cp_pbdir, IOPINS);
+ clrbits_be16(&cp->cp_pbodr, IOPINS);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- dpaddr = CPM_SERIAL_BASE;
-
- rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
+ rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
- rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
- rtx->rxbd.cbd_sc = 0;
+ out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
+ out_be16(&rtx->rxbd.cbd_sc, 0);
- rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
- rtx->txbd.cbd_sc = 0;
+ out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
+ out_be16(&rtx->txbd.cbd_sc, 0);
/* Set up the uart parameters in the parameter ram. */
- up->smc_rbase = dpaddr;
- up->smc_tbase = dpaddr+sizeof(cbd_t);
- up->smc_rfcr = SMC_EB;
- up->smc_tfcr = SMC_EB;
+ out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
+ out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
+ out_8(&up->smc_rfcr, SMC_EB);
+ out_8(&up->smc_tfcr, SMC_EB);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
- sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
+ out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
/* Mask all interrupts and remove anything pending.
*/
- sp->smc_smcm = 0;
- sp->smc_smce = 0xff;
+ out_8(&sp->smc_smcm, 0);
+ out_8(&sp->smc_smce, 0xff);
/* Set up the baud rate generator */
smc_setbrg ();
/* Make the first buffer the only buffer. */
- rtx->txbd.cbd_sc |= BD_SC_WRAP;
- rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
+ setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
/* single/multi character receive. */
- up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
- up->smc_maxidl = CONFIG_SYS_MAXIDLE;
- rtx->rxindex = 0;
+ out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
+ out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
+ out_be32(&rtx->rxindex, 0);
/* Initialize Tx/Rx parameters. */
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
+ ;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ out_be16(&cp->cp_cpcr,
+ mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
+ ;
/* Enable transmitter/receiver. */
- sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+ setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
return (0);
}
static void
smc_putc(const char c)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
if (c == '\n')
smc_putc ('\r');
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
/* Wait for last character to go. */
- rtx->txbuf = c;
- rtx->txbd.cbd_datlen = 1;
- rtx->txbd.cbd_sc |= BD_SC_READY;
- __asm__("eieio");
+ out_8(&rtx->txbuf, c);
+ out_be16(&rtx->txbd.cbd_datlen, 1);
+ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
- while (rtx->txbd.cbd_sc & BD_SC_READY) {
+ while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
WATCHDOG_RESET ();
- __asm__("eieio");
- }
}
static void
static int
smc_getc(void)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
unsigned char c;
+ uint rxindex;
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
/* Wait for character to show up. */
- while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
+ while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
WATCHDOG_RESET ();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
*/
- c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
- rtx->rxindex++;
+ rxindex = in_be32(&rtx->rxindex);
+ c = in_8(rtx->rxbuf + rxindex);
+ rxindex++;
/* check if all char are readout, then make prepare for next receive */
- if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
- rtx->rxindex = 0;
- rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
+ if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
+ rxindex = 0;
+ setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
}
+ out_be32(&rtx->rxindex, rxindex);
return(c);
}
static int
smc_tstc(void)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
-
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
- return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
+ return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}
struct serial_device serial_smc_device =
#include <common.h>
#include <mpc8xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int get_clocks (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
- volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
- uint sccr = immap->im_clkrst.car_sccr;
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+ uint sccr = in_be32(&immap->im_clkrst.car_sccr);
/*
* If for some reason measuring the gclk frequency won't
* work, we return the hardwired value.
#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
#endif
+#define CPM_SPI_BASE_RX CPM_SPI_BASE
+#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
+
/* -------------------
* Function prototypes
* ------------------- */
* *********************************************************************** */
void spi_init_f (void)
{
- unsigned int dpaddr;
-
- volatile spi_t *spi;
- volatile immap_t *immr;
- volatile cpm8xx_t *cp;
- volatile cbd_t *tbdf, *rbdf;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
/* 1 */
/* ------------------------------------------------
* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
* -------------------------------------------- */
- cp->cp_pbpar |= 0x0000000E; /* set bits */
- cp->cp_pbpar &= ~0x00000001; /* reset bit */
+ clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
/* ----------------------------------------------
* In/Out or per. Function 0/1
* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
* ---------------------------------------------- */
- cp->cp_pbdir |= 0x0000000F;
+ setbits_be32(&cp->cp_pbdir, 0x0000000F);
/* ----------------------------------------------
* open drain or active output
* PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
* ---------------------------------------------- */
- cp->cp_pbodr |= 0x00000008;
- cp->cp_pbodr &= ~0x00000007;
+ clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
/* Initialize the parameter ram.
* We need to make sure many things are initialized to zero
*/
- spi->spi_rstate = 0;
- spi->spi_rdp = 0;
- spi->spi_rbptr = 0;
- spi->spi_rbc = 0;
- spi->spi_rxtmp = 0;
- spi->spi_tstate = 0;
- spi->spi_tdp = 0;
- spi->spi_tbptr = 0;
- spi->spi_tbc = 0;
- spi->spi_txtmp = 0;
-
- dpaddr = CPM_SPI_BASE;
+ out_be32(&spi->spi_rstate, 0);
+ out_be32(&spi->spi_rdp, 0);
+ out_be16(&spi->spi_rbptr, 0);
+ out_be16(&spi->spi_rbc, 0);
+ out_be32(&spi->spi_rxtmp, 0);
+ out_be32(&spi->spi_tstate, 0);
+ out_be32(&spi->spi_tdp, 0);
+ out_be16(&spi->spi_tbptr, 0);
+ out_be16(&spi->spi_tbc, 0);
+ out_be32(&spi->spi_txtmp, 0);
/* 3 */
/* Set up the SPI parameters in the parameter ram */
- spi->spi_rbase = dpaddr;
- spi->spi_tbase = dpaddr + sizeof (cbd_t);
+ out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
+ out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
/***********IMPORTANT******************/
* is missing from the sample I2C driver. If you dont
* initialize these pointers, the kernel hangs.
*/
- spi->spi_rbptr = spi->spi_rbase;
- spi->spi_tbptr = spi->spi_tbase;
+ out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
+ out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
/* 4 */
/* Init SPI Tx + Rx Parameters */
- while (cp->cp_cpcr & CPM_CR_FLG)
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
- while (cp->cp_cpcr & CPM_CR_FLG)
+
+ out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
+ CPM_CR_FLG);
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
;
/* 5 */
/* Set SDMA configuration register */
- immr->im_siu_conf.sc_sdcr = 0x0001;
+ out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
/* 6 */
/* Set to big endian. */
- spi->spi_tfcr = SMC_EB;
- spi->spi_rfcr = SMC_EB;
+ out_8(&spi->spi_tfcr, SMC_EB);
+ out_8(&spi->spi_rfcr, SMC_EB);
/* 7 */
/* Set maximum receive size. */
- spi->spi_mrblr = MAX_BUFFER;
+ out_be16(&spi->spi_mrblr, MAX_BUFFER);
/* 8 + 9 */
/* tx and rx buffer descriptors */
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
- tbdf->cbd_sc &= ~BD_SC_READY;
- rbdf->cbd_sc &= ~BD_SC_EMPTY;
+ clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
+ clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
/* Set the bd's rx and tx buffer address pointers */
- rbdf->cbd_bufaddr = (ulong) rxbuf;
- tbdf->cbd_bufaddr = (ulong) txbuf;
+ out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
+ out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
/* 10 + 11 */
- cp->cp_spim = 0; /* Mask all SPI events */
- cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
+ out_8(&cp->cp_spim, 0); /* Mask all SPI events */
+ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
return;
}
* *********************************************************************** */
void spi_init_r (void)
{
- volatile cpm8xx_t *cp;
- volatile spi_t *spi;
- volatile immap_t *immr;
- volatile cbd_t *tbdf, *rbdf;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
/* tx and rx buffer descriptors */
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Allocate memory for RX and TX buffers */
rxbuf = (uchar *) malloc (MAX_BUFFER);
txbuf = (uchar *) malloc (MAX_BUFFER);
- rbdf->cbd_bufaddr = (ulong) rxbuf;
- tbdf->cbd_bufaddr = (ulong) txbuf;
+ out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
+ out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
return;
}
**************************************************************************** */
ssize_t spi_xfer (size_t count)
{
- volatile immap_t *immr;
- volatile cpm8xx_t *cp;
- volatile spi_t *spi;
- cbd_t *tbdf, *rbdf;
- ushort loop;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
int tm;
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
-
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Set CS for device */
- cp->cp_pbdat &= ~0x0001;
+ clrbits_be32(&cp->cp_pbdat, 0x0001);
/* Setting tx bd status and data length */
- tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
- tbdf->cbd_datlen = count;
+ out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
+ out_be16(&tbdf->cbd_datlen, count);
/* Setting rx bd status and data length */
- rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
- rbdf->cbd_datlen = 0; /* rx length has no significance */
-
- loop = cp->cp_spmode & SPMODE_LOOP;
- cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */
- loop |
- SPMODE_REV |
- SPMODE_MSTR |
- SPMODE_EN |
- SPMODE_LEN(8) | /* 8 Bits per char */
- SPMODE_PM(0x8) ; /* medium speed */
- cp->cp_spim = 0; /* Mask all SPI events */
- cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
+ out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
+ out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
+
+ clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
+ SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
+ out_8(&cp->cp_spim, 0); /* Mask all SPI events */
+ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
/* start spi transfer */
- cp->cp_spcom |= SPI_STR; /* Start transmit */
+ setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
/* --------------------------------
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* -------------------------------- */
for (tm=0; tm<1000; ++tm) {
- if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
+ if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
break;
- }
- if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
+ if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
break;
- }
udelay (1000);
}
if (tm >= 1000) {
}
/* Clear CS for device */
- cp->cp_pbdat |= 0x0001;
+ setbits_be32(&cp->cp_pbdat, 0x0001);
return count;
}
#include <linux/types.h>
#include <asm/8xx_immap.h>
+#include <asm/io.h>
#ifdef __KERNEL__
static __inline__ void
iopin_set_high(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- *datp |= (1 << (31 - iopin->pin));
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ setbits_be32(datp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_low(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- *datp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ clrbits_be32(datp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_high(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- return (*datp >> (31 - iopin->pin)) & 1;
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return (in_be32(datp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_low(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
static __inline__ void
iopin_set_out(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- *dirp |= (1 << (31 - iopin->pin));
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ setbits_be32(dirp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_in(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- *dirp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ clrbits_be32(dirp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_out(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- return (*dirp >> (31 - iopin->pin)) & 1;
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_in(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
static __inline__ void
iopin_set_odr(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- *odrp |= (1 << (15 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ setbits_be16(odrp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- *odrp |= (1 << (31 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ setbits_be16(odrp, 1 << (31 - iopin->pin));
}
}
static __inline__ void
iopin_set_act(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- *odrp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ clrbits_be16(odrp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- *odrp &= ~(1 << (31 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ clrbits_be16(odrp, 1 << (31 - iopin->pin));
}
}
static __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- return (*odrp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- return (*odrp >> (31 - iopin->pin)) & 1;
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_act(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
static __inline__ void
iopin_set_ded(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- *parp |= (1 << (31 - iopin->pin));
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ setbits_be32(parp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_gen(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- *parp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ clrbits_be32(parp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- return (*parp >> (31 - iopin->pin)) & 1;
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return (in_be32(parp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
static __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- *sorp |= (1 << (15 - iopin->pin));
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ setbits_be16(sorp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- *sorp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ clrbits_be16(sorp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- return (*sorp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
static __inline__ void
iopin_set_falledge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- *intp |= (1 << (15 - iopin->pin));
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ setbits_be16(intp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_anyedge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- *intp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ clrbits_be16(intp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_falledge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- return (*intp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return (in_be16(intp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
static __inline__ uint
iopin_is_anyedge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
*/
#include <common.h>
+#include <asm/io.h>
/* ------------------------------------------------------------------------- */
unsigned long temp;
#if defined(CONFIG_8xx)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* unlock */
- immap->im_sitk.sitk_tbk = KAPWR_KEY;
+ out_be32(&immap->im_sitk.sitk_tbk, KAPWR_KEY);
#endif
/* reset */
#if defined(CONFIG_8xx)
/* enable */
- immap->im_sit.sit_tbscr |= TBSCR_TBE;
+ setbits_be16(&immap->im_sit.sit_tbscr, TBSCR_TBE);
#endif
return (0);
}
/* MPC 8xx */
#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
- void reset_8xx_watchdog(volatile immap_t *immr);
+ void reset_8xx_watchdog(immap_t __iomem *immr);
#endif
#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
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