+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = m5271evb.o
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
- puts ("Board: Freescale M5271EVB\n");
- return 0;
-};
-
-phys_size_t initdram (int board_type) {
-
- int i;
-
- /* Enable Address lines 23-21 and lower 16bits of data path */
- mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
- MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
- MCF_GPIO_AD_DATAL);
-
- /* Set CS2 pin to be SD_CS0 */
- mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
- | MCF_GPIO_PAR_CS_PAR_CS2);
-
- /* Configure SDRAM Control Pin Assignemnt Register */
- mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
- MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
- MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
- MCF_GPIO_SDRAM_SDCS_11);
- asm(" nop");
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
- /* Initialize DRAM Control Register: DCR */
- mbar_writeShort(MCF_SDRAMC_DCR,
- MCF_SDRAMC_DCR_RTIM(2)
- | MCF_SDRAMC_DCR_RC(0x2E));
- asm(" nop");
-
- /*
- * Initialize DACR0
- *
- * CASL: 01
- * CBM: cmd at A20, bank select bits 21 and up
- * PS: 32bit port size
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
- | MCF_SDRAMC_DACRn_CASL(1)
- | MCF_SDRAMC_DACRn_CBM(3)
- | MCF_SDRAMC_DACRn_PS(0));
- asm(" nop");
-
- /* Initialize DMR0 */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_16M
- | MCF_SDRAMC_DMRn_V);
- asm(" nop");
-
- /* Set IP bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_IP);
- asm(" nop");
-
- /* Wait at least 20ns to allow banks to precharge */
- for (i = 0; i < 5; i++)
- asm(" nop");
-
- /* Write to this block to initiate precharge */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
- asm(" nop");
-
- /* Set RE bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_RE);
-
- /* Wait for at least 8 auto refresh cycles to occur */
- for (i = 0; i < 2000; i++)
- asm(" nop");
-
- /* Finish the configuration by issuing the MRS */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_MRS);
- asm(" nop");
-
- /*
- * Write to the SDRAM Mode Register A0-A11 = 0x400
- *
- * Write Burst Mode = Programmed Burst Length
- * Op Mode = Standard Op
- * CAS Latency = 2
- * Burst Type = Sequential
- * Burst Length = 1
- */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
- asm(" nop");
- }
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
-
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
- .text :
- {
- arch/m68k/cpu/mcf52x2/start.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
-
- .reloc :
- {
- __got_start = .;
- KEEP(*(.got))
- __got_end = .;
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- _sbss = .;
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = idmr.o flash.o
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xff800000
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE 0x800000
-#define EN29LV640 0x227e227e
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (AMD_MANUFACT & FLASH_VENDMASK):
- printf ("AMD: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (EN29LV640 & FLASH_TYPEMASK):
- printf ("EN29LV640 (16Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
- Done:
- return;
-}
-
-
-unsigned long flash_init (void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id =
- (AMD_MANUFACT & FLASH_VENDMASK) |
- (EN29LV640 & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- if (i == 0)
- flashbase = PHYS_FLASH_1;
- else
- panic ("configured to many flash banks!\n");
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] = flashbase + 0x10000 * j;
- }
- size += flash_info[i].size;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
-
- return size;
-}
-
-
-#define CMD_READ_ARRAY 0x00F0
-#define CMD_UNLOCK1 0x00AA
-#define CMD_UNLOCK2 0x0055
-#define CMD_ERASE_SETUP 0x0080
-#define CMD_ERASE_CONFIRM 0x0030
-#define CMD_PROGRAM 0x00A0
-#define CMD_UNLOCK_BYPASS 0x0020
-
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
-
-#define BIT_ERASE_DONE 0x0080
-#define BIT_RDY_MASK 0x0080
-#define BIT_PROGRAM_ERROR 0x0020
-#define BIT_TIMEOUT 0x80000000 /* our flag */
-
-#define READY 1
-#define ERR 2
-#define TMO 4
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- ulong result;
- int iflag, prot, sect;
- int rc = ERR_OK;
- int chip1;
- ulong start;
-
- /* first look for protection bits */
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (AMD_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot)
- return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- iflag = disable_interrupts ();
-
- printf ("\n");
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- if (info->protect[sect] == 0) { /* not protected */
- volatile u16 *addr =
- (volatile u16 *) (info->start[sect]);
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- *addr = CMD_ERASE_CONFIRM;
-
- /* wait until flash is ready */
- chip1 = 0;
-
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
- chip1 = TMO;
- break;
- }
-
- if (!chip1
- && (result & 0xFFFF) & BIT_ERASE_DONE)
- chip1 = READY;
-
- } while (!chip1);
-
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
- if (chip1 == ERR) {
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if (chip1 == TMO) {
- rc = ERR_TIMOUT;
- goto outahere;
- }
-
- printf ("ok.\n");
- } else { /* it was protected */
-
- printf ("protected!\n");
- }
- }
-
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- outahere:
- /* allow flash to settle - wait 10 ms */
- printf("Waiting 10 ms...");
- udelay (10000);
-
-/* for (i = 0; i < 10 * 1000 * 1000; ++i)
- asm(" nop");
-*/
-
- printf("done\n");
- if (iflag)
- enable_interrupts ();
-
-
- return rc;
-}
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile u16 *addr = (volatile u16 *) dest;
- ulong result;
- int rc = ERR_OK;
- int iflag;
- int chip1;
- ulong start;
-
- /*
- * Check if Flash is (sufficiently) erased
- */
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- iflag = disable_interrupts ();
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_PROGRAM;
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait until flash is ready */
- chip1 = 0;
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
- chip1 = ERR | TMO;
- break;
- }
- if (!chip1 && ((result & 0x80) == (data & 0x80)))
- chip1 = READY;
-
- } while (!chip1);
-
- *addr = CMD_READ_ARRAY;
-
- if (chip1 == ERR || *addr != data)
- rc = ERR_PROG_ERROR;
-
- if (iflag)
- enable_interrupts ();
-
- return rc;
-}
-
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp, data;
- int rc;
-
- if (addr & 1) {
- printf ("unaligned destination not supported\n");
- return ERR_ALIGN;
- }
-
-#if 0
- if (cnt & 1) {
- printf ("odd transfer sizes not supported\n");
- return ERR_ALIGN;
- }
-#endif
-
- wp = addr;
-
- if (addr & 1) {
- data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
- src);
- if ((rc = write_word (info, wp - 1, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- while (cnt >= 2) {
- data = *((volatile u16 *) src);
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 1) {
- data = (*((volatile u8 *) src) << 8) |
- *((volatile u8 *) (wp + 1));
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- return ERR_OK;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
- puts ("Board: iDMR\n");
- return 0;
-};
-
-phys_size_t initdram (int board_type) {
- int i;
-
- /*
- * After reset, CS0 is configured to cover entire address space. We
- * need to configure it to its proper values, so that writes to
- * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
- * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
- */
-
- /* Flash chipselect, CS0 */
- /* ;CSAR0: Flash at 0xFF800000 */
- mbar_writeShort(0x0080, 0xFF80);
-
- /* CSCR0: Flash 6 waits, 16bit */
- mbar_writeShort(0x008A, 0x1980);
-
- /* CSMR0: Flash 8MB, R/W, valid */
- mbar_writeLong(0x0084, 0x007F0001);
-
-
- /*
- * SDRAM configuration proper
- */
-
- /*
- * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
- * not enable data pins D[15:0], as we have 16 bit port to SDRAM
- */
- mbar_writeByte(MCF_GPIO_PAR_AD,
- MCF_GPIO_AD_ADDR23 |
- MCF_GPIO_AD_ADDR22 |
- MCF_GPIO_AD_ADDR21);
-
- /* No need to configure BS pins - reset values are OK */
-
- /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
- mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
-
- /* SDRAM Control Pin Assignment Reg. */
- mbar_writeByte(MCF_GPIO_PAR_SDRAM,
- MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
- MCF_GPIO_SDRAM_SDWE |
- MCF_GPIO_SDRAM_SCAS |
- MCF_GPIO_SDRAM_SRAS |
- MCF_GPIO_SDRAM_SCKE |
- MCF_GPIO_SDRAM_SDCS_01);
-
- /*
- * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5
- * iterations will do, but we do 10 just to be safe.
- */
- for (i = 0; i < 10; ++i)
- asm(" nop");
-
-
- /* 1. Initialize DRAM Control Register: DCR */
- mbar_writeShort(MCF_SDRAMC_DCR,
- MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
- MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
-
-
- /*
- * 2. Initialize DACR0
- *
- * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
- * CBM: cmd at A20, bank select bits 21 and up
- * PS: 16 bit
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
- MCF_SDRAMC_DACRn_BA(0x00) |
- MCF_SDRAMC_DACRn_CASL(0x03) |
- MCF_SDRAMC_DACRn_CBM(0x03) |
- MCF_SDRAMC_DACRn_PS(0x03));
-
- /* Initialize DMR0 */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_16M |
- MCF_SDRAMC_DMRn_V);
-
-
- /* 3. Set IP bit in DACR to initiate PALL command */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_IP);
-
- /* Write to this block to initiate precharge */
- *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
-
- /*
- * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
- * wait a wee longer, just to be safe.
- */
- for (i = 0; i < 5; ++i)
- asm(" nop");
-
-
- /* 4. Set RE bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_RE);
-
- /*
- * Wait for at least 8 auto refresh cycles to occur, i.e. at least
- * 781 bus cycles.
- */
- for (i = 0; i < 1000; ++i)
- asm(" nop");
-
- /* Finish the configuration by issuing the MRS */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_MRS);
-
- /*
- * Write to the SDRAM Mode Register A0-A11 = 0x400
- *
- * Write Burst Mode = Programmed Burst Length
- * Op Mode = Standard Op
- * CAS Latency = 3
- * Burst Type = Sequential
- * Burst Length = 1
- */
- *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-
-int testdram (void) {
-
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
- .text :
- {
- arch/m68k/cpu/mcf52x2/start.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
-
- .reloc :
- {
- __got_start = .;
- KEEP(*(.got))
- __got_end = .;
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- _sbss = .;
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - - - idmr - -
Active m68k mcf52x2 - - cobra5272 cobra5272 - -
Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
-Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-mx1ads arm arm920t - 2014-01-13
-mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
+idmr m68k mcf52x2 - 2014-01-28
+M5271EVB m68k mcf52x2 - 2014-01-28
+dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen <michael@schwingen.org>
+mx1ads arm arm920t e570aca9 2014-01-13
+mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
omap730p2 arm arm926ejs 79c5c08d 2013-11-11
pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
+++ /dev/null
-/*
- * Configuation settings for the Freescale M5271EVB
- *
- * Based on MC5272C3 and r5200 board configs
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5271EVB_H
-#define _M5271EVB_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_M5271EVB /* define board type */
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE 115200
-
-#undef CONFIG_WATCHDOG /* disable watchdog */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_OFFSET 0x4000
-#else
-#define CONFIG_ENV_ADDR 0xffe04000
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-#define CONFIG_BOOTFILE "u-boot.bin"
-#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_RETRY_COUNT 5
-# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-# define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif /* FEC_ENET */
-
-#define CONFIG_HOSTNAME M5271EVB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=10000\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp $loadaddr $uboot\0" \
- "upd=run load; run prog\0" \
- "prog=prot off ffe00000 ffe3ffff;" \
- "era ffe00000 ffe3ffff;" \
- "cp.b $loadaddr ffe00000 $filesize;" \
- "save\0" \
- ""
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
-
-#define CONFIG_SYS_HZ 1000000
-
-/* Clock configuration
- * The external oscillator is a 25.000 MHz
- * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
- * bus_clk = (cpu_clk/2) (fixed ratio)
- *
- * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
- * match the new clock speed. Max cpu_clk is 150 MHz.
- */
-#define CONFIG_SYS_CLK 100000000
-#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE 0x20000
-#else
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_SIZE 0x200000
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/* Chip Select 0 : Boot Flash */
-#define CONFIG_SYS_CS0_BASE 0xFFE00000
-#define CONFIG_SYS_CS0_MASK 0x001F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-
-/* Chip Select 1 : External SRAM */
-#define CONFIG_SYS_CS1_BASE 0x30000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001900
-
-#endif /* _M5271EVB_H */
+++ /dev/null
-/*
- * Configuration settings for the iDMR board
- *
- * Based on MC5272C3, r5200 and M5271EVB board configs
- * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _IDMR_H
-#define _IDMR_H
-
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_IDMR /* define board type */
-
-#undef CONFIG_WATCHDOG /* disable watchdog */
-
-/*
- * Default environment settings
- */
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
-#define CONFIG_ETHPRIME
-#define CONFIG_IPADDR 192.168.30.1
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_ROOTPATH ""
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_HOSTNAME idmr
-#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage"
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \
- "filesystem over NFS; echo"
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
- "$(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "ethact=FEC\0 " \
- "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
- "cp.b 200000 ff800000 $(filesize);" \
- "prot on ff800000 ff81ffff\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=/tftpboot/idmr/u-boot.bin\0" \
- ""
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Configuration for environment, which occupies third sector in flash.
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_ADDR 0xff820000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#else /* CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#endif /* !CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
-
-#define CONFIG_SYS_HZ (50000000 / 64)
-#define CONFIG_SYS_CLK 100000000
-
-#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
-
-/*
- * Ethernet
- */
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE 0x20000
-#else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
-
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-/*
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
- */
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/* Port configuration */
-#define CONFIG_SYS_FECI2C 0xF0
-
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=idmr-0"
-
-#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \
- "64k(env)," \
- "640k(kernel)," \
- "2m(rootfs)," \
- "-(user)";
-
-#if defined(CONFIG_CMD_MII)
-#error "MII commands don't work on iDMR board and should not be enabled."
-#endif
-
-#endif /* _IDMR_H */
projects / u-boot / commitdiff