While the 1.0 and 1.2 spin of the bf533-stamp boards can handle the higher
SCLK speeds just fine, the 1.1 spin cannot due to the bugs introduced with
the shortened SDRAM traces. So lower the SCLK speed down to a value that
all three can handle.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
+#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
/*