]> git.sur5r.net Git - u-boot/commitdiff
armv8/ls1043a: Implement workaround for erratum A009660
authorMingkai Hu <mingkai.hu@nxp.com>
Tue, 2 Feb 2016 03:28:03 +0000 (11:28 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 24 Feb 2016 16:40:56 +0000 (08:40 -0800)
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/include/asm/arch-fsl-layerscape/config.h

index 7ff01481bef68b2ebbf0b3fbd0ba960288e7bd37..213ce3a82468bb142d4cc53217f0c09dc97781af 100644 (file)
@@ -213,6 +213,24 @@ static void erratum_a009929(void)
 #endif
 }
 
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+       && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error A009660 and A008514 can not be both enabled.
+#endif
+
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+       u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+       out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
 
        /* Erratum */
        erratum_a009929();
+       erratum_a009660();
 }
 #endif
 
index a4eb096a64ebb6e1392099d66f663b46f6c2f6d5..0ef7c9dd957ddc84ec164a966869ad7b1ac75528 100644 (file)
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A009660
 #else
 #error SoC not defined
 #endif