The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Timeout the transfer after 5 mS. This is usually a bit more, since
+ * the code in the tightloops this timeout is used in adds some overhead.
+ */
+#define FEC_XFER_TIMEOUT 5000
+
#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif
unsigned int status;
uint32_t size, end;
uint32_t addr;
+ int timeout = FEC_XFER_TIMEOUT;
+ int ret = 0;
/*
* This routine transmits one frame. This routine only accepts
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
udelay(1);
invalidate_dcache_range(addr, addr + size);
+ if (!timeout--) {
+ ret = -EINVAL;
+ break;
+ }
}
debug("fec_send: status 0x%x index %d\n",
else
fec->tbd_index = 1;
- return 0;
+ return ret;
}
/**