ARM: uniphier: set up charge pump current for MPLL of LD11 SoC

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index c66f083fae705b0aa787ab6cebf6185a7bf1945c..697eb7aabf01c4889b6acce5ff79d080d23fb780 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -18,6 +18,8 @@
 #define SC_PLLCTRL_SSC_EN              BIT(31)
 #define SC_PLLCTRL2_NRSTDS             BIT(28)
 #define SC_PLLCTRL2_SSC_JK_MASK                GENMASK(26, 0)
+#define SC_PLLCTRL3_REGI_SHIFT         16
+#define SC_PLLCTRL3_REGI_MASK          GENMASK(19, 16)
 
 /* PLL type: VPLL27 */
 #define SC_VPLL27CTRL_WP               BIT(0)
@@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
        return 0;
 }
 
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
+{
+       void __iomem *base;
+       u32 tmp;
+
+       base = ioremap(reg_base, SZ_16);
+       if (!base)
+               return -ENOMEM;
+
+       tmp = readl(base + 8);  /* SSCPLLCTRL */
+       tmp &= ~SC_PLLCTRL3_REGI_MASK;
+       tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+       writel(tmp, base + 8);
+
+       iounmap(base);
+
+       return 0;
+}
+
 int uniphier_ld20_vpll27_init(unsigned long reg_base)
 {
        void __iomem *base;

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index 7746deb72d1d1067ac1ca28d0313d2473e54ec34..02befa298b465f06fe1af227a748f37686d6a148 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -18,6 +18,8 @@ void uniphier_ld11_pll_init(void)
        uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);     /* 1500MHz -> 1600MHz */
        uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
+       uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
        mdelay(1);
 
        uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);

diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h
index d7e93037d66e50efed62f2320f4cec81a816cd1f..5eefc4ee31159f174a8ec56e2c3447e2a7d1370c 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll.h
+++ b/arch/arm/mach-uniphier/clk/pll.h
@@ -15,6 +15,7 @@ void uniphier_ld4_dpll_ssc_en(void);
 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
                              unsigned int ssc_rate, unsigned int divn);
 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
 int uniphier_ld20_vpll27_init(unsigned long reg_base);
 int uniphier_ld20_dspll_init(unsigned long reg_base);