--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_LINKAGE_H
+#define __ASM_ARC_LINKAGE_H
+
+#define ASM_NL ` /* use '`' to mark new line in macro */
+
+#endif /* __ASM_ARC_LINKAGE_H */
select CPU_V7
select SUPPORT_SPL
+config TARGET_BAV335X
+ bool "Support bav335x"
+ select CPU_V7
+ select SUPPORT_SPL
+ help
+ The BAV335x OEM Network Processor integrates all the functions of an
+ embedded network computer in a small, easy to use SODIMM module which
+ incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+ processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+ ethernet with simple connection to external connectors.
+
+ For more information, visit: http://birdland.com/oem
+
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
+config TARGET_SOCFPGA_ARRIA5
+ bool "Support socfpga_arria5"
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
select CPU_V7
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
+source "board/birdland/bav335x/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
bool "Twister"
select SUPPORT_SPL
+config TARGET_OMAP3_CAIRO
+ bool "QUIPOS CAIRO"
+ select SUPPORT_SPL
+
endchoice
config DM
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
+source "board/quipos/cairo/Kconfig"
endif
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
- omap_nand_switch_ecc(0, 0);
+ if (argc == 2) {
+ omap_nand_switch_ecc(0, 1);
+ } else {
+ if (strncmp(argv[2], "hamming", 7) == 0)
+ omap_nand_switch_ecc(0, 1);
+ else if (strncmp(argv[2], "bch8", 4) == 0)
+ omap_nand_switch_ecc(0, 8);
+ else
+ goto usage;
+ }
} else {
goto usage;
}
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_SOCFPGA) += \
+ socfpga_arria5_socdk.dtb \
+ socfpga_cyclone5_socdk.dtb \
+ socfpga_cyclone5_socrates.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ mmc0: dwmmc0@ff704000 {
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_arria5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria V SoC Development Kit";
+ compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&portb 18 0>;
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+#define CONFIG_FSL_ISBC_KEY_EXT
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
#define DCU_LAYER_MAX_NUM 16
config TARGET_M5485EVB
bool "Support M5485EVB"
+config TARGET_AMCORE
+ bool "Support AMCORE"
+
endchoice
source "board/BuS/eb_cpu5282/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/freescale/m548xevb/Kconfig"
+source "board/sysam/amcore/Kconfig"
endmenu
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
+# Support generic board on m68k
+__HAVE_ARCH_GENERIC_BOARD := y
+
PLATFORM_CPPFLAGS += -D__M68K__
PLATFORM_LDFLAGS += -n
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y = start.o
+obj-y = interrupts.o cpu.o speed.o cpu_init.o
+
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
+is5307:=$(shell grep CONFIG_M5307 $(cfg))
+
+ifneq (,$(findstring CONFIG_M5307,$(is5307)))
+PLATFORM_CPPFLAGS += -mcpu=5307
+endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ /* enable watchdog/reset, set timeout to 0 and wait */
+ out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI);
+
+ /* wait for watchdog reset */
+ for (;;)
+ ;
+
+ /* we don't return! */
+ return 0;
+}
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
+ strmhz(buf, CONFIG_SYS_CPU_CLK));
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_M5307)
+/*
+ * Simple mcf5307 chip select module init.
+ *
+ * Note: this chip has an issue reported in the device "errata":
+ * MCF5307ER Rev 4.2 reports @ section 35:
+ * Corrupted Return PC in Exception Stack Frame
+ * When processing an autovectored interrupt an error can occur that
+ * causes 0xFFFFFFFF to be written as the return PC value in the
+ * exception stack frame. The problem is caused by a conflict between
+ * an internal autovector access and a chip select mapped to the IACK
+ * address space (0xFFFFXXXX).
+ * Workaround:
+ * Set the C/I bit in the chip select mask register (CSMR) for the
+ * chip select that is mapped to 0xFFFFXXXX.
+ * This will prevent the chip select from asserting for IACK accesses.
+ */
+
+#define MCF5307_SP_ERR_FIX(cs_base, mask) \
+ do { \
+ if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
+ 0xffff0000) \
+ setbits_be32(&mask, CSMR_CI); \
+ } while (0)
+
+void init_csm(void)
+{
+ csm_t *csm = (csm_t *)(MMAP_CSM);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
+ defined(CONFIG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
+ defined(CONFIG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
+ defined(CONFIG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
+ defined(CONFIG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
+ defined(CONFIG_SYS_CS4_CTRL))
+ out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
+ out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
+ defined(CONFIG_SYS_CS5_CTRL))
+ out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
+ out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
+ defined(CONFIG_SYS_CS6_CTRL))
+ out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
+ out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
+ defined(CONFIG_SYS_CS7_CTRL))
+ out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
+ out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
+#endif
+}
+
+/*
+ * Set up the memory map and initialize registers
+ */
+void cpu_init_f(void)
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_8(&sim->sypcr, 0x00);
+ out_8(&sim->swivr, 0x0f);
+ out_8(&sim->swsr, 0x00);
+ out_8(&sim->mpark, 0x00);
+
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* timer 2 not masked */
+ out_be32(&icr->imr, 0xfffffbff);
+
+ out_8(&icr->icr0, 0x00); /* sw watchdog */
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x88); /* timer 2 */
+ out_8(&icr->icr3, 0x00); /* i2c */
+ out_8(&icr->icr4, 0x00); /* uart 0 */
+ out_8(&icr->icr5, 0x00); /* uart 1 */
+ out_8(&icr->icr6, 0x00); /* dma 0 */
+ out_8(&icr->icr7, 0x00); /* dma 1 */
+ out_8(&icr->icr8, 0x00); /* dma 2 */
+ out_8(&icr->icr9, 0x00); /* dma 3 */
+
+ /* Chipselect Init */
+ init_csm();
+
+ /* enable data/instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
+
+void uart_port_conf(void)
+{
+}
+
+void arch_preboot_os(void)
+{
+ /*
+ * OS can change interrupt offsets and are about to boot the OS so
+ * we need to make sure we disable all async interrupts.
+ */
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x00); /* timer 2 */
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int interrupt_init(void)
+{
+ enable_interrupts();
+
+ return 0;
+}
+
+void dtimer_intr_setup(void)
+{
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* clearing TIMER2 mask, so enabling the related interrupt */
+ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
+ /* set TIMER2 interrupt priority */
+ out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#if defined(CONFIG_M5307)
+ gd->bus_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+
+.macro SAVE_ALL
+ move.w #0x2700,%sr; /* disable intrs */
+ subl #60,%sp; /* space for 15 regs */
+ moveml %d0-%d7/%a0-%a6,%sp@
+.endm
+
+.macro RESTORE_ALL
+ moveml %sp@,%d0-%d7/%a0-%a6;
+ addl #60,%sp; /* space for 15 regs */
+ rte
+.endm
+
+/* If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+/* Flash offset is 0 until we setup CS0 */
+.long 0x00000000
+#if defined(CONFIG_M5307) && \
+ (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long _start - CONFIG_SYS_TEXT_BASE
+#else
+.long _START
+#endif
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+ .text
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr
+
+ /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.c %d0, %MBAR
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.c %d0, %RAMBAR
+
+ /* DS 4.8.2 (Cache Organization) invalidate and disable cache */
+ move.l #CF_CACR_CINVA, %d0
+ movec %d0, %CACR
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /*
+ * if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
+ movec %d0, %VBR
+#endif
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /*
+ * set stackpointer to internal sram end - 80
+ * (global data struct size + some bytes)
+ * get some stackspace for the first c-code,
+ */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* run low-level CPU init code (from flash) */
+ bsr cpu_init_f
+
+ /* run low-level board init code (from flash) */
+ bsr board_init_f
+
+ /* board_init_f() does not return */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l %a0, %d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
+ /* * fix got pointer register a5 */
+ move.l %a1,%a5
+
+ move.l %a0, %a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start, %d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
+ jsr (%a1)
+
+/*--------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ bra _fault
+
+ .globl _exc_handler
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*--------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
#define CONFIG_CF_V2
#endif
-#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
+ defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
#endif
#endif /* CONFIG_M5282 */
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
+ (CONFIG_SYS_INTR_BASE))->ipr)
+#define CONFIG_SYS_TMRINTR_NO (31)
+#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
+ MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5307 */
+
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+
+typedef struct sim {
+ u8 rsr;
+ u8 sypcr;
+ u8 swivr;
+ u8 swsr;
+ u16 par;
+ u8 irqpar;
+ u8 res1;
+ u8 pllcr;
+ u8 res2;
+ u16 res3;
+ u8 mpark;
+ u8 res4;
+ u16 res5;
+ u32 res6;
+} sim_t;
+
+typedef struct intctrl {
+ u32 ipr;
+ u32 imr;
+ u16 res7;
+ u8 res8;
+ u8 avr;
+ u8 icr0;
+ u8 icr1;
+ u8 icr2;
+ u8 icr3;
+ u8 icr4;
+ u8 icr5;
+ u8 icr6;
+ u8 icr7;
+ u8 icr8;
+ u8 icr9;
+ u16 res9;
+} intctrl_t;
+
+typedef struct csm {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} csm_t;
+
+typedef struct sdramctrl {
+ u16 dcr;
+ u16 res1;
+ u32 res2;
+ u32 dacr0;
+ u32 dmr0;
+ u32 dacr1;
+ u32 dmr1;
+} sdramctrl_t;
+
+typedef struct gpio {
+ u16 paddr;
+ u16 res1;
+ u16 padat;
+ u16 res2;
+} gpio_t;
+
+#endif /* __IMMAP_5307__ */
+
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef mcf5307_h
+#define mcf5307_h
+
+/*
+ * Size of internal RAM (RAMBAR)
+ */
+#define INT_RAM_SIZE 4096
+
+/* Bit definitions and macros for SYPCR */
+#define SYPCR_SWTAVAL 0x02
+#define SYPCR_SWTA 0x04
+#define SYPCR_SWT(x) ((x&0x3)<<3)
+#define SYPCR_SWP 0x20
+#define SYPCR_SWRI 0x40
+#define SYPCR_SWE 0x80
+
+/* Bit definitions and macros for CSMR */
+#define CSMR_V 0x01
+#define CSMR_UD 0x02
+#define CSMR_UC 0x04
+#define CSMR_SD 0x08
+#define CSMR_SC 0x10
+#define CSMR_CI 0x20
+#define CSMR_AM 0x40
+#define CSMR_WP 0x100
+
+/* Bit definitions and macros for DACR (SDRAM) */
+#define DACR_PM_CONTINUOUS 0x04
+#define DACR_IP_PRECHG_ALL 0x08
+#define DACR_PORT_SZ_32 0
+#define DACR_PORT_SZ_8 (1<<4)
+#define DACR_PORT_SZ_16 (2<<4)
+#define DACR_IMRS_INIT_CMD (1<<6)
+#define DACR_CMD_PIN(x) ((x&7)<<8)
+#define DACR_CASL(x) ((x&3)<<12)
+#define DACR_RE (1<<15)
+
+/* Bit definitions and macros for CSCR */
+#define CSCR_BSTW 0x08
+#define CSCR_BSTR 0x10
+#define CSCR_BEM 0x20
+#define CSCR_PS(x) ((x&0x3)<<6)
+#define CSCR_AA 0x100
+#define CSCR_WS ((x&0xf)<<10)
+
+/* Bit definitions for the ICR family of registers */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+#endif /* mcf5307_h */
+
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5272) || defined(CONFIG_M5307)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
* include/asm-ppc/u-boot.h
*/
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
#ifndef __ASSEMBLY__
typedef struct bd_info {
#endif /* __ASSEMBLY__ */
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
+ifndef CONFIG_SYS_GENERIC_BOARD
+obj-y += board.o
+endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
+ u32 dsp_mask = cpu_dsp_mask();
+#endif
+
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int dsp_cpu;
+ uint rcw_tmp1, rcw_tmp2;
+#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
else
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
+
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* As per CHASSIS2 architeture total 12 clusters are posible and
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
+ int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
+ u32 c_pll_sel = (in_be32
+ (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
+ & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+ cplx_pll += cc_group[dsp_cluster] - 1;
+ sys_info->freq_processor_dsp[dsp_cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+#endif
+
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
#endif
+#if defined(CONFIG_SYS_MAPLE)
+#define CPRI_CLK_SEL 0x1C000000
+#define CPRI_CLK_SHIFT 26
+#define CPRI_ALT_CLK_SEL 0x00007000
+#define CPRI_ALT_CLK_SHIFT 12
+
+ rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
+ rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
+ /* For MAPLE and CPRI frequency */
+ switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
+ break;
+ case 5:
+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
+ >> CPRI_ALT_CLK_SHIFT) == 6) {
+ sys_info->freq_maple =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
+ sys_info->freq_cpri =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
+ }
+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
+ >> CPRI_ALT_CLK_SHIFT) == 7) {
+ sys_info->freq_maple =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
+ sys_info->freq_cpri =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
+ }
+ break;
+ case 6:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE/CPRI clock select!\n");
+ }
+
+ /* For MAPLE ULB and eTVPE frequencies */
+#define ULB_CLK_SEL 0x00000038
+#define ULB_CLK_SHIFT 3
+#define ETVPE_CLK_SEL 0x00000007
+#define ETVPE_CLK_SHIFT 0
+
+ switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
+ break;
+ case 5:
+ sys_info->freq_maple_ulb = sys_info->freq_systembus;
+ break;
+ case 6:
+ sys_info->freq_maple_ulb =
+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple_ulb =
+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE ULB clock select!\n");
+ }
+
+ switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
+ break;
+ case 5:
+ sys_info->freq_maple_etvpe = sys_info->freq_systembus;
+ break;
+ case 6:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE eTVPE clock select!\n");
+ }
+
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
return mask;
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+u32 compute_dsp_cpumask(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int i = CONFIG_DSP_CLUSTER_START, count = 0;
+ u32 cluster, type, dsp_mask = 0;
+
+ do {
+ int j;
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = init_type(cluster, j);
+ if (type) {
+ if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC)
+ dsp_mask |= 1 << count;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return dsp_mask;
+}
+
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int count = 0, i = CONFIG_DSP_CLUSTER_START;
+ u32 cluster;
+
+ do {
+ int j;
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ if (init_type(cluster, j)) {
+ if (count == core)
+ return i;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return -1; /* cannot identify the cluster */
+}
+#endif
+
int fsl_qoriq_core_to_cluster(unsigned int core)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
return cpu->mask;
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+__weak u32 cpu_dsp_mask(void)
+{
+ ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ /* better to query feature reporting register than just assume 1 */
+ if (cpu == &cpu_type_unknown)
+ return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
+ MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
+
+ if (cpu->dsp_num_cores == 0)
+ return compute_dsp_cpumask();
+
+ return cpu->dsp_mask;
+}
+
/*
- * Return the number of cores on this SOC.
+ * Return the number of SC/DSP cores on this SOC.
+ */
+__weak int cpu_num_dspcores(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ /*
+ * Report # of cores in terms of the cpu_mask if we haven't
+ * figured out how many there are yet
+ */
+ if (cpu->dsp_num_cores == 0)
+ return hweight32(cpu_dsp_mask());
+
+ return cpu->dsp_num_cores;
+}
+#endif
+
+/*
+ * Return the number of PPC cores on this SOC.
*/
__weak int cpu_numcores(void)
{
return cpu->num_cores;
}
+
/*
* Check if the given core ID is valid
*
cpu->num_cores = cpu_numcores();
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ if (cpu->dsp_num_cores == 0) {
+ cpu->dsp_mask = cpu_dsp_mask();
+ cpu->dsp_num_cores = cpu_num_dspcores();
+ }
+#endif
return 0;
}
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SEC_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SEC_MON_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
+#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
+#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_MAPLE
+#define CONFIG_SYS_CPRI
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_CPRI_CLK 3
+#define CONFIG_SYS_ULB_CLK 4
+#define CONFIG_SYS_ETVPE_CLK 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS 4
+#define CONFIG_MAX_DSP_CPUS 12
+#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS 2
+#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#ifndef __FSL_SECURE_BOOT_H
#define __FSL_SECURE_BOOT_H
+#include <asm/config_mpc85xx.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
defined(CONFIG_PPC_T1023) || \
defined(CONFIG_PPC_T1024)
#define CONFIG_SYS_CPC_REINIT_F
+#define CONFIG_KEY_REVOCATION
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif
+#if defined(CONFIG_C29XPCIE)
+#define CONFIG_KEY_REVOCATION
+#endif
+
+#if defined(CONFIG_PPC_P3041) || \
+ defined(CONFIG_PPC_P4080) || \
+ defined(CONFIG_PPC_P5020) || \
+ defined(CONFIG_PPC_P5040) || \
+ defined(CONFIG_PPC_P2041)
+ #define CONFIG_FSL_TRUST_ARCH_v1
+#endif
+
+#if defined(CONFIG_FSL_CORENET)
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+#endif
+
#endif
#endif
#include <asm/fsl_i2c.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
+#include <fsl_sfp.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
#include <fsl_immap.h>
u8 res_f4[0xf0c];
};
#endif
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
-struct ccsr_sfp_regs {
- u32 ospr; /* 0x200 */
- u32 reserved0[14];
- u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
- u32 oem_uid; /* 0x9c OEM Unique ID */
- u8 reserved2[0x04];
- u32 ovpr; /* 0xA4 Intent To Secure */
- u8 reserved4[0x08];
- u32 fsl_uid; /* 0xB0 FSL Unique ID */
- u8 reserved5[0x04];
- u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
- u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
-};
-#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
-#define CONFIG_SYS_SNVS_OFFSET 0xE6000
+#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
#define CONFIG_SYS_SFP_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+#define CONFIG_SYS_SEC_MON_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
u32 soc_ver;
u32 num_cores;
u32 mask; /* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ u32 dsp_num_cores;
+ u32 dsp_mask; /* which DSP cpu(s) actually exist */
+#endif
};
struct cpu_type *identify_cpu(u32 ver);
int fixup_cpu(void);
int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \
#ifndef _BUR_COMMON_H_
#define _BUR_COMMON_H_
+#include <../../../drivers/video/am335x-fb.h>
+
+int load_lcdtiming(struct am335x_lcdpanel *panel);
+void br_summaryscreen(void);
void blink(u32 blinks, u32 intervall, u32 pin);
void pmicsetup(u32 mpupll);
void enable_uart0_pin_mux(void);
* SPDX-License-Identifier: GPL-2.0+
*
*/
-
+#include <version.h>
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
+#include <lcd.h>
+#include <fs.h>
+#ifdef CONFIG_USE_FDT
+ #include <fdt_support.h>
+#endif
#include "bur_common.h"
+#include "../../../drivers/video/am335x-fb.h"
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USE_FDT
+ #define FDTPROP(a, b, c) fdt_getprop_u32_default((void *)a, b, c, ~0UL)
+ #define PATHTIM "/panel/display-timings/default"
+ #define PATHINF "/panel/panel-info"
+#endif
/* --------------------------------------------------------------------------*/
+#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
+ !defined(CONFIG_SPL_BUILD)
+int load_lcdtiming(struct am335x_lcdpanel *panel)
+{
+ struct am335x_lcdpanel pnltmp;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ u32 dtbprop;
+
+ if (dtbaddr == ~0UL) {
+ puts("load_lcdtiming: failed to get 'dtbaddr' from env!\n");
+ return -1;
+ }
+ memcpy(&pnltmp, (void *)panel, sizeof(struct am335x_lcdpanel));
+
+ pnltmp.hactive = FDTPROP(dtbaddr, PATHTIM, "hactive");
+ pnltmp.vactive = FDTPROP(dtbaddr, PATHTIM, "vactive");
+ pnltmp.bpp = FDTPROP(dtbaddr, PATHINF, "bpp");
+ pnltmp.hfp = FDTPROP(dtbaddr, PATHTIM, "hfront-porch");
+ pnltmp.hbp = FDTPROP(dtbaddr, PATHTIM, "hback-porch");
+ pnltmp.hsw = FDTPROP(dtbaddr, PATHTIM, "hsync-len");
+ pnltmp.vfp = FDTPROP(dtbaddr, PATHTIM, "vfront-porch");
+ pnltmp.vbp = FDTPROP(dtbaddr, PATHTIM, "vback-porch");
+ pnltmp.vsw = FDTPROP(dtbaddr, PATHTIM, "vsync-len");
+ pnltmp.pup_delay = FDTPROP(dtbaddr, PATHTIM, "pupdelay");
+ pnltmp.pon_delay = FDTPROP(dtbaddr, PATHTIM, "pondelay");
+
+ /* calc. proper clk-divisor */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "clock-frequency");
+ if (dtbprop != ~0UL)
+ pnltmp.pxl_clk_div = 192000000 / dtbprop;
+ else
+ pnltmp.pxl_clk_div = ~0UL;
+
+ /* check polarity of control-signals */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "hsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= HSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "vsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= VSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-ctrl");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_CONTROL;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-edge");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_RISEFALL;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "pixelclk-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= PXCLK_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "de-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= DE_INVERT;
+#else
+ pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL);
+ pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL);
+ pnltmp.bpp = getenv_ulong("ds1_bpp", 10, ~0UL);
+ pnltmp.hfp = getenv_ulong("ds1_hfp", 10, ~0UL);
+ pnltmp.hbp = getenv_ulong("ds1_hbp", 10, ~0UL);
+ pnltmp.hsw = getenv_ulong("ds1_hsw", 10, ~0UL);
+ pnltmp.vfp = getenv_ulong("ds1_vfp", 10, ~0UL);
+ pnltmp.vbp = getenv_ulong("ds1_vbp", 10, ~0UL);
+ pnltmp.vsw = getenv_ulong("ds1_vsw", 10, ~0UL);
+ pnltmp.pxl_clk_div = getenv_ulong("ds1_pxlclkdiv", 10, ~0UL);
+ pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL);
+ pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL);
+ pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL);
+#endif
+ if (
+ ~0UL == (pnltmp.hactive) ||
+ ~0UL == (pnltmp.vactive) ||
+ ~0UL == (pnltmp.bpp) ||
+ ~0UL == (pnltmp.hfp) ||
+ ~0UL == (pnltmp.hbp) ||
+ ~0UL == (pnltmp.hsw) ||
+ ~0UL == (pnltmp.vfp) ||
+ ~0UL == (pnltmp.vbp) ||
+ ~0UL == (pnltmp.vsw) ||
+ ~0UL == (pnltmp.pxl_clk_div) ||
+ ~0UL == (pnltmp.pol) ||
+ ~0UL == (pnltmp.pup_delay) ||
+ ~0UL == (pnltmp.pon_delay)
+ ) {
+ puts("lcd-settings in env/dtb incomplete!\n");
+ printf("display-timings:\n"
+ "================\n"
+ "hactive: %d\n"
+ "vactive: %d\n"
+ "bpp : %d\n"
+ "hfp : %d\n"
+ "hbp : %d\n"
+ "hsw : %d\n"
+ "vfp : %d\n"
+ "vbp : %d\n"
+ "vsw : %d\n"
+ "pxlclk : %d\n"
+ "pol : 0x%08x\n"
+ "pondly : %d\n",
+ pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
+ pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
+ pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
+ pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay);
+
+ return -1;
+ }
+ debug("lcd-settings in env complete, taking over.\n");
+ memcpy((void *)panel,
+ (void *)&pnltmp,
+ sizeof(struct am335x_lcdpanel));
+
+ return 0;
+}
+
+#ifdef CONFIG_USE_FDT
+static int load_devicetree(void)
+{
+ char *dtbname = getenv("dtb");
+ char *dtbdev = getenv("dtbdev");
+ char *dtppart = getenv("dtbpart");
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ loff_t dtbsize;
+
+ if (!dtbdev || !dtbdev) {
+ puts("load_devicetree: <dtbdev>/<dtbpart> missing.\n");
+ return -1;
+ }
+
+ if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) {
+ puts("load_devicetree: set_blk_dev failed.\n");
+ return -1;
+ }
+ if (dtbname && dtbaddr != ~0UL) {
+ if (fs_read(dtbname, dtbaddr, 0, 0, &dtbsize) == 0) {
+ gd->fdt_blob = (void *)dtbaddr;
+ gd->fdt_size = dtbsize;
+ debug("loaded %d bytes of dtb onto 0x%08x\n",
+ (u32)dtbsize, dtbaddr);
+ return dtbsize;
+ }
+ puts("load_devicetree: load dtb failed,file does not exist!\n");
+ }
+
+ puts("load_devicetree: <dtb>/<dtbaddr> missing!\n");
+ return -1;
+}
+
+static const char *dtbmacaddr(u32 ifno)
+{
+ int node, len;
+ char enet[16];
+ const char *mac;
+ const char *path;
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("dtbmacaddr: failed to get 'dtbaddr' from env!\n");
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, "/aliases");
+ if (node < 0)
+ return NULL;
+
+ sprintf(enet, "ethernet%d", ifno);
+ path = fdt_getprop((void *)dtbaddr, node, enet, NULL);
+ if (!path) {
+ printf("no alias for %s\n", enet);
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, path);
+ mac = fdt_getprop((void *)dtbaddr, node, "mac-address", &len);
+ if (mac && is_valid_ether_addr((u8 *)mac))
+ return mac;
+
+ return NULL;
+}
+
+static void br_summaryscreen_printdtb(char *prefix,
+ char *name,
+ char *suffix)
+{
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ char buf[32] = { 0 };
+ const char *nodep = buf;
+ char *mac = 0;
+ int nodeoffset;
+ int len;
+
+ if (dtbaddr == ~0UL) {
+ puts("br_summaryscreen: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+
+ if (strcmp(name, "brmac1") == 0) {
+ mac = (char *)dtbmacaddr(0);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else if (strcmp(name, "brmac2") == 0) {
+ mac = (char *)dtbmacaddr(1);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else {
+ nodeoffset = fdt_path_offset((void *)dtbaddr,
+ "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("no 'factory-settings' in dtb!\n");
+ return;
+ }
+ nodep = fdt_getprop((void *)dtbaddr, nodeoffset, name, &len);
+ }
+ if (nodep && strlen(nodep) > 1)
+ lcd_printf("%s %s %s", prefix, nodep, suffix);
+ else
+ lcd_printf("\n");
+}
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(blob, "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("set bootloader version 'factory-settings' not in dtb!\n");
+ return -1;
+ }
+ if (fdt_setprop(blob, nodeoffset, "bl-version",
+ PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
+ puts("set bootloader version 'bl-version' prop. not in dtb!\n");
+ return -1;
+ }
+ return 0;
+}
+#else
+
+static void br_summaryscreen_printenv(char *prefix,
+ char *name, char *altname,
+ char *suffix)
+{
+ char *envval = getenv(name);
+ if (0 != envval) {
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else if (0 != altname) {
+ envval = getenv(altname);
+ if (0 != envval)
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else {
+ lcd_printf("\n");
+ }
+}
+#endif
+void br_summaryscreen(void)
+{
+#ifdef CONFIG_USE_FDT
+ br_summaryscreen_printdtb(" - B&R -", "order-no", "-\n");
+ br_summaryscreen_printdtb(" Serial/Rev :", "serial-no", " /");
+ br_summaryscreen_printdtb(" ", "hw-revision", "\n");
+ br_summaryscreen_printdtb(" MAC (IF1) :", "brmac1", "\n");
+ br_summaryscreen_printdtb(" MAC (IF2) :", "brmac2", "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#else
+ br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
+ br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
+ br_summaryscreen_printenv(" MAC (IF1) :", "br_mac1", "ethaddr", "\n");
+ br_summaryscreen_printenv(" MAC (IF2) :", "br_mac2", 0, "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#endif
+}
+
+void lcdpower(int on)
+{
+ u32 pin, swval, i;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ pin = FDTPROP(dtbaddr, PATHINF, "pwrpin");
+#else
+ pin = getenv_ulong("ds1_pwr", 16, ~0UL);
+#endif
+ if (pin == ~0UL) {
+ puts("no pwrpin in dtb/env, cannot powerup display!\n");
+ return;
+ }
+
+ for (i = 0; i < 3; i++) {
+ if (pin != 0) {
+ swval = pin & 0x80 ? 0 : 1;
+ if (on)
+ gpio_direction_output(pin & 0x7F, swval);
+ else
+ gpio_direction_output(pin & 0x7F, !swval);
+
+ debug("switched pin %d to %d\n", pin & 0x7F, swval);
+ }
+ pin >>= 8;
+ }
+}
+
+vidinfo_t panel_info = {
+ .vl_col = 1366, /*
+ * give full resolution for allocating enough
+ * memory
+ */
+ .vl_row = 768,
+ .vl_bpix = 5,
+ .priv = 0
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct am335x_lcdpanel lcd_panel;
+#ifdef CONFIG_USE_FDT
+ /* TODO: is there a better place to load the dtb ? */
+ load_devicetree();
+#endif
+ memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
+ if (load_lcdtiming(&lcd_panel) != 0)
+ return;
+
+ lcd_panel.panel_power_ctrl = &lcdpower;
+
+ if (0 != am335xfb_init(&lcd_panel))
+ printf("ERROR: failed to initialize video!");
+ /*
+ * modifiy panel info to 'real' resolution, to operate correct with
+ * lcd-framework.
+ */
+ panel_info.vl_col = lcd_panel.hactive;
+ panel_info.vl_row = lcd_panel.vactive;
+
+ lcd_set_flush_dcache(1);
+}
+
+void lcd_enable(void)
+{
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ unsigned int driver = FDTPROP(dtbaddr, PATHINF, "brightdrv");
+ unsigned int bright = FDTPROP(dtbaddr, PATHINF, "brightdef");
+ unsigned int pwmfrq = FDTPROP(dtbaddr, PATHINF, "brightfdim");
+#else
+ unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL);
+ unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50);
+ unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
+#endif
+ unsigned int tmp;
+ struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+
+ bright = bright != ~0UL ? bright : 50;
+
+ switch (driver) {
+ case 0: /* PMIC LED-Driver */
+ /* brightness level */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, bright, 0xFF);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x0A, 0xFF);
+ break;
+ case 1: /* PWM using timer6 */
+ if (pwmfrq != ~0UL) {
+ timerhw->tiocp_cfg = TCFG_RESET;
+ udelay(10);
+ while (timerhw->tiocp_cfg & TCFG_RESET)
+ ;
+ tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */
+ timerhw->tldr = tmp;
+ timerhw->tcrr = tmp;
+ tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
+ timerhw->tmar = tmp;
+ timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
+ TCLR_CE | TCLR_AR | TCLR_ST);
+ } else {
+ puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
+ }
+ break;
+ default:
+ puts("no suitable backlightdriver in env/dtb!\n");
+ break;
+ }
+ br_summaryscreen();
+}
+#elif CONFIG_SPL_BUILD
+#else
+#error "LCD-support with a suitable FB-Driver is mandatory !"
+#endif /* CONFIG_LCD */
+
void blink(u32 blinks, u32 intervall, u32 pin)
{
gpio_direction_output(pin, 0);
gpio_set_value(pin, 0);
}
+
#ifdef CONFIG_SPL_BUILD
void pmicsetup(u32 mpupll)
{
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+ /* Set PWR_EN bit in Status Register */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
}
void set_uart_mux_conf(void)
int board_eth_init(bd_t *bis)
{
int rv = 0;
- uint8_t mac_addr[6];
+ char mac_addr[6];
+ const char *mac = 0;
uint32_t mac_hi, mac_lo;
-
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
-
- if (is_valid_ether_addr(mac_addr)) {
- printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
- mac_addr[0], mac_addr[1], mac_addr[2],
- mac_addr[3], mac_addr[4], mac_addr[5]
- );
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT)
+ printf("<ethaddr> not set. trying DTB ... ");
+ mac = dtbmacaddr(0);
+ #endif
+ if (!mac) {
+ printf("<ethaddr> not set. validating E-fuse MAC ... ");
+ if (is_valid_ether_addr((const u8 *)mac_addr))
+ mac = (const char *)mac_addr;
+ }
+
+ if (mac) {
+ printf("using: %pM on ", mac);
+ eth_setenv_enetaddr("ethaddr", (const u8 *)mac);
}
}
writel(MII_MODE_ENABLE, &cdev->miisel);
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
-#define KEY (0+4)
-#define LCD_PWR (0+5)
-#define PUSH_KEY (0+31)
-#define USB2SD_NRST (32+29)
-#define USB2SD_PWR (96+13)
+#define ESC_KEY (0+19)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
/* -------------------------------------------------------------------------*/
/* -- PSOC Resetcontroller Register defines -- */
/* -- defines for RSTCTRL_CTRLREG -- */
#define RSTCTRL_FORCE_PWR_NEN 0x0404
+#define RSTCTRL_CAN_STB 0x4040
+
+#define VXWORKS_BOOTLINE 0x80001100
+#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
+#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
&cmper->epwmss0clkctrl,
&cmper->epwmss1clkctrl,
&cmper->epwmss2clkctrl,
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
-
+ /* setup LCD-Pixel Clock */
+ writel(0x2, CM_DPLL + 0x34);
/* power-OFF LCD-Display */
gpio_direction_output(LCD_PWR, 0);
/* power-ON 3V3 via Resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- buf = RSTCTRL_FORCE_PWR_NEN;
+ buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
(uint8_t *)&buf, sizeof(buf));
i2c_set_bus_speed(oldspeed);
puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
}
-#if defined(CONFIG_AM335X_USB0)
- /* power on USB2SD Controller */
- gpio_direction_output(USB2SD_PWR, 1);
- mdelay(1);
- /* give a reset Pulse to USB2SD Controller */
- gpio_direction_output(USB2SD_NRST, 0);
- mdelay(1);
- gpio_set_value(USB2SD_NRST, 1);
-#endif
pmicsetup(0);
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- const unsigned int ton = 250;
const unsigned int toff = 1000;
unsigned int cnt = 3;
unsigned short buf = 0xAAAA;
+ unsigned char scratchreg = 0;
unsigned int oldspeed;
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+ /* try to read out some boot-instruction from resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+ i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ &scratchreg, sizeof(scratchreg));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
- if (gpio_get_value(KEY)) {
+ if (gpio_get_value(ESC_KEY)) {
do {
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
- mdelay(ton);
- /* turn off light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ lcd_position_cursor(1, 8);
+ switch (cnt) {
+ case 3:
+ lcd_puts(
+ "release ESC-KEY to enter SERVICE-mode.");
+ break;
+ case 2:
+ lcd_puts(
+ "release ESC-KEY to enter DIAGNOSE-mode.");
+ break;
+ case 1:
+ lcd_puts(
+ "release ESC-KEY to enter BOOT-mode. ");
+ break;
+ }
mdelay(toff);
cnt--;
- if (!gpio_get_value(KEY) &&
+ if (!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && 2 == cnt) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
+ cnt = 4;
+ break;
+ } else if (!gpio_get_value(ESC_KEY) &&
gpio_get_value(PUSH_KEY) && 1 == cnt) {
- puts("updating from USB ...\n");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "updating U-BOOT from USB ... ");
setenv("bootcmd", "run usbupdate");
+ cnt = 4;
+ break;
+ } else if ((!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0) ||
+ (gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0)) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
break;
- } else if (!gpio_get_value(KEY)) {
+ } else if (!gpio_get_value(ESC_KEY)) {
break;
}
} while (cnt);
+ } else if (scratchreg == 0xCC) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting vxworks from network ... ");
+ setenv("bootcmd", "run netboot");
+ cnt = 4;
+ } else if (scratchreg == 0xCD) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
+ } else if (scratchreg == 0xCE) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting AR from eMMC ... ");
+ setenv("bootcmd", "run mmcboot");
+ cnt = 4;
}
+ lcd_position_cursor(1, 8);
switch (cnt) {
case 0:
- puts("3 blinks ... entering BOOT mode.\n");
+ lcd_puts("entering BOOT-mode. ");
+ setenv("bootcmd", "run defaultAR");
buf = 0x0000;
break;
case 1:
- puts("2 blinks ... entering DIAGNOSE mode.\n");
+ lcd_puts("entering DIAGNOSE-mode. ");
buf = 0x0F0F;
break;
case 2:
- puts("1 blinks ... entering SERVICE mode.\n");
+ lcd_puts("entering SERVICE mode. ");
buf = 0xB4B4;
break;
case 3:
- puts("0 blinks ... entering RUN mode.\n");
+ lcd_puts("loading OS... ");
buf = 0x0404;
break;
}
- mdelay(ton);
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
/* write bootinfo into scratchregister of resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
} else {
puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
}
+ /* setup vxworks bootline */
+ char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
+
+ /* setup default IP, in case if there is nothing in environment */
+ if (!getenv("ipaddr")) {
+ setenv("ipaddr", "192.168.60.1");
+ setenv("netmask", "255.255.255.0");
+ setenv("serverip", "192.168.60.254");
+ setenv("gatewayip", "192.168.60.254");
+ puts("net: had no IP! made default setup.\n");
+ }
+
+ sprintf(vxworksbootline,
+ "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
+ DEFAULT_BOOTLINE,
+ getenv("serverip"),
+ getenv("ipaddr"), getenv("netmask"),
+ getenv("gatewayip"),
+ VXWORKS_USER,
+ (unsigned int) gd->fb_base-0x20,
+ (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
+ (u32)getenv_ulong("vx_romfsbase", 16, 0),
+ (u32)getenv_ulong("vx_romfssize", 16, 0));
+
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
* expect that vectors are there, original u-boot moves them to _start
#include <asm/io.h>
#include <i2c.h>
-static struct module_pin_mux usb0_pin_mux[] = {
- {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
- /* USB0 DrvBus Receiver disable (from romcode 0x20) */
- {OFFSET(usb0_drvvbus), (MODE(0))},
- /* USB1 DrvBus as GPIO due to HW-Workaround */
- {OFFSET(usb1_drvvbus), (MODE(7))},
- {-1},
-};
-static struct module_pin_mux spi1_pin_mux[] = {
+static struct module_pin_mux spi0_pin_mux[] = {
/* SPI1_SCLK */
- {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
- {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
- {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
- {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ /* SPI1_CS1 */
+ {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
};
static struct module_pin_mux gpios[] = {
- /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
- {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
- /* GPIO0_4 (SPI D1) - TA602 */
- {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
- {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
/* GPIO0_7 (PWW0 OUT) - CAN TERM */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
- {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
- /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
- {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_19 (DMA_INTR0) - TA602 */
+ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
/* GPIO0_30 (GPMC_WAIT0) - TA601 */
{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO1_29 (gpmc_csn0) - MMC nRST */
+ {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_4 (GPMC_nWE) - TST_BAST */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+ {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(usb0_pin_mux);
- configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
/* -- defines for GPIO -- */
-#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
#define REPSWITCH (0+20) /* GPIO0_20 */
-
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
int spl_start_uboot(void)
{
if (0 == gpio_get_value(REPSWITCH)) {
- blink(5, 125, ETHLED_ORANGE);
mdelay(1000);
printf("SPL: entering u-boot instead kernel image.\n");
return 1;
void am33xx_spl_board_init(void)
{
- pmicsetup(1000);
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+ /*
+ * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+ * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+ * the source of timer6 clk to CLK_M_OSC
+ */
+ writel(0x01, &cmdpll->clktimer6clk);
+
+ /* enable additional clocks of modules which are accessed later */
+ u32 *const clk_domains[] = {
+ &cmper->lcdcclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_tsspecific[] = {
+ &cmper->lcdclkctrl,
+ &cmper->timer5clkctrl,
+ &cmper->timer6clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+ /* setup LCD-Pixel Clock */
+ writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
+
+ pmicsetup(0);
}
const struct dpll_params *get_dpll_ddr_params(void)
/* Basic board specific setup. Pinmux has been handled already. */
int board_init(void)
{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
gpmc_init();
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- gpio_direction_output(ETHLED_ORANGE, 0);
-
if (0 == gpio_get_value(REPSWITCH)) {
- printf("\n\n\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
- "!!!!!!! recovery switch activated !!!!!!!\n"
- "!!!!!!! running usbupdate !!!!!!!\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
- setenv("bootcmd", "sleep 2; run netupdate;");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
}
-
- printf("turning on display power+backlight ... ");
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
- 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
- 0x62, TPS65217_MASK_ALL_BITS); /* 100% */
- printf("ok.\n");
-
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
+static struct module_pin_mux uart1_pin_mux[] = {
+ /* UART0_RXD */
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
- /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
- {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
+ /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
+ {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-
+#ifndef CONFIG_NAND
+ /* GPIO2_3 - NAND_OE */
+ {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_4 - NAND_WEN */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_5 - NAND_BE_CLE */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
{-1},
};
#endif
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
configure_module_pin_mux(gpIOs);
}
default "socfpga_cyclone5"
endif
+
+if TARGET_SOCFPGA_ARRIA5
+
+config SYS_BOARD
+ default "socfpga"
+
+config SYS_VENDOR
+ default "altera"
+
+config SYS_SOC
+ default "socfpga"
+
+config SYS_CONFIG_NAME
+ default "socfpga_arria5"
+
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := socfpga_cyclone5.o
+obj-y := socfpga.o
obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
#include <iocsr_config.h>
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
0x0000001F,
0x00004100,
};
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000060,
+ 0x00018060,
+ 0x06018060,
+ 0x00004000,
+ 0x0C0300C0,
+ 0x0C030000,
+ 0x00000030,
+ 0x00000000,
+ 0x00000000,
+ 0x00002000,
+ 0x00000000,
+ 0x00000000,
+ 0x06000000,
+ 0x00006018,
+ 0x01806018,
+ 0x00001000,
+ 0x0000C030,
+ 0x04000000,
+ 0x03000000,
+ 0x0000300C,
+ 0x00000000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00001806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x00100000,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x10000000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00002000,
+ 0x00000400,
+ 0x0000300C,
+ 0x01000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000C03,
+ 0x00000200,
+ 0x00001806,
+ 0x00800000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000800,
+ 0x00000100,
+ 0x00001000,
+ 0x00400000,
+ 0xC0300000,
+ 0x00000000,
+ 0x00000400,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x18060180,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00002000,
+ 0x10038060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000020,
+ 0x01806018,
+ 0x00001000,
+ 0x00010000,
+ 0x04000000,
+ 0x03000000,
+ 0x0000801C,
+ 0x00004000,
+ 0x00000800,
+ 0x01806018,
+ 0x02000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00002000,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+ 0x00601806,
+ 0x80601800,
+ 0x80600001,
+ 0x80000601,
+ 0x00180601,
+ 0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C820D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00481800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0xFFD602AF,
+ 0x86FFFFFF,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
+#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
#ifndef _PRELOADER_IOCSR_CONFIG_H_
#define _PRELOADER_IOCSR_CONFIG_H_
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#endif
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
#include "pinmux_config.h"
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
/* pin mux configuration data */
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
- 0, /* EMACIO0 - Unused */
- 2, /* EMACIO1 - USB */
- 2, /* EMACIO2 - USB */
- 2, /* EMACIO3 - USB */
- 2, /* EMACIO4 - USB */
- 2, /* EMACIO5 - USB */
- 2, /* EMACIO6 - USB */
- 2, /* EMACIO7 - USB */
- 2, /* EMACIO8 - USB */
- 0, /* EMACIO9 - Unused */
- 2, /* EMACIO10 - USB */
- 2, /* EMACIO11 - USB */
- 2, /* EMACIO12 - USB */
- 2, /* EMACIO13 - USB */
- 0, /* EMACIO14 - N/A */
- 0, /* EMACIO15 - N/A */
- 0, /* EMACIO16 - N/A */
- 0, /* EMACIO17 - N/A */
- 0, /* EMACIO18 - N/A */
- 0, /* EMACIO19 - N/A */
- 3, /* FLASHIO0 - SDMMC */
- 3, /* FLASHIO1 - SDMMC */
- 3, /* FLASHIO2 - SDMMC */
- 3, /* FLASHIO3 - SDMMC */
- 0, /* FLASHIO4 - SDMMC */
- 0, /* FLASHIO5 - SDMMC */
- 0, /* FLASHIO6 - SDMMC */
- 0, /* FLASHIO7 - SDMMC */
- 0, /* FLASHIO8 - SDMMC */
- 3, /* FLASHIO9 - SDMMC */
- 3, /* FLASHIO10 - SDMMC */
- 3, /* FLASHIO11 - SDMMC */
- 3, /* GENERALIO0 - TRACE */
- 3, /* GENERALIO1 - TRACE */
- 3, /* GENERALIO2 - TRACE */
- 3, /* GENERALIO3 - TRACE */
- 3, /* GENERALIO4 - TRACE */
- 3, /* GENERALIO5 - TRACE */
- 3, /* GENERALIO6 - TRACE */
- 3, /* GENERALIO7 - TRACE */
- 3, /* GENERALIO8 - TRACE */
- 3, /* GENERALIO9 - SPIM0 */
- 3, /* GENERALIO10 - SPIM0 */
- 3, /* GENERALIO11 - SPIM0 */
- 3, /* GENERALIO12 - SPIM0 */
- 2, /* GENERALIO13 - CAN0 */
- 2, /* GENERALIO14 - CAN0 */
- 3, /* GENERALIO15 - I2C0 */
- 3, /* GENERALIO16 - I2C0 */
- 2, /* GENERALIO17 - UART0 */
- 2, /* GENERALIO18 - UART0 */
- 0, /* GENERALIO19 - N/A */
- 0, /* GENERALIO20 - N/A */
- 0, /* GENERALIO21 - N/A */
- 0, /* GENERALIO22 - N/A */
- 0, /* GENERALIO23 - N/A */
- 0, /* GENERALIO24 - N/A */
- 0, /* GENERALIO25 - N/A */
- 0, /* GENERALIO26 - N/A */
- 0, /* GENERALIO27 - N/A */
- 0, /* GENERALIO28 - N/A */
- 0, /* GENERALIO29 - N/A */
- 0, /* GENERALIO30 - N/A */
- 0, /* GENERALIO31 - N/A */
- 2, /* MIXED1IO0 - EMAC */
- 2, /* MIXED1IO1 - EMAC */
- 2, /* MIXED1IO2 - EMAC */
- 2, /* MIXED1IO3 - EMAC */
- 2, /* MIXED1IO4 - EMAC */
- 2, /* MIXED1IO5 - EMAC */
- 2, /* MIXED1IO6 - EMAC */
- 2, /* MIXED1IO7 - EMAC */
- 2, /* MIXED1IO8 - EMAC */
- 2, /* MIXED1IO9 - EMAC */
- 2, /* MIXED1IO10 - EMAC */
- 2, /* MIXED1IO11 - EMAC */
- 2, /* MIXED1IO12 - EMAC */
- 2, /* MIXED1IO13 - EMAC */
- 0, /* MIXED1IO14 - Unused */
- 3, /* MIXED1IO15 - QSPI */
- 3, /* MIXED1IO16 - QSPI */
- 3, /* MIXED1IO17 - QSPI */
- 3, /* MIXED1IO18 - QSPI */
- 3, /* MIXED1IO19 - QSPI */
- 3, /* MIXED1IO20 - QSPI */
- 0, /* MIXED1IO21 - GPIO */
- 0, /* MIXED2IO0 - N/A */
- 0, /* MIXED2IO1 - N/A */
- 0, /* MIXED2IO2 - N/A */
- 0, /* MIXED2IO3 - N/A */
- 0, /* MIXED2IO4 - N/A */
- 0, /* MIXED2IO5 - N/A */
- 0, /* MIXED2IO6 - N/A */
- 0, /* MIXED2IO7 - N/A */
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 3, /* FLASHIO4 */
+ 3, /* FLASHIO5 */
+ 3, /* FLASHIO6 */
+ 3, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 1, /* GENERALIO5 */
+ 1, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 1, /* MIXED1IO1 */
+ 1, /* MIXED1IO2 */
+ 1, /* MIXED1IO3 */
+ 1, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 1, /* MIXED1IO8 */
+ 1, /* MIXED1IO9 */
+ 1, /* MIXED1IO10 */
+ 1, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 1, /* MIXED1IO15 */
+ 1, /* MIXED1IO16 */
+ 1, /* MIXED1IO17 */
+ 1, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
0, /* GPLINMUX48 */
0, /* GPLINMUX49 */
0, /* GPLINMUX50 */
0, /* USB0USEFPGA */
0 /* SPIM0USEFPGA */
};
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 3, /* EMACIO14 */
+ 3, /* EMACIO15 */
+ 3, /* EMACIO16 */
+ 3, /* EMACIO17 */
+ 3, /* EMACIO18 */
+ 3, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 3, /* GENERALIO0 */
+ 3, /* GENERALIO1 */
+ 3, /* GENERALIO2 */
+ 3, /* GENERALIO3 */
+ 3, /* GENERALIO4 */
+ 3, /* GENERALIO5 */
+ 3, /* GENERALIO6 */
+ 3, /* GENERALIO7 */
+ 3, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 3, /* GENERALIO23 */
+ 3, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 0, /* MIXED1IO1 */
+ 0, /* MIXED1IO2 */
+ 0, /* MIXED1IO3 */
+ 0, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 0, /* MIXED1IO8 */
+ 0, /* MIXED1IO9 */
+ 0, /* MIXED1IO10 */
+ 0, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 3, /* MIXED2IO0 */
+ 3, /* MIXED2IO1 */
+ 3, /* MIXED2IO2 */
+ 3, /* MIXED2IO3 */
+ 3, /* MIXED2IO4 */
+ 3, /* MIXED2IO5 */
+ 3, /* MIXED2IO6 */
+ 3, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
* State of enabling for which IP connected out through the muxing.
* Value 1 mean the IP connection is muxed out
*/
-#define CONFIG_HPS_EMAC0 (0)
-#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_EMAC0 (1)
+#define CONFIG_HPS_EMAC1 (0)
#define CONFIG_HPS_USB0 (0)
#define CONFIG_HPS_USB1 (1)
#define CONFIG_HPS_NAND (0)
#define CONFIG_HPS_SDMMC (1)
-#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_QSPI (0)
#define CONFIG_HPS_UART0 (1)
#define CONFIG_HPS_UART1 (0)
-#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_TRACE (0)
#define CONFIG_HPS_I2C0 (1)
#define CONFIG_HPS_I2C1 (0)
#define CONFIG_HPS_I2C2 (0)
#define CONFIG_HPS_I2C3 (0)
-#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM0 (0)
#define CONFIG_HPS_SPIM1 (0)
#define CONFIG_HPS_SPIS0 (0)
#define CONFIG_HPS_SPIS1 (0)
#define CONFIG_HPS_CAN1 (0)
/* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
/* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS0 (0)
#define CONFIG_HPS_QSPI_CS1 (0)
#define CONFIG_HPS_QSPI_CS2 (0)
#define CONFIG_HPS_QSPI_CS3 (0)
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
*/
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
/* SDRAM PLL */
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
- * This if..else... is not required if generated by tools */
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
-#else
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
/*
* To tell where is the VCOs source:
/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
-#else
-#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
-#endif
+#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Print Board information
- */
-int checkboard(void)
-{
- puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
- return 0;
-}
-
-/*
- * Initialization function which happen at early stage of c code
- */
-int board_early_init_f(void)
-{
- return 0;
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
--- /dev/null
+if TARGET_BAV335X
+
+config SYS_BOARD
+ default "bav335x"
+
+config SYS_VENDOR
+ default "birdland"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "bav335x"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0 as for example the IDK
+ uses UART3 so enter 4 here.
+
+config BAV_VERSION
+ int "BAV335x Version (1=A, 2=B)"
+ range 1 2
+ help
+ The BAV335x has various version of the board. Rev.A (mostly obsolete)
+ used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY.
+ Overwrite this if you have an older Rev.A and want ethernet support.
+
+endif
--- /dev/null
+BAV335x BOARD
+M: Gilles Gameiro <gilles@gigadevices.com>
+S: Maintained
+F: include/configs/bav335x.h
+F: board/birdland/bav335x/Kconfig
+F: board/birdland/bav335x/Makefile
+F: board/birdland/bav335x/README
+F: board/birdland/bav335x/board.c
+F: board/birdland/bav335x/board.h
+F: board/birdland/bav335x/mux.c
+F: board/birdland/bav335x/u-boot.lds
+F: configs/birdland_bav335a_defconfig
+F: configs/birdland_bav335b_defconfig
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+Summary
+=======
+
+This document covers various features of the 'BAV335x' board build.
+For more information about this board, visit http://birdland.com/oem
+
+
+Hardware
+========
+
+The binary produced supports the bav335x Rev.A with 10/100 MB PHY
+and Rev.B (default) with GB ethernet PHY.
+If the BAV335x EEPROM is populated and programmed, the board will
+automatically detect the version and extract proper serial# and
+mac address from the EE.
+
+
+Customization
+=============
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+ errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings). Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+
+static __maybe_unused struct ctrl_dev *cdev =
+ (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct board_eeconfig *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
+ return -ENODEV;
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC) {
+ /* read the i2c eeprom again using only a 1 byte address */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC)
+ return -EINVAL;
+ }
+ return 0;
+}
+
+
+
+
+enum board_type get_board_type(bool debug)
+{
+ int ecode;
+ struct board_eeconfig header;
+
+ ecode = read_eeprom(&header);
+ if (ecode == 0) {
+ if (header.version[1] == 'A') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.A");
+ return BAV335A;
+ } else if (header.version[1] == 'B') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.B");
+ return BAV335B;
+ } else if (debug) {
+ puts("### Un-known board model in serial-EE\n");
+ }
+ } else if (debug) {
+ switch (ecode) {
+ case -ENODEV:
+ puts("### Board doesn't have a serial-EE\n");
+ break;
+ case -EINVAL:
+ puts("### Board serial-EE signature is incorrect.\n");
+ break;
+ default:
+ puts("### IO Error reading serial-EE.\n");
+ break;
+ }
+ }
+
+#if (CONFIG_BAV_VERSION == 1)
+ if (debug)
+ puts("### Selecting BAV335A as per config\n");
+ return BAV335A;
+#elif (CONFIG_BAV_VERSION == 2)
+ if (debug)
+ puts("### Selecting BAV335B as per config\n");
+ return BAV335B;
+#endif
+#if (NOT_DEFINED == 2)
+#error "SHOULD NEVER DISPLAY THIS"
+#endif
+
+ if (debug)
+ puts("### Defaulting to model BAV335x Rev.B\n");
+ return BAV335B;
+}
+
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr3_bav335x_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+
+static struct emif_regs ddr3_bav335x_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ /* debug print detect status */
+ (void)get_board_type(true);
+
+ /* Get the frequency */
+ /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /* Set the USB Current Limit */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("! tps65217_reg_write: could not set USB limit\n");
+
+ /* Set the Core Voltage (DCDC3) to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("! tps65217_reg_write: could not set Core Voltage\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set the MPU Voltage (DCDC2) */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2,
+ TPS65217_DCDC_VOLT_SEL_1325MV)) {
+ puts("! tps65217_reg_write: could not set MPU Voltage\n");
+ return;
+ }
+
+ /*
+ * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+ * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+ */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO3\n");
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO4\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr_bone_black;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+ enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+ enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+ enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+ enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+ enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+ enum board_type board;
+
+ board = get_board_type(false);
+ enable_board_pin_mux(board);
+}
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs_bonelt,
+ &ddr3_bav335x_data,
+ &ddr3_bav335x_cmd_ctrl_data,
+ &ddr3_bav335x_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "BAV335xB");
+ setenv("board_rev", "B"); /* Fix me, but why bother.. */
+#endif
+ return 0;
+}
+#endif
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+
+/*
+ * This function will:
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int ecode, rv, n;
+ uint8_t mac_addr[6];
+ struct board_eeconfig header;
+ __maybe_unused enum board_type board;
+
+ /* Default manufacturing address; used when no EE or invalid */
+ n = 0;
+ mac_addr[0] = 0;
+ mac_addr[1] = 0x20;
+ mac_addr[2] = 0x18;
+ mac_addr[3] = 0x1C;
+ mac_addr[4] = 0x00;
+ mac_addr[5] = 0x01;
+
+ ecode = read_eeprom(&header);
+ /* if we have a valid EE, get mac address from there */
+ if ((ecode == 0) &&
+ is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) {
+ memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
+ }
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+ board = get_board_type(false);
+
+ /* Rev.A uses 10/100 PHY in mii mode */
+ if (board == BAV335A) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+ }
+ /* Rev.B (default) uses GB PHY in rmii mode */
+ else {
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
+ = PHY_INTERFACE_MODE_RGMII;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+#endif
+
+ return n;
+}
+#endif
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Serial MagicE: AA 55 BA BE */
+#define BOARD_MAGIC 0xBEBA55AA
+enum board_type {UNKNOWN, BAV335A, BAV335B};
+
+
+/*
+ * The BAV335x may use a built-in read-only serial EEProm.
+ * The Evaluation board, disables the write-protect so the Serial-EE
+ * Can be programmed during manufacturing to store fields such as
+ * a board serial number, ethernet mac address and other user fields.
+ * Additionally, the Serial-EE can store the specific version of the
+ * board it runs on, and overwrite the defaults in _defconfig
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct board_eeconfig {
+ unsigned int magic;
+ char name[HDR_NAME_LEN]; /* BAV3354 */
+ char version[4]; /* 0B20 - Rev.B2 */
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+enum board_type get_board_type(bool verbose_debug_output);
+
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(enum board_type board);
+
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR 0x35
+#define CFG_REG 0x10
+
+
+void enable_board_pin_mux(enum board_type board)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+ if (board == BAV335A)
+ configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
+ else
+ configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
+
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+}
--- /dev/null
+/*
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/birdland/bav335x/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
obj-$(CONFIG_P5040DS) += p_corenet/
obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
+
+ifdef CONFIG_SECURE_BOOT
+obj-y += fsl_validate.o
+obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o
+endif
+
endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fsl_validate.h>
+
+static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ return fsl_secboot_validate(cmdtp, flag, argc, argv);
+}
+
+/***************************************************/
+static char esbc_validate_help_text[] =
+ "esbc_validate hdr_addr <hash_val> - Validates signature using\n"
+ " RSA verification\n"
+ " $hdr_addr Address of header of the image\n"
+ " to be validated.\n"
+ " $hash_val -Optional\n"
+ " It provides Hash of public/srk key to be\n"
+ " used to verify signature.\n";
+
+U_BOOT_CMD(
+ esbc_validate, 3, 0, do_esbc_validate,
+ "Validates signature on a given image using RSA verification",
+ esbc_validate_help_text
+);
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <fsl_sec.h>
+#include <command.h>
+#include <malloc.h>
+#include <dm/uclass.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <hash.h>
+#include <fsl_secboot_err.h>
+#ifndef CONFIG_MPC85xx
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#define SHA256_BITS 256
+#define SHA256_BYTES (256/8)
+#define SHA256_NIBBLES (256/4)
+#define NUM_HEX_CHARS (sizeof(ulong) * 2)
+
+/* This array contains DER value for SHA-256 */
+static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
+ 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
+ 0x04, 0x20
+ };
+
+static u8 hash_val[SHA256_BYTES];
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+
+void branch_to_self(void) __attribute__ ((noreturn));
+
+/*
+ * This function will put core in infinite loop.
+ * This will be called when the ESBC can not proceed further due
+ * to some unknown errors.
+ */
+void branch_to_self(void)
+{
+ printf("Core is in infinite loop due to errors.\n");
+self:
+ goto self;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 check_ie(struct fsl_secboot_img_priv *img)
+{
+ if (img->hdr.ie_flag)
+ return 1;
+
+ return 0;
+}
+
+/* This function returns the CSF Header Address of uboot
+ * For MPC85xx based platforms, the LAW mapping for NOR
+ * flash changes in uboot code. Hence the offset needs
+ * to be calculated and added to the new NOR flash base
+ * address
+ */
+#if defined(CONFIG_MPC85xx)
+int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+ u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+ ulong flash_addr, addr;
+ int found = 0;
+ int i = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ flash_addr = flash_info[i].start[0];
+ addr = flash_info[i].start[0] + csf_flash_offset;
+ if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
+ debug("Barker found on addr %lx\n", addr);
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ return -1;
+
+ *csf_addr = addr;
+ *flash_base_addr = flash_addr;
+
+ return 0;
+}
+#else
+/* For platforms like LS1020, correct flash address is present in
+ * the header. So the function reqturns flash base address as 0
+ */
+int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+
+ if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ return -1;
+
+ *csf_addr = csf_hdr_addr;
+ *flash_base_addr = 0;
+ return 0;
+}
+#endif
+
+static int get_ie_info_addr(ulong *ie_addr)
+{
+ struct fsl_secboot_img_hdr *hdr;
+ struct fsl_secboot_sg_table *sg_tbl;
+ ulong flash_base_addr, csf_addr;
+
+ if (get_csf_base_addr(&csf_addr, &flash_base_addr))
+ return -1;
+
+ hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+
+ /* For SoC's with Trust Architecture v1 with corenet bus
+ * the sg table field in CSF header has absolute address
+ * for sg table in memory. In other Trust Architecture,
+ * this field specifies the offset of sg table from the
+ * base address of CSF Header
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+ sg_tbl = (struct fsl_secboot_sg_table *)
+ (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
+#else
+ sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ (ulong)hdr->psgtable);
+#endif
+
+ /* IE Key Table is the first entry in the SG Table */
+#if defined(CONFIG_MPC85xx)
+ *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr;
+#else
+ *ie_addr = sg_tbl->src_addr;
+#endif
+
+ debug("IE Table address is %lx\n", *ie_addr);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+/* This function checks srk_table_flag in header and set/reset srk_flag.*/
+static u32 check_srk(struct fsl_secboot_img_priv *img)
+{
+ if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
+ return 1;
+
+ return 0;
+}
+
+/* This function returns ospr's key_revoc values.*/
+static u32 get_key_revoc(void)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+ OSPR_KEY_REVOC_SHIFT;
+}
+
+/* This function checks if selected key is revoked or not.*/
+static u32 is_key_revoked(u32 keynum, u32 rev_flag)
+{
+ if (keynum == UNREVOCABLE_KEY)
+ return 0;
+
+ if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag)
+ return 1;
+
+ return 0;
+}
+
+/* It validates srk_table key lengths.*/
+static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries)
+{
+ int i = 0;
+ for (i = 0; i < num_entries; i++) {
+ if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) ||
+ (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) ||
+ (tbl[i].key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
+ }
+ return 0;
+}
+#endif
+
+/* This function return length of public key.*/
+static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
+{
+ return img->key_len;
+}
+
+/*
+ * Handles the ESBC uboot client header verification failure.
+ * This function handles all the errors which might occur in the
+ * parsing and checking of ESBC uboot client header. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_header_verification_failure(void)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+
+ /* 29th bit of OSPR is ITS */
+ u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
+
+ /*
+ * Read the SEC_MON status register
+ * Read SSM_ST field
+ */
+ sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
+ if (its == 1)
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_SOFT_FAIL);
+ else
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_NON_SECURE);
+ }
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+}
+
+/*
+ * Handles the ESBC uboot client image verification failure.
+ * This function handles all the errors which might occur in the
+ * public key hash comparison and signature verification of
+ * ESBC uboot client image. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_image_verification_failure(void)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+
+ u32 its = sfp_in32(&sfp_regs->ospr) & ITS_MASK >> ITS_BIT;
+
+ /*
+ * Read the SEC_MON status register
+ * Read SSM_ST field
+ */
+ sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
+ if (its == 1) {
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_SOFT_FAIL);
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ } else {
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_NON_SECURE);
+ }
+ }
+}
+
+static void fsl_secboot_bootscript_parse_failure(void)
+{
+ fsl_secboot_header_verification_failure();
+}
+
+/*
+ * Handles the errors in esbc boot.
+ * This function handles all the errors which might occur in the
+ * esbc boot phase. It will call the appropriate api to log the
+ * errors and set the error bits in the SEC_MON.
+ */
+void fsl_secboot_handle_error(int error)
+{
+ const struct fsl_secboot_errcode *e;
+
+ for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
+ e++) {
+ if (e->errcode == error)
+ printf("ERROR :: %x :: %s\n", error, e->name);
+ }
+
+ switch (error) {
+ case ERROR_ESBC_CLIENT_HEADER_BARKER:
+ case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+#ifdef CONFIG_KEY_REVOCATION
+ case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ /*@fallthrough@*/
+ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN:
+ case ERROR_IE_TABLE_NOT_FOUND:
+#endif
+ fsl_secboot_header_verification_failure();
+ break;
+ case ERROR_ESBC_SEC_RESET:
+ case ERROR_ESBC_SEC_DEQ:
+ case ERROR_ESBC_SEC_ENQ:
+ case ERROR_ESBC_SEC_DEQ_TO:
+ case ERROR_ESBC_SEC_JOBQ_STATUS:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_EM:
+ fsl_secboot_image_verification_failure();
+ break;
+ case ERROR_ESBC_MISSING_BOOTM:
+ fsl_secboot_bootscript_parse_failure();
+ break;
+ case ERROR_ESBC_WRONG_CMD:
+ default:
+ branch_to_self();
+ break;
+ }
+}
+
+static void fsl_secblk_handle_error(int error)
+{
+ switch (error) {
+ case ERROR_ESBC_SEC_ENQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ_TO:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO);
+ break;
+ default:
+ printf("Job Queue Output status %x\n", error);
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS);
+ break;
+ }
+}
+
+/*
+ * Calculate hash of key obtained via offset present in ESBC uboot
+ * client hdr. This function calculates the hash of key which is obtained
+ * through offset present in ESBC uboot client header.
+ */
+static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int i, srk = 0;
+ int ret = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate hash of the esbc key */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ if (ret)
+ return ret;
+
+ /* Update hash for ESBC key */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ srk = 1;
+ }
+#endif
+ if (!srk)
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->key_len, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < SHA256_BYTES; i++)
+ img->img_key_hash[i] = hash_val[i];
+
+ return 0;
+}
+
+/*
+ * Calculate hash of ESBC hdr and ESBC. This function calculates the
+ * single hash of ESBC header and ESBC image. If SG flag is on, all
+ * SG entries are also hashed alongwith the complete SG table.
+ */
+static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int ret = 0;
+ int key_hash = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate the hash of the ESBC */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ /* Copy hash at destination buffer */
+ if (ret)
+ return ret;
+
+ /* Update hash for CSF Header */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
+ if (ret)
+ return ret;
+
+ /* Update the hash with that of srk table if srk flag is 1
+ * If IE Table is selected, key is not added in the hash
+ * If neither srk table nor IE key table available, add key
+ * from header in the hash calculation
+ */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+ key_hash = 1;
+ }
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_hash && check_ie(img))
+ key_hash = 1;
+#endif
+ if (!key_hash)
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->hdr.key_len, 0);
+ if (ret)
+ return ret;
+
+ /* Update hash for actual Image */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)img->hdr.pimg, img->hdr.img_size, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
+ * pointers for padding, DER value and hash. And finally, constructs EM'
+ * which includes hash of complete CSF header and ESBC image. If SG flag
+ * is on, hash of SG table and entries is also included.
+ */
+static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img)
+{
+ /*
+ * RSA PKCSv1.5 encoding format for encoded message is below
+ * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
+ * PS is Padding String
+ * DER is DER value for SHA-256
+ * Hash is SHA-256 hash
+ * *********************************************************
+ * representative points to first byte of EM initially and is
+ * filled with 0x0
+ * representative is incremented by 1 and second byte is filled
+ * with 0x1
+ * padding points to third byte of EM
+ * digest points to full length of EM - 32 bytes
+ * hash_id (DER value) points to 19 bytes before pDigest
+ * separator is one byte which separates padding and DER
+ */
+
+ size_t len;
+ u8 *representative;
+ u8 *padding, *digest;
+ u8 *hash_id, *separator;
+ int i;
+
+ len = (get_key_len(img) / 2) - 1;
+ representative = img->img_encoded_hash_second;
+ representative[0] = 0;
+ representative[1] = 1; /* block type 1 */
+
+ padding = &representative[2];
+ digest = &representative[1] + len - 32;
+ hash_id = digest - sizeof(hash_identifier);
+ separator = hash_id - 1;
+
+ /* fill padding area pointed by padding with 0xff */
+ memset(padding, 0xff, separator - padding);
+
+ /* fill byte pointed by separator */
+ *separator = 0;
+
+ /* fill SHA-256 DER value pointed by HashId */
+ memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
+
+ /* fill hash pointed by Digest */
+ for (i = 0; i < SHA256_BYTES; i++)
+ digest[i] = hash_val[i];
+}
+
+/*
+ * Reads and validates the ESBC client header.
+ * This function reads key and signature from the ESBC client header.
+ * If Scatter/Gather flag is on, lengths and offsets of images
+ * present as SG entries are also read. This function also checks
+ * whether the header is valid or not.
+ */
+static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
+{
+ char buf[20];
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)img->ehdrloc;
+ u8 *k, *s;
+#ifdef CONFIG_KEY_REVOCATION
+ u32 ret;
+ u32 key_num, key_revoc_flag, size;
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ struct ie_key_info *ie_info;
+ u32 ie_num, ie_revoc_flag, ie_key_len;
+#endif
+ int key_found = 0;
+
+ /* check barker code */
+ if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
+ return ERROR_ESBC_CLIENT_HEADER_BARKER;
+
+ sprintf(buf, "%p", hdr->pimg);
+ setenv("img_addr", buf);
+
+ if (!hdr->img_size)
+ return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+
+ /* Key checking*/
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+ key_num = hdr->len_kr.srk_sel;
+ if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+ size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+ memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+ ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk);
+
+ if (ret != 0)
+ return ret;
+
+ img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+ memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
+ img->key_len);
+
+ key_found = 1;
+ }
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_found && check_ie(img)) {
+ if (get_ie_info_addr(&img->ie_addr))
+ return ERROR_IE_TABLE_NOT_FOUND;
+ ie_info = (struct ie_key_info *)img->ie_addr;
+ if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+ ie_num = hdr->ie_key_sel;
+ if (ie_num == 0 || ie_num > ie_info->num_keys)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+ ie_revoc_flag = ie_info->key_revok;
+ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+ if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) ||
+ (ie_key_len == 2 * KEY_SIZE_BYTES / 2) ||
+ (ie_key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+ memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+ ie_key_len);
+
+ img->key_len = ie_key_len;
+ key_found = 1;
+ }
+#endif
+
+ if (key_found == 0) {
+ /* check key length */
+ if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) ||
+ (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) ||
+ (hdr->key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+ memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
+
+ img->key_len = hdr->key_len;
+
+ key_found = 1;
+ }
+
+ /* check signaure */
+ if (get_key_len(img) == 2 * hdr->sign_len) {
+ /* check signature length */
+ if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) ||
+ (hdr->sign_len == KEY_SIZE_BYTES / 2) ||
+ (hdr->sign_len == KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_LEN;
+ } else {
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN;
+ }
+
+ memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
+
+ /* No SG support */
+ if (hdr->sg_flag)
+ return ERROR_ESBC_CLIENT_HEADER_SG;
+
+ /* modulus most significant bit should be set */
+ k = (u8 *)&img->img_key;
+
+ if ((k[0] & 0x80) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1;
+
+ /* modulus value should be odd */
+ if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2;
+
+ /* Check signature value < modulus value */
+ s = (u8 *)&img->img_sign;
+
+ if (!(memcmp(s, k, hdr->sign_len) < 0))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD;
+
+ return ESBC_VALID_HDR;
+}
+
+static inline int str2longbe(const char *p, ulong *num)
+{
+ char *endptr;
+ ulong tmp;
+
+ if (!p) {
+ return 0;
+ } else {
+ tmp = simple_strtoul(p, &endptr, 16);
+ if (sizeof(ulong) == 4)
+ *num = cpu_to_be32(tmp);
+ else
+ *num = cpu_to_be64(tmp);
+ }
+
+ return *p != '\0' && *endptr == '\0';
+}
+
+int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ ulong hash[SHA256_BYTES/sizeof(ulong)];
+ char hash_str[NUM_HEX_CHARS + 1];
+ ulong addr = simple_strtoul(argv[1], NULL, 16);
+ struct fsl_secboot_img_priv *img;
+ struct fsl_secboot_img_hdr *hdr;
+ void *esbc;
+ int ret, i, hash_cmd = 0;
+ u32 srk_hash[8];
+ uint32_t key_len;
+ struct key_prop prop;
+#if !defined(USE_HOSTCC)
+ struct udevice *mod_exp_dev;
+#endif
+
+ if (argc == 3) {
+ char *cp = argv[2];
+ int i = 0;
+
+ if (*cp == '0' && *(cp + 1) == 'x')
+ cp += 2;
+
+ /* The input string expected is in hex, where
+ * each 4 bits would be represented by a hex
+ * sha256 hash is 256 bits long, which would mean
+ * num of characters = 256 / 4
+ */
+ if (strlen(cp) != SHA256_NIBBLES) {
+ printf("%s is not a 256 bits hex string as expected\n",
+ argv[2]);
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) {
+ strncpy(hash_str, cp + (i * NUM_HEX_CHARS),
+ NUM_HEX_CHARS);
+ hash_str[NUM_HEX_CHARS] = '\0';
+ if (!str2longbe(hash_str, &hash[i])) {
+ printf("%s is not a 256 bits hex string ",
+ argv[2]);
+ return -1;
+ }
+ }
+
+ hash_cmd = 1;
+ }
+
+ img = malloc(sizeof(struct fsl_secboot_img_priv));
+
+ if (!img)
+ return -1;
+
+ memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+ hdr = &img->hdr;
+ img->ehdrloc = addr;
+ esbc = (u8 *)img->ehdrloc;
+
+ memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
+
+ /* read and validate esbc header */
+ ret = read_validate_esbc_client_header(img);
+
+ if (ret != ESBC_VALID_HDR) {
+ fsl_secboot_handle_error(ret);
+ goto exit;
+ }
+
+ /* SRKH present in SFP */
+ for (i = 0; i < NUM_SRKH_REGS; i++)
+ srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]);
+
+ /*
+ * Calculate hash of key obtained via offset present in
+ * ESBC uboot client hdr
+ */
+ ret = calc_img_key_hash(img);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /* Compare hash obtained above with SRK hash present in SFP */
+ if (hash_cmd)
+ ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES);
+ else
+ ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!hash_cmd && check_ie(img))
+ ret = 0;
+#endif
+
+ if (ret != 0) {
+ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY);
+ goto exit;
+ }
+
+ ret = calc_esbchdr_esbc_hash(img);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /* Construct encoded hash EM' wrt PKCSv1.5 */
+ construct_img_encoded_hash_second(img);
+
+ /* Fill prop structure for public key */
+ memset(&prop, 0, sizeof(struct key_prop));
+ key_len = get_key_len(img) / 2;
+ prop.modulus = img->img_key;
+ prop.public_exponent = img->img_key + key_len;
+ prop.num_bits = key_len * 8;
+ prop.exp_len = key_len;
+
+ ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
+ if (ret) {
+ printf("RSA: Can't find Modular Exp implementation\n");
+ return -EINVAL;
+ }
+
+ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+ &prop, img->img_encoded_hash);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /*
+ * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+ * memcmp returns zero on success
+ * memcmp returns non-zero on failure
+ */
+ ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
+ img->hdr.sign_len);
+
+ if (ret) {
+ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM);
+ goto exit;
+ }
+
+ printf("esbc_validate command successful\n");
+
+exit:
+ return 0;
+}
DECLARE_GLOBAL_DATA_PTR;
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "RAW timing DDR";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
#ifndef __DDR_H__
#define __DDR_H__
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 2147483648u,
- .capacity = 4294967296u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2, /* ECC */
- .burst_lengths_bitmask = 0x0c,
- .tckmin_x_ps = 1071,
- .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 6000,
- .trp_ps = 13125,
- .tras_ps = 34000,
- .trc_ps = 48125,
- .trfc_ps = 260000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 35000,
-};
-
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
--- /dev/null
+if TARGET_OMAP3_CAIRO
+
+config SYS_BOARD
+ default "cairo"
+
+config SYS_VENDOR
+ default "quipos"
+
+config SYS_CONFIG_NAME
+ default "omap3_cairo"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2014 DENX Software Engineering
+# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cairo.o
--- /dev/null
+/*
+ * Copyright (c) 2014 DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from code written by Robert Aigner (ra@spiid.net)
+ *
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <netdev.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include <asm/omap_mmc.h>
+#include "cairo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ /* TODO: verify if cairo handheld platform needs extvbus programming */
+
+ return retval;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_CAIRO();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ *
+ * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->sharing = SAMSUNG_SHARING;
+ timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
+ timings->ctrla = SAMSUNG_V_ACTIMA_165;
+ timings->ctrlb = SAMSUNG_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = SAMSUNG_V_MR_165;
+}
+#endif
+
+static const struct ns16550_platdata cairo_serial = {
+ OMAP34XX_UART2,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(cairo_uart) = {
+ "serial_omap",
+ &cairo_serial
+};
+
+/* force SPL booting into U-Boot, not Linux */
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 1;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Original code (C) Copyright 2010
+ * Robert Aigner (ra@spiid.net)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 Cairo board",
+ "NAND",
+};
+
+/*
+ * OMAP3 Cairo handheld hardware revision
+ */
+enum {
+ OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
+ OMAP3_CAIRO_BOARD_GEN_2,
+};
+
+#define MUX_CAIRO() \
+MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
+ (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+
+#endif
--- /dev/null
+if TARGET_AMCORE
+
+config SYS_CPU
+ string
+ default "mcf530x"
+
+config SYS_BOARD
+ string
+ default "amcore"
+
+config SYS_VENDOR
+ string
+ default "sysam"
+
+config SYS_CONFIG_NAME
+ string
+ default "amcore"
+
+endif
+
+
+
--- /dev/null
+AMCORE BOARD
+M: Angelo Dureghello <angelo@sysam.it>
+S: Maintained
+F: board/sysam/amcore/
+F: include/configs/amcore.h
+F: configs/amcore_defconfig
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = amcore.o
--- /dev/null
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+void init_lcd(void)
+{
+ /* setup for possible K0108 lcd connected on the parallel port */
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_be16(&sim->par, 0x300);
+
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+ out_be16(&gpio->paddr, 0xfcff);
+ out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("AMCORE v.001(alpha)\n");
+
+ init_lcd();
+
+ return 0;
+}
+
+/*
+ * in initdram we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+ while (usec--)
+ asm volatile ("nop");
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, RC;
+
+ sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+ /*
+ * SDRAM MT48LC4M32B2 details
+ * Memory block 0: 16 MB of SDRAM at address $00000000
+ * Port size: 32-bit port
+ *
+ * Memory block 0 wired as follows:
+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
+ *
+ * Ensure that there is a delay of at least 100 microseconds from
+ * processor reset to the following code so that the SDRAM is ready
+ * for commands.
+ */
+ fudelay(100);
+
+ /*
+ * DCR
+ * set proper RC as per specification
+ */
+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* 0x8000 is the faster option */
+ out_be16(&dc->dcr, 0x8200 | RC);
+
+ /*
+ * DACR0, page mode continuous, CMD on A20 0x0300
+ */
+ out_be32(&dc->dacr0, 0x00003304);
+
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ out_be32(&dc->dmr0, dramsize|1);
+
+ /* issue a PRECHARGE ALL */
+ out_be32(&dc->dacr0, 0x0000330c);
+ out_be32((u32 *)0x00000004, 0xbeaddeed);
+ /* issue AUTOREFRESH */
+ out_be32(&dc->dacr0, 0x0000b304);
+ /* let refresh occour */
+ fudelay(1);
+
+ out_be32(&dc->dacr0, 0x0000b344);
+ out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+}
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
--- /dev/null
+/*
+ * Linker script for Sysam AMCORE board
+ *
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf530x/start.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.sdata)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
return 0;
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int init_func_ram(void)
{
#ifdef CONFIG_BOARD_TYPES
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int setup_board_part1(void)
{
bd_t *bd = gd->bd;
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
+ bd->bi_pcifreq = gd->pci_clk;
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
+#endif
return 0;
}
{
#ifdef CONFIG_SYS_TEXT_BASE
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
+#ifdef CONFIG_M68K
+ /*
+ * On all ColdFire arch cpu, monitor code starts always
+ * just after the default vector table location, so at 0x400
+ */
+ gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
+#endif
#endif
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks,
+#endif
+#ifdef CONFIG_M68K
+ get_clocks,
#endif
env_init, /* initialize environment */
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
checkcpu,
#endif
print_cpuinfo, /* display cpu info (and speed) */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
dram_init, /* configure available RAM banks */
#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
init_func_ram,
#endif
#ifdef CONFIG_POST
reserve_stacks,
setup_dram_config,
show_dram_config,
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
* Transfer execution from Flash to RAM by calculating the address
* of the in-RAM copy of board_init_r() and calling it
*/
- (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
+ (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
/* NOTREACHED - board_init_r() does not return */
hang();
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int initr_trap(void)
{
/*
* Setup trap handlers
*/
+#if defined(CONFIG_PPC)
trap_init(gd->relocaddr);
-
+#else
+ trap_init(CONFIG_SYS_SDRAM_BASE);
+#endif
return 0;
}
#endif
return 0;
}
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-static int initr_noncached(void)
-{
- noncached_init();
- return 0;
-}
-#endif
-
#ifdef CONFIG_DM
static int initr_dm(void)
{
#endif
initr_barrier,
initr_malloc,
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
- initr_noncached,
-#endif
bootstage_relocate,
#ifdef CONFIG_DM
initr_dm,
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
initr_trap,
#endif
#ifdef CONFIG_ADDR_MAP
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
initr_enable_interrupts,
#endif
-#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
+#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) \
+ || defined(CONFIG_M68K)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
return CMD_RET_USAGE;
}
- if (state != BOOTM_STATE_START && images.state >= state) {
+ if (((state & BOOTM_STATE_START) != BOOTM_STATE_START) &&
+ images.state >= state) {
printf("Trying to execute a command out of order\n");
return CMD_RET_USAGE;
}
/* extract disk guid */
s = str;
- tok = strsep(&s, ";");
- val = extract_val(tok, "uuid_disk");
+ val = extract_val(str, "uuid_disk");
if (!val) {
+#ifdef CONFIG_RANDOM_UUID
+ *str_disk_guid = malloc(UUID_STR_LEN + 1);
+ gen_rand_uuid_str(*str_disk_guid, UUID_STR_FORMAT_STD);
+#else
free(str);
return -2;
+#endif
+ } else {
+ val = strsep(&val, ";");
+ if (extract_env(val, &p))
+ p = val;
+ *str_disk_guid = strdup(p);
+ free(val);
+ /* Move s to first partition */
+ strsep(&s, ";");
}
- if (extract_env(val, &p))
- p = val;
- *str_disk_guid = strdup(p);
- free(val);
-
if (strlen(s) == 0)
return -3;
/* uuid */
val = extract_val(tok, "uuid");
- if (!val) { /* 'uuid' is mandatory */
- errno = -4;
- goto err;
- }
- if (extract_env(val, &p))
- p = val;
- if (strlen(p) >= sizeof(parts[i].uuid)) {
- printf("Wrong uuid format for partition %d\n", i);
+ if (!val) {
+ /* 'uuid' is optional if random uuid's are enabled */
+#ifdef CONFIG_RANDOM_UUID
+ gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD);
+#else
errno = -4;
goto err;
+#endif
+ } else {
+ if (extract_env(val, &p))
+ p = val;
+ if (strlen(p) >= sizeof(parts[i].uuid)) {
+ printf("Wrong uuid format for partition %d\n", i);
+ errno = -4;
+ goto err;
+ }
+ strcpy((char *)parts[i].uuid, p);
+ free(val);
}
- strcpy((char *)parts[i].uuid, p);
- free(val);
-
/* name */
val = extract_val(tok, "name");
if (!val) { /* name is mandatory */
}
/* save partitions layout to disk */
- gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
+ ret = gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
free(str_disk_guid);
free(partitions);
- return 0;
+ return ret;
}
/**
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
"Use the UMS [User Mass Storage]",
- "ums <USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
+ "<USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
" devtype defaults to mmc"
);
U_BOOT_CMD(ytrace, 2, 0, do_ytrace,
"show/set yaffs trace mask",
- "ytrace [new_mask] show/set yaffs trace mask");
+ "[new_mask] show/set yaffs trace mask");
U_BOOT_CMD(ydevls, 1, 0, do_ydevls,
"list yaffs mount points", "list yaffs mount points");
U_BOOT_CMD(ydevconfig, 5, 0, do_ydevconfig,
"configure yaffs mount point",
- "ydevconfig mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
+ "mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
U_BOOT_CMD(ymount, 2, 0, do_ymount,
- "mount yaffs", "ymount mtpoint mounts a yaffs2 mount point");
+ "mount yaffs", "mtpoint mounts a yaffs2 mount point");
U_BOOT_CMD(yumount, 2, 0, do_yumount,
- "unmount yaffs", "yunmount mtpoint unmounts a yaffs2 mount point");
+ "unmount yaffs", "mtpoint unmounts a yaffs2 mount point");
-U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "yls [-l] dirname");
+U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "[-l] dirname");
U_BOOT_CMD(yrd, 2, 0, do_yrd,
- "read file from yaffs", "yrd path read file from yaffs");
+ "read file from yaffs", "path read file from yaffs");
U_BOOT_CMD(ywr, 4, 0, do_ywr,
"write file to yaffs",
- "ywr filename value num_vlues write values to yaffs file");
+ "filename value num_vlues write values to yaffs file");
U_BOOT_CMD(yrdm, 3, 0, do_yrdm,
"read file to memory from yaffs",
- "yrdm filename offset reads yaffs file into memory");
+ "filename offset reads yaffs file into memory");
U_BOOT_CMD(ywrm, 4, 0, do_ywrm,
"write file from memory to yaffs",
- "ywrm filename offset size writes memory to yaffs file");
+ "filename offset size writes memory to yaffs file");
U_BOOT_CMD(ymkdir, 2, 0, do_ymkdir,
- "YAFFS mkdir", "ymkdir dir create a yaffs directory");
+ "YAFFS mkdir", "dir create a yaffs directory");
U_BOOT_CMD(yrmdir, 2, 0, do_yrmdir,
- "YAFFS rmdir", "yrmdir dirname removes a yaffs directory");
+ "YAFFS rmdir", "dirname removes a yaffs directory");
-U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "yrm path removes a yaffs file");
+U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "path removes a yaffs file");
U_BOOT_CMD(ymv, 4, 0, do_ymv,
"YAFFS mv",
- "ymv old_path new_path moves/rename files within a yaffs mount point");
+ "old_path new_path moves/rename files within a yaffs mount point");
lcd_puts(buf);
}
+
+static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned int col, row;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ col = simple_strtoul(argv[1], NULL, 10);
+ row = simple_strtoul(argv[2], NULL, 10);
+ lcd_position_cursor(col, row);
+
+ return 0;
+}
+
+static int do_lcd_puts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setcurs, 3, 1, do_lcd_setcursor,
+ "set cursor position within screen",
+ " <col> <row> in character"
+);
+
+U_BOOT_CMD(
+ lcdputs, 2, 1, do_lcd_puts,
+ "print string on lcd-framebuffer",
+ " <string>"
+);
+
--- /dev/null
+CONFIG_M68K=y
+CONFIG_TARGET_AMCORE=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_BAV335X=y
++S:CONFIG_BAV_VERSION=1
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_BAV335X=y
++S:CONFIG_BAV_VERSION=2
--- /dev/null
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_OMAP3_CAIRO=y
--- /dev/null
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
--- /dev/null
+DSP side awareness for Freescale heterogeneous multicore chips based on
+StarCore and Power Architecture
+===============================================================
+powerpc/mpc85xx code ve APIs and function to get the number,
+configuration and frequencies of all PowerPC cores and devices
+connected to them, but it didnt have the similar code ofr HEterogeneous
+SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
+
+Code for DSP side awareness provides such functionality for Freescale
+Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420
+
+As part of this feature, following changes have been made:
+==========================================================
+
+1. Changed files:
+=================
+- arch/powerpc/cpu/mpc85xx/cpu.c
+
+Code added in this file to print the DSP cores and other device's(CPRI,
+MAPLE etc) frequencies
+
+- arch/powerpc/cpu/mpc85xx/speed.c
+
+Added Defines and code to extract the frequncy information for all
+required cores and devices from RCW and System frequency
+
+- arch/powerpc/cpu/mpc8xxx/cpu.c
+
+Added API to get the number of SC cores in running system and Their BIT
+MASK, similar to the code written for PowerPC
+
+- arch/powerpc/include/asm/config_mpc85xx.h
+
+Added top level CONFIG to identify presence of HETEROGENUOUS clusters
+in the system and CONFIGS for SC3900/DSP components
+
+- arch/powerpc/include/asm/processor.h
+- include/common.h
+
+Added newly added Functions Declaration
+
+- include/e500.h
+
+Global structure updated for dsp cores and other components
+
+2. CONFIGs ADDED
+================
+
+CONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of
+ DSP/SC3900 core clusters
+
+CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs
+
+Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
+PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
+value as 5 not 4, to iterate over all PLLs while coding
+
+CONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator
+CONFIG_SYS_CPRI - Define for CPRI Interface
+CONFIG_PPC_CLUSTER_START - Start index of ppc clusters
+CONFIG_DSP_CLUSTER_START - Start index of dsp clusters
+
+Following are the defines for PLL's index that provide the Clocking to
+CPRI, ULB and ETVE components
+
+CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock
+CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock
+CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
+
+3. Changes in MPC85xx_SYS_INFO Global structure
+===============================================
+
+DSP cores and other device's components have been added in this structure.
+
+freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies
+freq_cpri - To store CPRI frequency
+freq_maple - To store MAPLE frequency
+freq_maple_ulb - To store MAPLE-ULB frequency
+freq_maple_etvpe - To store MAPLE-eTVPE frequency
+
+4. U-BOOT LOGS
+==============
+4.1 B4860QDS board
+ Boot from NOR flash
+
+U-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47)
+
+CPU0: B4860E, Version: 2.0, (0x86880020)
+Core: e6500, Version: 2.0, (0x80400020) Clock Configuration:
+ CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
+ DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
+ DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
+ CCB:666.667 MHz,
+ DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
+ CPRI:600 MHz
+ MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
+ FMAN1: 666.667 MHz
+ QMAN: 333.333 MHz
+
+CPUn - PowerPC core
+DSP CPUn - SC3900 core
+
+Shaveta Leekha(shaveta@freescale.com)
+Created August 7, 2014
+===========================================
--- /dev/null
+/*
+ * (C) Copyright 2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+esbc_validate command
+========================================
+
+1. esbc_validate command is meant for validating header and
+ signature of images (Boot Script and ESBC uboot client).
+ SHA-256 and RSA operations are performed using SEC block in HW.
+ This command works on both PBL based and Non PBL based Freescale
+ platforms.
+ Command usage:
+ esbc_validate img_hdr_addr [pub_key_hash]
+ esbc_validate hdr_addr <hash_val>
+ Validates signature using RSA verification.
+ $hdr_addr Address of header of the image to be validated.
+ $hash_val -Optional. It provides Hash of public/srk key to be
+ used to verify signature.
+
+2. ESBC uboot client can be linux. Additionally, rootfs and device
+ tree blob can also be signed.
+3. In the event of header or signature failure in validation,
+ ITS and ITF bits determine further course of action.
+4. In case of soft failure, appropriate error is dumped on console.
+5. In case of hard failure, SoC is issued RESET REQUEST after
+ dumping error on the console.
+6. KEY REVOCATION Feature:
+ QorIQ platforms like B4/T4 have support of srk key table and key
+ revocation in ISBC code in Silicon.
+ The srk key table allows the user to have a key table with multiple
+ keys and revoke any key in case of particular key gets compromised.
+ In case the ISBC code uses the key revocation and srk key table to
+ verify the u-boot code, the subsequent chain of trust should also
+ use the same.
+6. ISBC KEY EXTENSION Feature:
+ This feature allows large number of keys to be used for esbc validation
+ of images. A set of public keys is being signed and validated by ISBC
+ which can be further used for esbc validation of images.
"partitions=uuid_disk=${uuid_gpt_disk};name=${uboot_name},
size=${uboot_size},uuid=${uboot_uuid};"
- Fields 'name', 'size' and 'uuid' are mandatory for every partition.
+ The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
- option: CONFIG_RANDOM_UUID
- If any partition "UUID" no exists then it is randomly generated.
+ The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
+ enabled. A random uuid will be used if omitted or they point to an empty/
+ non-existent environment variable. The environment variable will be set to
+ the generated UUID.
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o
+obj-$(CONFIG_RSA) += mod_exp_uclass.o
+obj-$(CONFIG_RSA_SOFTWARE_EXP) += mod_exp_sw.o
but otherwise makes few changes. Since cros_ec also supports
LPC (which doesn't support driver model yet), a full
conversion is not yet possible.
+
+config CONFIG_FSL_SEC_MON
+ bool "Enable FSL SEC_MON Driver"
+ help
+ Freescale Security Monitor block is responsible for monitoring
+ system states.
+ Security Monitor can be transitioned on any security failures,
+ like software violations or hardware security violations.
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
+obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_sec_mon.h>
+
+int change_sec_mon_state(u32 initial_state, u32 final_state)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ int timeout = 10;
+
+ if ((sts & HPSR_SSM_ST_MASK) != initial_state)
+ return -1;
+
+ if (initial_state == HPSR_SSM_ST_TRUST) {
+ switch (final_state) {
+ case HPSR_SSM_ST_NON_SECURE:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+
+ /*
+ * poll till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+
+ timeout = 10;
+
+ printf("SEC_MON state transitioning to Non Secure.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
+
+ /*
+ * poll till SEC_MON is in
+ * Non Secure state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_NON_SECURE)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
+ switch (final_state) {
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ return 0;
+}
static uint8_t cs_next;
static __maybe_unused struct nand_ecclayout omap_ecclayout;
+#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
+ { CONFIG_NAND_OMAP_GPMC_WSCFG };
+#else
+/* wscfg is preset to zero since its a static variable */
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
/*
* Driver configurations
*/
struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
- int cs;
+ uint8_t cs;
+ uint8_t ws; /* wait status pin (0,1) */
};
/* We are wasting a bit of memory but al least we are safe */
/* Check wait pin as dev ready indicator */
static int omap_dev_ready(struct mtd_info *mtd)
{
- return gpmc_cfg->status & (1 << 8);
+ register struct nand_chip *this = mtd->priv;
+ struct omap_nand_info *info = this->priv;
+ return gpmc_cfg->status & (1 << (8 + info->ws));
}
/*
return -EINVAL;
}
} else {
- err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ if (eccstrength == 1) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_SW,
mtd->writesize, mtd->oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ mtd->writesize, mtd->oobsize);
+ } else {
+ printf("nand: error: unsupported ECC scheme\n");
+ return -EINVAL;
+ }
}
/* Update NAND handling after ECC mode switch */
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
+ omap_nand_info[cs].ws = wscfg[cs];
nand->priv = &omap_nand_info[cs];
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
+#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
&dma_p->opmode);
+#else
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
+ &dma_p->opmode);
+#endif
writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
+#ifdef CONFIG_DW_AXI_BURST_LEN
+ writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
+#endif
+
/* Start up the PHY */
if (phy_startup(priv->phydev)) {
printf("Could not initialize PHY %s\n",
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
+ /* turn ON display through powercontrol function if accessible */
+ if (0 != panel->panel_power_ctrl)
+ panel->panel_power_ctrl(1);
+
+ debug("am335x-fb: wait for stable power ...\n");
+ mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
gd->fb_base += 0x20; /* point fb behind palette */
- /* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl) {
- mdelay(panel->pon_delay);
- panel->panel_power_ctrl(1);
- }
+ debug("am335x-fb: waiting picture to be stable.\n.");
+ mdelay(panel->pon_delay);
return 0;
}
unsigned int vsw; /* Vertical Sync Pulse Width */
unsigned int pxl_clk_div; /* Pixel clock divider*/
unsigned int pol; /* polarity of sync, clock signals */
+ unsigned int pup_delay; /*
+ * time in ms after power on to
+ * initialization of lcd-controller
+ * (VCC ramp up time)
+ */
unsigned int pon_delay; /*
- * time in ms for turning on lcd after
- * initializing lcd-controller
+ * time in ms after initialization of
+ * lcd-controller (pic stabilization)
*/
void (*panel_power_ctrl)(int); /* fp for power on/off display */
};
}
ext4fs_close();
+ *actwrite = len;
+
return 0;
fail:
ext4fs_close();
+ *actwrite = 0;
return -1;
}
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
iter++, cpu = cpumask_next(cpu, mask)) \
int cpu_numcores (void);
+int cpu_num_dspcores(void);
u32 cpu_mask (void);
+u32 cpu_dsp_mask(void);
int is_core_valid (unsigned int);
int probecpu (void);
int checkcpu (void);
#define CONFIG_M54451 /* define processor type */
#define CONFIG_M54451EVB /* M54451EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
--- /dev/null
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_AMCORE
+#define CONFIG_HOSTNAME AMCORE
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_MCF530x
+#define CONFIG_M5307
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AES
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT "amcore $ "
+/* undef to save memory */
+#undef CONFIG_SYS_LONGHELP
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0x0
+#define CONFIG_SYS_MEMTEST_END 0x1000000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_CLK 45000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR 0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+ CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+ CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1 C/I BIT for errata */
+#define CONFIG_SYS_CS0_MASK 0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define CONFIG_SYS_CS0_CTRL 0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE 0x3000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x0100
+
+#endif /* __AMCORE_CONFIG_H */
+
#ifndef __CONFIG_ASPENITE_H
#define __CONFIG_ASPENITE_H
+/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
--- /dev/null
+/*
+ * bav335x.h
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BAV335X_H
+#define __CONFIG_BAV335X_H
+
+#include <configs/ti_am335x_common.h>
+#define CONFIG_ENV_IS_NOWHERE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_FIT
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+# ifdef CONFIG_ENABLE_VBOOT
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
+# endif
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+DEFAULT_LINUX_BOOT_ENV \
+"boot_fdt=try\0" \
+"bootpart=0:2\0" \
+"bootdir=\0" \
+"fdtdir=/dtbs\0" \
+"bootfile=zImage\0" \
+"fdtfile=undefined\0" \
+"console=ttyO0,115200n8\0" \
+"loadaddr=0x82000000\0" \
+"fdtaddr=0x88000000\0" \
+"rdaddr=0x88080000\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0" \
+"partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+"optargs=\0" \
+"cmdline=\0" \
+"mmcdev=0\0" \
+"mmcpart=1\0" \
+"mmcroot=/dev/mmcblk0p2 ro\0" \
+"mmcrootfstype=ext4 rootwait fixrtc\0" \
+"rootpath=/export/rootfs\0" \
+"nfsopts=nolock\0" \
+"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+"ramroot=/dev/ram0 rw\0" \
+"ramrootfstype=ext2\0" \
+"mmcargs=setenv bootargs console=${console} ${optargs} " \
+ "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
+"server_ip=192.168.1.100\0" \
+"gw_ip=192.168.1.1\0" \
+"netmask=255.255.255.0\0" \
+"hostname=\0" \
+"device=eth0\0" \
+"autoconf=off\0" \
+"root_dir=/home/userid/targetNFS\0" \
+"nfs_options=,vers=3\0" \
+"nfsrootfstype=ext4 rootwait fixrtc\0" \
+"nfsargs=setenv bootargs console=${console} ${optargs} " \
+ "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
+ "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
+"bootenv=uEnv.txt\0" \
+"script=boot.scr\0" \
+"scriptfile=${script}\0" \
+"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+ "source ${loadaddr}\0" \
+ "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+"importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t -r $loadaddr $filesize\0" \
+"ramargs=setenv bootargs console=${console} " \
+ "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
+"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} " \
+ "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
+"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
+ "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
+"mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "gpio set 54;" \
+ "setenv bootpart ${mmcdev}:1; " \
+ "if test -e mmc ${bootpart} /etc/fstab; then " \
+ "setenv mmcpart 1;" \
+ "fi; " \
+ "echo Checking for: /uEnv.txt ...;" \
+ "if test -e mmc ${bootpart} /uEnv.txt; then " \
+ "if run loadbootenv; then " \
+ "gpio set 55;" \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Checking if uenvcmd is set ...;" \
+ "if test -n ${uenvcmd}; then " \
+ "gpio set 56; " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "echo Checking if client_ip is set ...;" \
+ "if test -n ${client_ip}; then " \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo using ${fdtfile} ...;" \
+ "fi;" \
+ "gpio set 56; " \
+ "if test -n ${uname_r}; then " \
+ "echo Running nfsboot_uname_r ...;" \
+ "run nfsboot_uname_r;" \
+ "fi;" \
+ "echo Running nfsboot ...;" \
+ "run nfsboot;" \
+ "fi;" \
+ "fi; " \
+ "echo Checking for: /${script} ...;" \
+ "if test -e mmc ${bootpart} /${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile ${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/${script} ...;" \
+ "if test -e mmc ${bootpart} /boot/${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile /boot/${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/uEnv.txt ...;" \
+ "for i in 1 2 3 4 5 6 7 ; do " \
+ "setenv mmcpart ${i};" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
+ "gpio set 55;" \
+ "load mmc ${bootpart} ${loadaddr} " \
+ "/boot/uEnv.txt;" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from /boot/uEnv.txt;" \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo Using: dtb=${fdtfile} ...;" \
+ "fi;" \
+ "echo Checking if uname_r is set in " \
+ "/boot/uEnv.txt...;" \
+ "if test -n ${uname_r}; then " \
+ "gpio set 56; " \
+ "echo Running uname_boot ...;" \
+ "setenv mmcroot /dev/mmcblk${mmcdev}" \
+ "p${mmcpart} ro;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "done;" \
+ "fi;\0" \
+"netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} dtbs/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} vmlinuz-${uname_r}; " \
+ "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+"findfdt="\
+ "if test $board_rev = B; then " \
+ "setenv fdtfile birdland_bav335b.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $board_rev = A; then " \
+ "setenv fdtfile birdland_bav335a.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
+"uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; "\
+ "run loadimage;" \
+ "setenv fdtdir /boot/dtbs/${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/" \
+ "${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtb-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtbs; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find " \
+ "[${fdtfile}] " \
+ "did you name it correctly?" \
+ "echo booting fallback " \
+ "[/boot/dtbs/" \
+ "${uname_r}" \
+ "/${fdtbase}.dtb]...;" \
+ "setenv fdtdir /boot/dtbs/" \
+ "${uname_r}; " \
+ "setenv fdtfile " \
+ "${fdtbase}.dtb; " \
+ "run loadfdt;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi; " \
+ "setenv rdfile initrd.img-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
+ "echo loading ${bootdir}/${rdfile} ...; "\
+ "run loadrd;" \
+ "if test -n ${uuid}; then " \
+ "setenv mmcroot UUID=${uuid} ro;" \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
+ "${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
+ "else " \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi;" \
+"fi;\0" \
+ NANDARGS \
+ DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "gpio set 53; " \
+ "i2c mw 0x24 1 0x3e; " \
+ "run findfdt; " \
+ "setenv mmcdev 0; " \
+ "setenv bootpart 0:1; " \
+ "run mmcboot;" \
+ "gpio clear 56; " \
+ "gpio clear 55; " \
+ "gpio clear 54; " \
+ "setenv mmcdev 1; " \
+ "setenv bootpart 1:1; " \
+ "run mmcboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#endif
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL"
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0xD80000;" \
+ "fdt ram 0x80F80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+ "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
+ "512k(u-boot),128k(u-boot-env1)," \
+ "128k(u-boot-env2),3464k(kernel)," \
+ "-(rootfs)"
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x0
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#endif
+#endif /* NOR support */
+
+#endif /* ! __CONFIG_AM335X_EVM_H */
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"defaultip=192.168.60.253\0" \
+"defaultsip=192.168.60.254\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then " \
+"setenv ncip ${serverip}; else " \
+"setenv ncip 192.168.60.254; " \
+"setenv serverip 192.168.60.254; " \
+"setenv gatewayip 192.168.60.254; " \
+"setenv ipaddr 192.168.60.1; " \
+"fi;" \
+"setenv netdisplay0 '" \
+"setcurs 1 9; puts myip; setcurs 10 9; puts ${ipaddr};" \
+"setcurs 1 10;puts serverip; setcurs 10 10; puts ${serverip}\;'" \
+"run netdisplay0; " \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+#define CONFIG_CMD_TIME
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4)
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_24BMP
+#define CONFIG_BMP_32BPP
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_AM33XX
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_NET_RETRY_COUNT 2
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-
+/* Network console */
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_MALLOC_LEN (5120 << 10)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
/*
* Commands configuration
#define MACH_TYPE_SHEEVAD 2625
#endif
+/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_SPL_OS_BOOT
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-#endif /* CONFIG_SPL_OS_BOOT */
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80100000\0" \
- "bootfile=arimg\0" \
- "usbboot=echo Booting from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 ${loadaddr} ${bootfile}; " \
- "usb stop; " \
- "go ${loadaddr};\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload 0; " \
- "dhcp; " \
- "tftp ${loadaddr} arimg; " \
- "go ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0"
+BUR_COMMON_ENV \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"autoload=0\0" \
+"loadaddr=0x80100000\0" \
+"logoaddr=0x82000000\0" \
+"defaultARlen=0x8000\0" \
+"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \
+"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"mmcboot=echo booting AR from eMMC-flash ...; "\
+ "run logo0 || run logo1; " \
+ "run loadromfs; " \
+ "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \
+ "run defaultAR;\0" \
+"netboot=echo booting AR from network ...; " \
+ "run loadromfs; " \
+ "tftp ${loadaddr} arimg && go ${loadaddr}; " \
+ "puts 'networkboot failed!';\0" \
+"usbupdate=echo updating u-boot from usb ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img && source; " \
+ "puts 'usbupdate failed!'\0" \
+"netscript=echo running script from network (tftp) ...; " \
+ "tftp 0x80000000 netscript.img && source; " \
+ "puts 'netscript load failed!'\0" \
+"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
+"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
+ "if tftp 0x80100000 arimg.bin; " \
+ "then mmc write 0x80100000 800 ${defaultARlen}; " \
+ "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
+"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
+ "if tftp 0x80100000 romfs.bin; " \
+ "then mmc write 0x80100000 700 100; " \
+ "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
+
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
"run usbupdate;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+#define CONFIG_BOOTDELAY 0
/* undefine command which we not need here */
-#undef CONFIG_BOOTM_LINUX
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
--- /dev/null
+/*
+ * Configuration settings for the QUIPOS Cairo board.
+ *
+ * Copyright (C) DENX GmbH
+ *
+ * Author :
+ * Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from EVM code by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Also derived from include/configs/omap3_beagle.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OMAP3_CAIRO_CONFIG_H
+#define __OMAP3_CAIRO_CONFIG_H
+
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs. We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+#define CONFIG_NAND
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_ENV_OVERWRITE
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
+
+#define CONFIG_NAND
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+
+/* Disable some commands */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+/* override default CONFIG_BOOTDELAY */
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "machid=ffffffff\0" \
+ "fdt_high=0x87000000\0" \
+ "baudrate=115200\0" \
+ "ethaddr=00:50:C2:7E:90:F0\0" \
+ "fec_addr=00:50:C2:7E:90:F0\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.2.9\0" \
+ "gateway=192.168.2.1\0" \
+ "serverip=192.168.2.10\0" \
+ "nfshost=192.168.2.10\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "bootargs_mmc_ramdisk=mem=128M " \
+ "console=ttyO1,115200n8 " \
+ "root=/dev/ram0 rw " \
+ "initrd=0x81600000,16M " \
+ "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
+ "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "mmcboot=mmc init; " \
+ "fatload mmc 0 0x80000000 uImage; " \
+ "fatload mmc 0 0x81600000 ramdisk.gz; " \
+ "setenv bootargs ${bootargs_mmc_ramdisk}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
+ "root=/dev/nfs " \
+ "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
+ "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
+ "omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
+ "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
+ "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
+ "omapfb.rotate_type=1\0" \
+ "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
+ "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
+ "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
+ "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
+ "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
+ "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
+ "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
+ "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
+ "nand erase 0 20000; " \
+ "fatload mmc 0 0x81600000 MLO; " \
+ "nandecc hw; " \
+ "nand write.i 0x81600000 0 20000;\0" \
+ "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
+ "nand erase 80000 40000; " \
+ "fatload mmc 0 0x81600000 u-boot.bin; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 80000 40000;\0" \
+ "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
+ "nand erase 280000 300000; " \
+ "fatload mmc 0 0x81600000 uImage; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 280000 300000;\0" \
+ "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
+ "nandecc sw; " \
+ "nand write.jffs2 0x680000 0xFF ${filesize}; " \
+ "nand erase 680000 ${filesize}; " \
+ "nand write.jffs2 81600000 680000 ${filesize};\0" \
+ "flash_scrub=nand scrub; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs;\0" \
+ "flash_all=run ledred; " \
+ "nand erase.chip; " \
+ "run ledorange; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs; " \
+ "run ledgreen; " \
+ "run boot_nand; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
+ "else run boot_nand; fi"
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Defines for SPL */
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+
+/* env defaults */
+#define CONFIG_BOOTFILE "uImage"
+
+/* Override OMAP3 common serial console configuration from UART3
+ * to UART2.
+ *
+ * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
+ * are needed and peripheral clocks for UART2 must be enabled in
+ * function per_clocks_enable().
+ */
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 2
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NS16550_COM3
+#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
+#undef CONFIG_SERIAL3
+#define CONFIG_SERIAL2
+#endif
+
+/* Keep old prompt in case some existing script depends on it */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "Cairo # "
+
+/* Provide MACH_TYPE for compatibility with non-DT kernels */
+#define MACH_TYPE_OMAP3_CAIRO 3063
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#endif /* __OMAP3_CAIRO_CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_REGEX /* Enable regular expression support */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR 0x8000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
* High level configuration
*/
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_REGEX /* Enable regular expression support */
#endif
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_cyclone5
* Common configurations used for both spear3xx as well as spear6xx
*/
+#define CONFIG_SYS_GENERIC_BOARD
+
/* U-boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
/* Support both device trees and ATAGs. */
#define CONFIG_OF_LIBFDT
+#define CONFIG_USE_FDT /* use fdt within board code */
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_NAND */
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifdef CONFIG_NAND
#define NANDARGS \
#ifdef CONFIG_MMC
#define MMCARGS \
- "silent=1\0"
+"dtbdev=mmc\0" \
+"dtbpart=0:1\0" \
+"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \
+"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \
+ "rootfstype=ext4\0" \
+"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
+ "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
+ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
+"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
+ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
+"defboot=run logo0 || run logo1; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
+ "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
+ "run ramboot; run usbupdate;\0" \
+"bootlimit=1\0" \
+"altbootcmd=run logo0 || run logo1; " \
+ "run mmcboot0;\0" \
+"upduboot=dhcp; " \
+ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
#else
#define MMCARGS ""
#endif /* CONFIG_MMC */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80200000\0" \
- "bootfile=zImage\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "rootpath=/tftpboot/tseries/rootfs-small\0" \
- "nfsopts=nolock\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0" \
- NANDARGS \
- MMCARGS
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"dtb=bur-ppt-ts30.dtb\0" \
+"dtbaddr=0x80100000\0" \
+"loadaddr=0x80200000\0" \
+"ramaddr=0x80A00000\0" \
+"kernel=zImage\0" \
+"ramdisk=rootfs.cpio.uboot\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \
+"nfsroot=/tftpboot/tseries/rootfs-small\0" \
+"nfsopts=nolock\0" \
+"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
+ "ip=dhcp\0" \
+"netboot=echo Booting from network ...; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${dtbaddr} ${dtb}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${dtbaddr}\0" \
+"ramboot=echo Booting from network into RAM ...; "\
+ "if dhcp; then; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${ramaddr} ${ramdisk}; " \
+ "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
+ "then; else tftp ${dtbaddr} ${dtb}; fi;" \
+ "run mmcroot0; " \
+ "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
+"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \
+"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
+NANDARGS \
+MMCARGS
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
- "run mmcboot1;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+ "run defboot;"
+#define CONFIG_BOOTDELAY 0
#ifdef CONFIG_NAND
/*
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FS_GENERIC
#endif /* CONFIG_MMC, ... */
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_SUPPORT_RAW_INITRD
/* Cache Definitions */
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
/* SMP Spin Table Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#define V2M_BASE 0x80000000
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0 (V2M_PA_CS0)
-#define V2M_NOR1 (V2M_PA_CS4)
-#define V2M_SRAM (V2M_PA_CS1)
-
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-/* SMSC91C111 Ethernet Configuration */
+/* Ethernet Configuration */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+/* The real hardware Versatile express uses SMSC9118 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE (0x018000000)
+#else
+/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE (0x01A000000)
+#endif
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
"fdt_addr_r=0x83000000\0" \
"fdt_high=0xa0000000\0"
-#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY -1
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
+/* Flash memory is available on the Juno board only */
+#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif
+
#endif /* __VEXPRESS_AEMV8A_H */
*/
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
+#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/hardware.h>
typedef struct
{
unsigned long freq_processor[CONFIG_MAX_CPUS];
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS];
+#endif
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_localbus;
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
+#ifdef CONFIG_SYS_CPRI
+ unsigned long freq_cpri;
+#endif
+#ifdef CONFIG_SYS_MAPLE
+ unsigned long freq_maple;
+ unsigned long freq_maple_ulb;
+ unsigned long freq_maple_etvpe;
+#endif
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
unsigned char diff_sysclk;
#endif
--- /dev/null
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SEC_MON_H
+#define __FSL_SEC_MON_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_MON_LE
+#define sec_mon_in32(a) in_le32(a)
+#define sec_mon_out32(a, v) out_le32(a, v)
+#define sec_mon_in16(a) in_le16(a)
+#define sec_mon_clrbits32 clrbits_le32
+#define sec_mon_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
+#define sec_mon_in32(a) in_be32(a)
+#define sec_mon_out32(a, v) out_be32(a, v)
+#define sec_mon_in16(a) in_be16(a)
+#define sec_mon_clrbits32 clrbits_be32
+#define sec_mon_setbits32 setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
+#endif
+
+struct ccsr_sec_mon_regs {
+ u8 reserved0[0x04];
+ u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
+ u8 reserved2[0x0c];
+ u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
+};
+
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
+#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
+#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
+#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
+
+/*
+ * SEC_MON read. This specifies the possible reads
+ * from the SEC_MON
+ */
+enum {
+ SEC_MON_SSM_ST,
+ SEC_MON_SW_FSV,
+ SEC_MON_SW_SV,
+};
+
+int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+
+#endif /* __FSL_SEC_MON_H */
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SECBOOT_ERR_H
+#define _FSL_SECBOOT_ERR_H
+
+#define ERROR_ESBC_PAMU_INIT 0x100000
+#define ERROR_ESBC_SEC_RESET 0x200000
+#define ERROR_ESBC_SEC_INIT 0x400000
+#define ERROR_ESBC_SEC_DEQ 0x800000
+#define ERROR_ESBC_SEC_DEQ_TO 0x1000000
+#define ERROR_ESBC_SEC_ENQ 0x2000000
+#define ERROR_ESBC_SEC_JOBQ_STATUS 0x4000000
+#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH 0x1
+#define ERROR_ESBC_CLIENT_HDR_LOC 0x2
+#define ERROR_ESBC_CLIENT_HEADER_BARKER 0x4
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN 0x8
+#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN 0x10
+#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED 0x11
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY 0x12
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM 0x13
+#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN 0x14
+#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED 0x15
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY 0x16
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM 0x17
+#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18
+#define ERROR_IE_TABLE_NOT_FOUND 0x19
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80
+#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100
+#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP 0x200
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY 0x400
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM 0x800
+#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS 0x1000
+#define ERROR_ESBC_CLIENT_BAD_ADDRESS 0x2000
+#define ERROR_ESBC_CLIENT_MISC 0x4000
+#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD 0x8000
+#define ERROR_ESBC_CLIENT_HEADER_SG 0x10000
+#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE 0x20000
+#define ERROR_ESBC_WRONG_CMD 0x40000
+#define ERROR_ESBC_MISSING_BOOTM 0x80000
+#define ERROR_ESBC_CLIENT_MAX 0x0
+
+struct fsl_secboot_errcode {
+ int errcode;
+ const char *name;
+};
+
+static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = {
+ { ERROR_ESBC_PAMU_INIT,
+ "Error in initializing PAMU"},
+ { ERROR_ESBC_SEC_RESET,
+ "Error in resetting Job ring of SEC"},
+ { ERROR_ESBC_SEC_INIT,
+ "Error in initializing SEC"},
+ { ERROR_ESBC_SEC_ENQ,
+ "Error in enqueue operation by SEC"},
+ { ERROR_ESBC_SEC_DEQ_TO,
+ "Dequeue operation by SEC is timed out"},
+ { ERROR_ESBC_SEC_DEQ,
+ "Error in dequeue operation by SEC"},
+ { ERROR_ESBC_SEC_JOBQ_STATUS,
+ "Error in status of the job submitted to SEC"},
+ { ERROR_ESBC_CLIENT_CPUID_NO_MATCH,
+ "Current core is not boot core i.e core0" },
+ { ERROR_ESBC_CLIENT_HDR_LOC,
+ "Header address not in allowed memory range" },
+ { ERROR_ESBC_CLIENT_HEADER_BARKER,
+ "Wrong barker code in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN,
+ "Wrong public key length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_LEN,
+ "Wrong signature length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN,
+ "Public key length not twice of signature length" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1,
+ "Public key Modulus most significant bit not set" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2,
+ "Public key Modulus in header not odd" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD,
+ "Signature not less than modulus" },
+ { ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP,
+ "Entry point not in allowed space or one of the SG entries" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_KEY,
+ "Public key hash comparison failed" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_EM,
+ "RSA verification failed" },
+ { ERROR_ESBC_CLIENT_SSM_TRUSTSTS,
+ "SNVS not in TRUSTED state" },
+ { ERROR_ESBC_CLIENT_BAD_ADDRESS,
+ "Bad address error" },
+ { ERROR_ESBC_CLIENT_MISC,
+ "Miscallaneous error" },
+ { ERROR_ESBC_CLIENT_HEADER_SG,
+ "No SG support" },
+ { ERROR_ESBC_CLIENT_HEADER_IMG_SIZE,
+ "Invalid Image size" },
+ { ERROR_ESBC_WRONG_CMD,
+ "Unknown cmd/Wrong arguments. Core in infinite loop"},
+ { ERROR_ESBC_MISSING_BOOTM,
+ "Bootm command missing from bootscript" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED,
+ "Selected key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY,
+ "Wrong key entry" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM,
+ "Wrong key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN,
+ "Wrong srk public key len in header" },
+ { ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED,
+ "Selected IE key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY,
+ "Wrong key entry in IE Table" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM,
+ "Wrong IE key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN,
+ "Wrong IE public key len in header" },
+ { ERROR_IE_TABLE_NOT_FOUND,
+ "Information about IE Table missing" },
+ { ERROR_ESBC_CLIENT_MAX, "NULL" }
+};
+
+void fsl_secboot_handle_error(int error);
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SFP_SNVS_
+#define _FSL_SFP_SNVS_
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SRK_LE
+#define srk_in32(a) in_le32(a)
+#else
+#define srk_in32(a) in_be32(a)
+#endif
+
+#ifdef CONFIG_SYS_FSL_SFP_LE
+#define sfp_in32(a) in_le32(a)
+#define sfp_out32(a, v) out_le32(a, v)
+#define sfp_in16(a) in_le16(a)
+#elif defined(CONFIG_SYS_FSL_SFP_BE)
+#define sfp_in32(a) in_be32(a)
+#define sfp_out32(a, v) out_be32(a, v)
+#define sfp_in16(a) in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
+#endif
+
+/* Number of SRKH registers */
+#define NUM_SRKH_REGS 8
+
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 ospr1; /* 0x204 */
+ u32 reserved1[4];
+ u32 fswpr; /* 0x218 FSL Section Write Protect */
+ u32 fsl_uid; /* 0x21c FSL UID 0 */
+ u32 fsl_uid_1; /* 0x220 FSL UID 0 */
+ u32 reserved2[12];
+ u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
+ u32 oem_uid; /* 0x274 OEM UID 0*/
+ u32 oem_uid_1; /* 0x278 OEM UID 1*/
+ u32 oem_uid_2; /* 0x27c OEM UID 2*/
+ u32 oem_uid_3; /* 0x280 OEM UID 3*/
+ u32 oem_uid_4; /* 0x284 OEM UID 4*/
+ u32 reserved3[8];
+};
+#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+
+};
+#else
+struct ccsr_sfp_regs {
+ u8 reserved0[0x40];
+ u32 ospr; /* 0x40 OEM Security Policy Register */
+ u8 reserved2[0x38];
+ u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved4[0x4];
+ u32 ovpr; /* 0xA4 OEM Validation Policy Register */
+ u8 reserved8[0x8];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+};
+#endif
+#define ITS_MASK 0x00000004
+#define ITS_BIT 2
+#define OSPR_KEY_REVOC_SHIFT 13
+#define OSPR_KEY_REVOC_MASK 0x0000e000
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_VALIDATE_H_
+#define _FSL_VALIDATE_H_
+
+#include <fsl_sec.h>
+#include <fsl_sec_mon.h>
+#include <command.h>
+#include <linux/types.h>
+
+#define WORD_SIZE 4
+
+/* Minimum and maximum size of RSA signature length in bits */
+#define KEY_SIZE 4096
+#define KEY_SIZE_BYTES (KEY_SIZE/8)
+#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE))
+
+extern struct jobring jr;
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define SRK_FLAG 0x01
+#define UNREVOCABLE_KEY 4
+#define ALIGN_REVOC_KEY 3
+#define MAX_KEY_ENTRIES 4
+#endif
+
+/* Barker code size in bytes */
+#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */
+ /* header */
+
+/* No-error return values */
+#define ESBC_VALID_HDR 0 /* header is valid */
+
+/* Maximum number of SG entries allowed */
+#define MAX_SG_ENTRIES 8
+
+/*
+ * ESBC uboot client header structure.
+ * The struct contain the following fields
+ * barker code
+ * public key offset
+ * pub key length
+ * signature offset
+ * length of the signature
+ * ptr to SG table
+ * no of entries in SG table
+ * esbc ptr
+ * size of esbc
+ * esbc entry point
+ * Scatter gather flag
+ * UID flag
+ * FSL UID
+ * OEM UID
+ * Here, pub key is modulus concatenated with exponent
+ * of equal length
+ */
+struct fsl_secboot_img_hdr {
+ u8 barker[ESBC_BARKER_LEN]; /* barker code */
+ union {
+ u32 pkey; /* public key offset */
+#ifdef CONFIG_KEY_REVOCATION
+ u32 srk_tbl_off;
+#endif
+ };
+
+ union {
+ u32 key_len; /* pub key length in bytes */
+#ifdef CONFIG_KEY_REVOCATION
+ struct {
+ u32 srk_table_flag:8;
+ u32 srk_sel:8;
+ u32 num_srk:16;
+ } len_kr;
+#endif
+ };
+
+ u32 psign; /* signature offset */
+ u32 sign_len; /* length of the signature in bytes */
+ union {
+ struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
+ u8 *pimg; /* ptr to ESBC client image */
+ };
+ union {
+ u32 sg_entries; /* no of entries in SG table */
+ u32 img_size; /* ESBC client image size in bytes */
+ };
+ ulong img_start; /* ESBC client entry point */
+ u32 sg_flag; /* Scatter gather flag */
+ u32 uid_flag;
+ u32 fsl_uid_0;
+ u32 oem_uid_0;
+ u32 reserved1[2];
+ u32 fsl_uid_1;
+ u32 oem_uid_1;
+ u32 reserved2[2];
+ u32 ie_flag;
+ u32 ie_key_sel;
+};
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+struct ie_key_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+
+struct ie_key_info {
+ uint32_t key_revok;
+ uint32_t num_keys;
+ struct ie_key_table ie_key_tbl[32];
+};
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+struct srk_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+#endif
+
+/*
+ * SG table.
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * source address
+ */
+struct fsl_secboot_sg_table {
+ u32 len; /* length of the segment in bytes */
+ ulong src_addr; /* ptr to the data segment */
+};
+#else
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct fsl_secboot_sg_table {
+ u32 len;
+ u32 trgt_id;
+ ulong src_addr;
+ ulong dst_addr;
+};
+#endif
+
+/*
+ * ESBC private structure.
+ * Private structure used by ESBC to store following fields
+ * ESBC client key
+ * ESBC client key hash
+ * ESBC client Signature
+ * Encoded hash recovered from signature
+ * Encoded hash of ESBC client header plus ESBC client image
+ */
+struct fsl_secboot_img_priv {
+ uint32_t hdr_location;
+ ulong ie_addr;
+ u32 key_len;
+ struct fsl_secboot_img_hdr hdr;
+
+ u8 img_key[2 * KEY_SIZE_BYTES]; /* ESBC client key */
+ u8 img_key_hash[32]; /* ESBC client key hash */
+
+#ifdef CONFIG_KEY_REVOCATION
+ struct srk_table srk_tbl[MAX_KEY_ENTRIES];
+#endif
+ u8 img_sign[KEY_SIZE_BYTES]; /* ESBC client signature */
+
+ u8 img_encoded_hash[KEY_SIZE_BYTES]; /* EM wrt RSA PKCSv1.5 */
+ /* Includes hash recovered after
+ * signature verification
+ */
+
+ u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */
+ /* Includes hash of
+ * ESBC client header plus
+ * ESBC client image
+ */
+
+ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
+ u32 ehdrloc; /* ESBC client location */
+};
+
+int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
+#endif
#include <asm/linkage.h>
+/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
+#ifndef ASM_NL
+#define ASM_NL ;
+#endif
+
#ifdef __cplusplus
#define CPP_ASMLINKAGE extern "C"
#else
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
- ALIGN; \
+ ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
- .globl SYMBOL_NAME(name); \
+ .globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
- .weak SYMBOL_NAME(name); \
+ .weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#ifndef END
#ifndef ENDPROC
#define ENDPROC(name) \
- .type name STT_FUNC; \
+ .type name STT_FUNC ASM_NL \
END(name)
#endif
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
+#define TPS65217_PWR_OFF 0x80
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
- char name[16]; /* Device name */
+ char name[32]; /* Device name */
/* GENERAL functions */
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
-#if defined(CONFIG_ARM)
-
DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr));
DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off));
DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
-#endif
-
return 0;
}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o rsa-mod-exp.o
+obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
define_config(m, slen, hash);
- /* printf(" $(wildcard include/config/"); */
- /* modified for U-Boot */
- printf(" $(wildcard %sinclude/config/",
- strncmp(depfile, "spl/", 4) ?
- (strncmp(depfile, "tpl/", 4) ? "" : "tpl/") : "spl/");
+ printf(" $(wildcard include/config/");
for (i = 0; i < slen; i++) {
c = m[i];
if (c == '_')
# Random bits by Matt Mackall <mpm@selenic.com>
# M68k port by Geert Uytterhoeven and Andreas Schwab
# AVR32 port by Haavard Skinnemoen (Atmel)
-# PARISC port by Kyle McMartin <kyle@parisc-linux.org>
+# AArch64, PARISC ports by Kyle McMartin
# sparc port by Martin Habets <errandir_news@mph.eclipse.co.uk>
#
# Usage:
# $1 (first bracket) matches the dynamic amount of the stack growth
#
# use anything else and feel the pain ;)
-my (@stack, $re, $dre, $x, $xs);
+my (@stack, $re, $dre, $x, $xs, $funcre);
{
my $arch = shift;
if ($arch eq "") {
$x = "[0-9a-f]"; # hex character
$xs = "[0-9a-f ]"; # hex character or space
- if ($arch eq 'arm') {
+ $funcre = qr/^$x* <(.*)>:$/;
+ if ($arch eq 'aarch64') {
+ #ffffffc0006325cc: a9bb7bfd stp x29, x30, [sp,#-80]!
+ $re = qr/^.*stp.*sp,\#-([0-9]{1,8})\]\!/o;
+ } elsif ($arch eq 'arm') {
#c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
$re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
} elsif ($arch eq 'avr32') {
#8000008a: 20 1d sub sp,4
#80000ca8: fa cd 05 b0 sub sp,sp,1456
$re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
- } elsif ($arch =~ /^i[3456]86$/) {
+ } elsif ($arch =~ /^x86(_64)?$/ || $arch =~ /^i[3456]86$/) {
#c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
- $dre = qr/^.*[as][du][db] (%.*),\%esp$/o;
- } elsif ($arch eq 'x86_64') {
- # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%rsp$/o;
- $dre = qr/^.*[as][du][db] (\%.*),\%rsp$/o;
+ # or
+ # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
+ $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o;
+ $dre = qr/^.*[as][du][db] (%.*),\%(e|r)sp$/o;
} elsif ($arch eq 'ia64') {
#e0000000044011fc: 01 0f fc 8c adds r12=-384,r12
$re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o;
# 2b6c: 4e56 fb70 linkw %fp,#-1168
# 1df770: defc ffe4 addaw #-28,%sp
$re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o;
+ } elsif ($arch eq 'metag') {
+ #400026fc: 40 00 00 82 ADD A0StP,A0StP,#0x8
+ $re = qr/.*ADD.*A0StP,A0StP,\#(0x$x{1,8})/o;
+ $funcre = qr/^$x* <[^\$](.*)>:$/;
} elsif ($arch eq 'mips64') {
#8800402c: 67bdfff0 daddiu sp,sp,-16
$re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
#
# main()
#
-my $funcre = qr/^$x* <(.*)>:$/;
my ($func, $file, $lastslash);
while (my $line = <STDIN>) {
arch = 'unknown'
str = self.col.Color(color, ' ' + target)
if not arch in done_arch:
- str = self.col.Color(color, char) + ' ' + str
+ str = ' %s %s' % (self.col.Color(color, char), str)
done_arch[arch] = True
if not arch in arch_list:
arch_list[arch] = str
expected_colour = col.GREEN if ok else col.RED
expect = '%10s: ' % arch
# TODO(sjg@chromium.org): If plus is '', we shouldn't need this
- expect += col.Color(expected_colour, plus)
+ expect += ' ' + col.Color(expected_colour, plus)
expect += ' '
for board in boards:
expect += col.Color(expected_colour, ' %s' % board)
# Check that the toolchain works
print 'Testing'
dirpath = os.path.join(dest, path)
- compiler_fname = self.ScanPath(dirpath, True)
- if not compiler_fname:
+ compiler_fname_list = self.ScanPath(dirpath, True)
+ if not compiler_fname_list:
print 'Could not locate C compiler - fetch failed.'
return 1
- toolchain = Toolchain(compiler_fname, True, True)
+ if len(compiler_fname_list) != 1:
+ print ('Internal error, ambiguous toolchains: %s' %
+ (', '.join(compiler_fname)))
+ return 1
+ toolchain = Toolchain(compiler_fname_list[0], True, True)
# Make sure that it will be found by buildman
if not self.TestSettingsHasPath(dirpath):
binhdrsz = sizeof(struct opt_hdr_v1) +
(binarye->binary.nargs + 1) * sizeof(unsigned int) +
s.st_size;
+ binhdrsz = ALIGN_SUP(binhdrsz, 32);
hdr->headersz_lsb = binhdrsz & 0xFFFF;
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
projects / u-boot / commitdiff