.width = 32,
},
};
+
+static const struct uniphier_board_data uniphier_ld21_data = {
+ .dram_freq = 1866,
+ .dram_nr_ch = 2,
+ .dram_ch[0] = {
+ .base = 0x80000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .base = 0xc0000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .flags = UNIPHIER_BD_PACKAGE_LD21,
+};
#endif
struct uniphier_board_id {
{ "socionext,ph1-ld11", &uniphier_ld11_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ { "socionext,ph1-ld21", &uniphier_ld21_data, },
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif
};
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
#define UNIPHIER_BD_DDR3PLUS BIT(2)
+#define UNIPHIER_BD_PACKAGE_LD21 1
+#define UNIPHIER_BD_PACKAGE_TYPE(f) ((f) & 0x3)
};
const struct uniphier_board_data *uniphier_get_board_param(void);