--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
+
model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
- chosen {
- stdout-path = &uart1;
- };
-
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins &mmc1_cd>;
+ cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
};
-&mmc2 {
- status = "disabled";
-};
-
&omap3_pmx_core {
gpio_key_pins: pinmux_gpio_key_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */
OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */
- OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
+ OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
+ OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
+ OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */
OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */
OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */
--- /dev/null
+/*
+ * Device Tree Source for OMAP3 SoC CPU thermal
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ coefficients = <0 20000>;
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 0>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
+
#include <dt-bindings/pinctrl/omap.h>
/ {
- compatible = "ti,omap3430", "ti,omap3";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-a8";
- device_type = "cpu";
- reg = <0x0>;
-
- clocks = <&dpll1_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
- };
- };
-
- pmu@54000000 {
- compatible = "arm,cortex-a8-pmu";
- reg = <0x54000000 0x800000>;
- interrupts = <3>;
- ti,hwmods = "debugss";
- };
-
- /*
- * The soc node represents the soc top level view. It is used for IPs
- * that are not memory mapped in the MPU view or for the MPU itself.
- */
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap3-mpu";
- ti,hwmods = "mpu";
- };
-
- iva: iva {
- compatible = "ti,iva2.2";
- ti,hwmods = "iva";
-
- dsp {
- compatible = "ti,omap3-c64";
- };
- };
- };
-
- /*
- * XXX: Use a flat representation of the OMAP3 interconnect.
- * The real OMAP interconnect network is quite complex.
- * Since it will not bring real advantage to represent that in DT for
- * the moment, just use a fake OCP bus entry to represent the whole bus
- * hierarchy.
- */
- ocp@68000000 {
- compatible = "ti,omap3-l3-smx", "simple-bus";
- reg = <0x68000000 0x10000>;
- interrupts = <9 10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "l3_main";
-
- l4_core: l4@48000000 {
- compatible = "ti,omap3-l4-core", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48000000 0x1000000>;
-
- scm: scm@2000 {
- compatible = "ti,omap3-scm", "simple-bus";
- reg = <0x2000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x2000 0x2000>;
-
- omap3_pmx_core: pinmux@30 {
- compatible = "ti,omap3-padconf",
- "pinctrl-single";
- reg = <0x30 0x238>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "syscon", "simple-bus";
- reg = <0x270 0x330>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x270 0x330>;
-
- pbias_regulator: pbias_regulator@2b0 {
- compatible = "ti,pbias-omap3", "ti,pbias-omap";
- reg = <0x2b0 0x4>;
- syscon = <&scm_conf>;
- pbias_mmc_reg: pbias_mmc_omap2430 {
- regulator-name = "pbias_mmc_omap2430";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
- };
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- scm_clockdomains: clockdomains {
- };
-
- omap3_pmx_wkup: pinmux@a00 {
- compatible = "ti,omap3-padconf",
- "pinctrl-single";
- reg = <0xa00 0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
- };
- };
-
- aes: aes@480c5000 {
- compatible = "ti,omap3-aes";
- ti,hwmods = "aes";
- reg = <0x480c5000 0x50>;
- interrupts = <0>;
- dmas = <&sdma 65 &sdma 66>;
- dma-names = "tx", "rx";
- };
-
- prm: prm@48306000 {
- compatible = "ti,omap3-prm";
- reg = <0x48306000 0x4000>;
- interrupts = <11>;
-
- prm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prm_clockdomains: clockdomains {
- };
- };
-
- cm: cm@48004000 {
- compatible = "ti,omap3-cm";
- reg = <0x48004000 0x4000>;
-
- cm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_clockdomains: clockdomains {
- };
- };
-
- counter32k: counter@48320000 {
- compatible = "ti,omap-counter32k";
- reg = <0x48320000 0x20>;
- ti,hwmods = "counter_32k";
- };
-
- intc: interrupt-controller@48200000 {
- compatible = "ti,omap3-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x48200000 0x1000>;
- };
-
- sdma: dma-controller@48056000 {
- compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <96>;
- };
-
- gpio1: gpio@48310000 {
- compatible = "ti,omap3-gpio";
- reg = <0x48310000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@49050000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49050000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@49052000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49052000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@49054000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49054000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@49056000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49056000 0x200>;
- interrupts = <33>;
- ti,hwmods = "gpio5";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio6: gpio@49058000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49058000 0x200>;
- interrupts = <34>;
- ti,hwmods = "gpio6";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart1: serial@4806a000 {
- compatible = "ti,omap3-uart";
- reg = <0x4806a000 0x2000>;
- reg-shift = <2>;
- interrupts-extended = <&intc 72>;
- dmas = <&sdma 49 &sdma 50>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart1";
- clock-frequency = <48000000>;
- };
-
- uart2: serial@4806c000 {
- compatible = "ti,omap3-uart";
- reg = <0x4806c000 0x400>;
- interrupts-extended = <&intc 73>;
- dmas = <&sdma 51 &sdma 52>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart2";
- clock-frequency = <48000000>;
- };
-
- uart3: serial@49020000 {
- compatible = "ti,omap3-uart";
- reg = <0x49020000 0x400>;
- interrupts-extended = <&intc 74>;
- dmas = <&sdma 53 &sdma 54>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart3";
- clock-frequency = <48000000>;
- };
-
- i2c1: i2c@48070000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48070000 0x80>;
- interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c1";
- };
-
- i2c2: i2c@48072000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48072000 0x80>;
- interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c2";
- };
-
- i2c3: i2c@48060000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48060000 0x80>;
- interrupts = <61>;
- dmas = <&sdma 25 &sdma 26>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c3";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap3-mailbox";
- ti,hwmods = "mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <2>;
- ti,mbox-num-fifos = <2>;
- mbox_dsp: dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- };
-
- mcspi1: spi@48098000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x48098000 0x100>;
- interrupts = <65>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi1";
- ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
-
- mcspi2: spi@4809a000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x4809a000 0x100>;
- interrupts = <66>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi2";
- ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- mcspi3: spi@480b8000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x480b8000 0x100>;
- interrupts = <91>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi3";
- ti,spi-num-cs = <2>;
- dmas = <&sdma 15>,
- <&sdma 16>,
- <&sdma 23>,
- <&sdma 24>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- mcspi4: spi@480ba000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x480ba000 0x100>;
- interrupts = <48>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi4";
- ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
- dma-names = "tx0", "rx0";
- };
-
- hdqw1w: 1w@480b2000 {
- compatible = "ti,omap3-1w";
- reg = <0x480b2000 0x1000>;
- interrupts = <58>;
- ti,hwmods = "hdq1w";
- };
-
- mmc1: mmc@4809c000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x4809c000 0x200>;
- interrupts = <83>;
- ti,hwmods = "mmc1";
- ti,dual-volt;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
-
- mmc2: mmc@480b4000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x480b4000 0x200>;
- interrupts = <86>;
- ti,hwmods = "mmc2";
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
-
- mmc3: mmc@480ad000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x480ad000 0x200>;
- interrupts = <94>;
- ti,hwmods = "mmc3";
- dmas = <&sdma 77>, <&sdma 78>;
- dma-names = "tx", "rx";
- };
-
- mmu_isp: mmu@480bd400 {
- #iommu-cells = <0>;
- compatible = "ti,omap2-iommu";
- reg = <0x480bd400 0x80>;
- interrupts = <24>;
- ti,hwmods = "mmu_isp";
- ti,#tlb-entries = <8>;
- };
-
- mmu_iva: mmu@5d000000 {
- #iommu-cells = <0>;
- compatible = "ti,omap2-iommu";
- reg = <0x5d000000 0x80>;
- interrupts = <28>;
- ti,hwmods = "mmu_iva";
- status = "disabled";
- };
-
- wdt2: wdt@48314000 {
- compatible = "ti,omap3-wdt";
- reg = <0x48314000 0x80>;
- ti,hwmods = "wd_timer2";
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <16>, /* OCP compliant interrupt */
- <59>, /* TX interrupt */
- <60>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp1_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@49022000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49022000 0xff>,
- <0x49028000 0xff>;
- reg-names = "mpu", "sidetone";
- interrupts = <17>, /* OCP compliant interrupt */
- <62>, /* TX interrupt */
- <63>, /* RX interrupt */
- <4>; /* Sidetone */
- interrupt-names = "common", "tx", "rx", "sidetone";
- ti,buffer-size = <1280>;
- ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
- clock-names = "fck", "ick";
- status = "disabled";
- };
-
- mcbsp3: mcbsp@49024000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49024000 0xff>,
- <0x4902a000 0xff>;
- reg-names = "mpu", "sidetone";
- interrupts = <22>, /* OCP compliant interrupt */
- <89>, /* TX interrupt */
- <90>, /* RX interrupt */
- <5>; /* Sidetone */
- interrupt-names = "common", "tx", "rx", "sidetone";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
- clock-names = "fck", "ick";
- status = "disabled";
- };
-
- mcbsp4: mcbsp@49026000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49026000 0xff>;
- reg-names = "mpu";
- interrupts = <23>, /* OCP compliant interrupt */
- <54>, /* TX interrupt */
- <55>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp4";
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp4_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcbsp5: mcbsp@48096000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x48096000 0xff>;
- reg-names = "mpu";
- interrupts = <27>, /* OCP compliant interrupt */
- <81>, /* TX interrupt */
- <82>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp5";
- dmas = <&sdma 21>,
- <&sdma 22>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp5_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- sham: sham@480c3000 {
- compatible = "ti,omap3-sham";
- ti,hwmods = "sham";
- reg = <0x480c3000 0x64>;
- interrupts = <49>;
- dmas = <&sdma 69>;
- dma-names = "rx";
- };
-
- smartreflex_core: smartreflex@480cb000 {
- compatible = "ti,omap3-smartreflex-core";
- ti,hwmods = "smartreflex_core";
- reg = <0x480cb000 0x400>;
- interrupts = <19>;
- };
-
- smartreflex_mpu_iva: smartreflex@480c9000 {
- compatible = "ti,omap3-smartreflex-iva";
- ti,hwmods = "smartreflex_mpu_iva";
- reg = <0x480c9000 0x400>;
- interrupts = <18>;
- };
-
- timer1: timer@48318000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48318000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- };
-
- timer2: timer@49032000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49032000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
- };
-
- timer3: timer@49034000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49034000 0x400>;
- interrupts = <39>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@49036000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49036000 0x400>;
- interrupts = <40>;
- ti,hwmods = "timer4";
- };
-
- timer5: timer@49038000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49038000 0x400>;
- interrupts = <41>;
- ti,hwmods = "timer5";
- ti,timer-dsp;
- };
-
- timer6: timer@4903a000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903a000 0x400>;
- interrupts = <42>;
- ti,hwmods = "timer6";
- ti,timer-dsp;
- };
-
- timer7: timer@4903c000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903c000 0x400>;
- interrupts = <43>;
- ti,hwmods = "timer7";
- ti,timer-dsp;
- };
-
- timer8: timer@4903e000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903e000 0x400>;
- interrupts = <44>;
- ti,hwmods = "timer8";
- ti,timer-pwm;
- ti,timer-dsp;
- };
-
- timer9: timer@49040000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49040000 0x400>;
- interrupts = <45>;
- ti,hwmods = "timer9";
- ti,timer-pwm;
- };
-
- timer10: timer@48086000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48086000 0x400>;
- interrupts = <46>;
- ti,hwmods = "timer10";
- ti,timer-pwm;
- };
-
- timer11: timer@48088000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48088000 0x400>;
- interrupts = <47>;
- ti,hwmods = "timer11";
- ti,timer-pwm;
- };
-
- timer12: timer@48304000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48304000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer12";
- ti,timer-alwon;
- ti,timer-secure;
- };
-
- usbhstll: usbhstll@48062000 {
- compatible = "ti,usbhs-tll";
- reg = <0x48062000 0x1000>;
- interrupts = <78>;
- ti,hwmods = "usb_tll_hs";
- };
-
- usbhshost: usbhshost@48064000 {
- compatible = "ti,usbhs-host";
- reg = <0x48064000 0x400>;
- ti,hwmods = "usb_host_hs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbhsohci: ohci@48064400 {
- compatible = "ti,ohci-omap3";
- reg = <0x48064400 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <76>;
- };
-
- usbhsehci: ehci@48064800 {
- compatible = "ti,ehci-omap";
- reg = <0x48064800 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <77>;
- };
- };
-
- gpmc: gpmc@6e000000 {
- compatible = "ti,omap3430-gpmc";
- ti,hwmods = "gpmc";
- reg = <0x6e000000 0x02d0>;
- interrupts = <20>;
- dmas = <&sdma 4>;
- dma-names = "rxtx";
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- usb_otg_hs: usb_otg_hs@480ab000 {
- compatible = "ti,omap3-musb";
- reg = <0x480ab000 0x1000>;
- interrupts = <92>, <93>;
- interrupt-names = "mc", "dma";
- ti,hwmods = "usb_otg_hs";
- multipoint = <1>;
- num-eps = <16>;
- ram-bits = <12>;
- };
-
- dss: dss@48050000 {
- compatible = "ti,omap3-dss";
- reg = <0x48050000 0x200>;
- status = "disabled";
- ti,hwmods = "dss_core";
- clocks = <&dss1_alwon_fck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dispc@48050400 {
- compatible = "ti,omap3-dispc";
- reg = <0x48050400 0x400>;
- interrupts = <25>;
- ti,hwmods = "dss_dispc";
- clocks = <&dss1_alwon_fck>;
- clock-names = "fck";
- };
-
- dsi: encoder@4804fc00 {
- compatible = "ti,omap3-dsi";
- reg = <0x4804fc00 0x200>,
- <0x4804fe00 0x40>,
- <0x4804ff00 0x20>;
- reg-names = "proto", "phy", "pll";
- interrupts = <25>;
- status = "disabled";
- ti,hwmods = "dss_dsi1";
- clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
- clock-names = "fck", "sys_clk";
- };
-
- rfbi: encoder@48050800 {
- compatible = "ti,omap3-rfbi";
- reg = <0x48050800 0x100>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- clocks = <&dss1_alwon_fck>, <&dss_ick>;
- clock-names = "fck", "ick";
- };
-
- venc: encoder@48050c00 {
- compatible = "ti,omap3-venc";
- reg = <0x48050c00 0x100>;
- status = "disabled";
- ti,hwmods = "dss_venc";
- clocks = <&dss_tv_fck>;
- clock-names = "fck";
- };
- };
-
- ssi: ssi-controller@48058000 {
- compatible = "ti,omap3-ssi";
- ti,hwmods = "ssi";
-
- status = "disabled";
-
- reg = <0x48058000 0x1000>,
- <0x48059000 0x1000>;
- reg-names = "sys",
- "gdd";
-
- interrupts = <71>;
- interrupt-names = "gdd_mpu";
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- ssi_port1: ssi-port@4805a000 {
- compatible = "ti,omap3-ssi-port";
-
- reg = <0x4805a000 0x800>,
- <0x4805a800 0x800>;
- reg-names = "tx",
- "rx";
-
- interrupt-parent = <&intc>;
- interrupts = <67>,
- <68>;
- };
-
- ssi_port2: ssi-port@4805b000 {
- compatible = "ti,omap3-ssi-port";
-
- reg = <0x4805b000 0x800>,
- <0x4805b800 0x800>;
- reg-names = "tx",
- "rx";
-
- interrupt-parent = <&intc>;
- interrupts = <69>,
- <70>;
- };
- };
- };
+ compatible = "ti,omap3430", "ti,omap3";
+ interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
+
+ clocks = <&dpll1_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ };
+
+ pmu@54000000 {
+ compatible = "arm,cortex-a8-pmu";
+ reg = <0x54000000 0x800000>;
+ interrupts = <3>;
+ ti,hwmods = "debugss";
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+
+ iva: iva {
+ compatible = "ti,iva2.2";
+ ti,hwmods = "iva";
+
+ dsp {
+ compatible = "ti,omap3-c64";
+ };
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP3 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp@68000000 {
+ compatible = "ti,omap3-l3-smx", "simple-bus";
+ reg = <0x68000000 0x10000>;
+ interrupts = <9 10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ l4_core: l4@48000000 {
+ compatible = "ti,omap3-l4-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48000000 0x1000000>;
+
+ scm: scm@2000 {
+ compatible = "ti,omap3-scm", "simple-bus";
+ reg = <0x2000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ omap3_pmx_core: pinmux@30 {
+ compatible = "ti,omap3-padconf",
+ "pinctrl-single";
+ reg = <0x30 0x238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x270 0x330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x270 0x330>;
+
+ pbias_regulator: pbias_regulator@2b0 {
+ compatible = "ti,pbias-omap3", "ti,pbias-omap";
+ reg = <0x2b0 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap2430 {
+ regulator-name = "pbias_mmc_omap2430";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+
+ omap3_pmx_wkup: pinmux@a00 {
+ compatible = "ti,omap3-padconf",
+ "pinctrl-single";
+ reg = <0xa00 0x5c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+ };
+ };
+
+ aes: aes@480c5000 {
+ compatible = "ti,omap3-aes";
+ ti,hwmods = "aes";
+ reg = <0x480c5000 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 65 &sdma 66>;
+ dma-names = "tx", "rx";
+ };
+
+ prm: prm@48306000 {
+ compatible = "ti,omap3-prm";
+ reg = <0x48306000 0x4000>;
+ interrupts = <11>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+
+ cm: cm@48004000 {
+ compatible = "ti,omap3-cm";
+ reg = <0x48004000 0x4000>;
+
+ cm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_clockdomains: clockdomains {
+ };
+ };
+
+ counter32k: counter@48320000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x48320000 0x20>;
+ ti,hwmods = "counter_32k";
+ };
+
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,omap3-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x48200000 0x1000>;
+ };
+
+ sdma: dma-controller@48056000 {
+ compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
+ reg = <0x48056000 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <96>;
+ };
+
+ gpio1: gpio@48310000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x48310000 0x200>;
+ interrupts = <29>;
+ ti,hwmods = "gpio1";
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@49050000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49050000 0x200>;
+ interrupts = <30>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@49052000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49052000 0x200>;
+ interrupts = <31>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@49054000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49054000 0x200>;
+ interrupts = <32>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@49056000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49056000 0x200>;
+ interrupts = <33>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@49058000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49058000 0x200>;
+ interrupts = <34>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x4806a000 0x2000>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 72>;
+ dmas = <&sdma 49 &sdma 50>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x4806c000 0x400>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 73>;
+ dmas = <&sdma 51 &sdma 52>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@49020000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49020000 0x400>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 74>;
+ dmas = <&sdma 53 &sdma 54>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48070000 0x80>;
+ interrupts = <56>;
+ dmas = <&sdma 27 &sdma 28>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48072000 0x80>;
+ interrupts = <57>;
+ dmas = <&sdma 29 &sdma 30>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48060000 0x80>;
+ interrupts = <61>;
+ dmas = <&sdma 25 &sdma 26>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ mailbox: mailbox@48094000 {
+ compatible = "ti,omap3-mailbox";
+ ti,hwmods = "mailbox";
+ reg = <0x48094000 0x200>;
+ interrupts = <26>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <2>;
+ ti,mbox-num-fifos = <2>;
+ mbox_dsp: dsp {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ };
+
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x48098000 0x100>;
+ interrupts = <65>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x4809a000 0x100>;
+ interrupts = <66>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x480b8000 0x100>;
+ interrupts = <91>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>,
+ <&sdma 16>,
+ <&sdma 23>,
+ <&sdma 24>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x480ba000 0x100>;
+ interrupts = <48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+
+ hdqw1w: 1w@480b2000 {
+ compatible = "ti,omap3-1w";
+ reg = <0x480b2000 0x1000>;
+ interrupts = <58>;
+ ti,hwmods = "hdq1w";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x4809c000 0x200>;
+ interrupts = <83>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x480b4000 0x200>;
+ interrupts = <86>;
+ ti,hwmods = "mmc2";
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x480ad000 0x200>;
+ interrupts = <94>;
+ ti,hwmods = "mmc3";
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+
+ mmu_isp: mmu@480bd400 {
+ #iommu-cells = <0>;
+ compatible = "ti,omap2-iommu";
+ reg = <0x480bd400 0x80>;
+ interrupts = <24>;
+ ti,hwmods = "mmu_isp";
+ ti,#tlb-entries = <8>;
+ };
+
+ mmu_iva: mmu@5d000000 {
+ #iommu-cells = <0>;
+ compatible = "ti,omap2-iommu";
+ reg = <0x5d000000 0x80>;
+ interrupts = <28>;
+ ti,hwmods = "mmu_iva";
+ status = "disabled";
+ };
+
+ wdt2: wdt@48314000 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x48314000 0x80>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ mcbsp1: mcbsp@48074000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48074000 0xff>;
+ reg-names = "mpu";
+ interrupts = <16>, /* OCP compliant interrupt */
+ <59>, /* TX interrupt */
+ <60>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ dmas = <&sdma 31>,
+ <&sdma 32>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp1_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcbsp2: mcbsp@49022000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49022000 0xff>,
+ <0x49028000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <17>, /* OCP compliant interrupt */
+ <62>, /* TX interrupt */
+ <63>, /* RX interrupt */
+ <4>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ ti,buffer-size = <1280>;
+ ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
+ clock-names = "fck", "ick";
+ status = "disabled";
+ };
+
+ mcbsp3: mcbsp@49024000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49024000 0xff>,
+ <0x4902a000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <22>, /* OCP compliant interrupt */
+ <89>, /* TX interrupt */
+ <90>, /* RX interrupt */
+ <5>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
+ clock-names = "fck", "ick";
+ status = "disabled";
+ };
+
+ mcbsp4: mcbsp@49026000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49026000 0xff>;
+ reg-names = "mpu";
+ interrupts = <23>, /* OCP compliant interrupt */
+ <54>, /* TX interrupt */
+ <55>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp4";
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp4_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcbsp5: mcbsp@48096000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48096000 0xff>;
+ reg-names = "mpu";
+ interrupts = <27>, /* OCP compliant interrupt */
+ <81>, /* TX interrupt */
+ <82>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp5";
+ dmas = <&sdma 21>,
+ <&sdma 22>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp5_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ sham: sham@480c3000 {
+ compatible = "ti,omap3-sham";
+ ti,hwmods = "sham";
+ reg = <0x480c3000 0x64>;
+ interrupts = <49>;
+ dmas = <&sdma 69>;
+ dma-names = "rx";
+ };
+
+ smartreflex_core: smartreflex@480cb000 {
+ compatible = "ti,omap3-smartreflex-core";
+ ti,hwmods = "smartreflex_core";
+ reg = <0x480cb000 0x400>;
+ interrupts = <19>;
+ };
+
+ smartreflex_mpu_iva: smartreflex@480c9000 {
+ compatible = "ti,omap3-smartreflex-iva";
+ ti,hwmods = "smartreflex_mpu_iva";
+ reg = <0x480c9000 0x400>;
+ interrupts = <18>;
+ };
+
+ timer1: timer@48318000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48318000 0x400>;
+ interrupts = <37>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@49032000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49032000 0x400>;
+ interrupts = <38>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@49034000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49034000 0x400>;
+ interrupts = <39>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@49036000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49036000 0x400>;
+ interrupts = <40>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@49038000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49038000 0x400>;
+ interrupts = <41>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@4903a000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903a000 0x400>;
+ interrupts = <42>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ };
+
+ timer7: timer@4903c000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903c000 0x400>;
+ interrupts = <43>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@4903e000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903e000 0x400>;
+ interrupts = <44>;
+ ti,hwmods = "timer8";
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+
+ timer9: timer@49040000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49040000 0x400>;
+ interrupts = <45>;
+ ti,hwmods = "timer9";
+ ti,timer-pwm;
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48086000 0x400>;
+ interrupts = <46>;
+ ti,hwmods = "timer10";
+ ti,timer-pwm;
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48088000 0x400>;
+ interrupts = <47>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ timer12: timer@48304000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48304000 0x400>;
+ interrupts = <95>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
+
+ usbhstll: usbhstll@48062000 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x48062000 0x1000>;
+ interrupts = <78>;
+ ti,hwmods = "usb_tll_hs";
+ };
+
+ usbhshost: usbhshost@48064000 {
+ compatible = "ti,usbhs-host";
+ reg = <0x48064000 0x400>;
+ ti,hwmods = "usb_host_hs";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbhsohci: ohci@48064400 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x48064400 0x400>;
+ interrupt-parent = <&intc>;
+ interrupts = <76>;
+ };
+
+ usbhsehci: ehci@48064800 {
+ compatible = "ti,ehci-omap";
+ reg = <0x48064800 0x400>;
+ interrupt-parent = <&intc>;
+ interrupts = <77>;
+ };
+ };
+
+ gpmc: gpmc@6e000000 {
+ compatible = "ti,omap3430-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x6e000000 0x02d0>;
+ interrupts = <20>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ usb_otg_hs: usb_otg_hs@480ab000 {
+ compatible = "ti,omap3-musb";
+ reg = <0x480ab000 0x1000>;
+ interrupts = <92>, <93>;
+ interrupt-names = "mc", "dma";
+ ti,hwmods = "usb_otg_hs";
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ };
+
+ dss: dss@48050000 {
+ compatible = "ti,omap3-dss";
+ reg = <0x48050000 0x200>;
+ status = "disabled";
+ ti,hwmods = "dss_core";
+ clocks = <&dss1_alwon_fck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dispc@48050400 {
+ compatible = "ti,omap3-dispc";
+ reg = <0x48050400 0x400>;
+ interrupts = <25>;
+ ti,hwmods = "dss_dispc";
+ clocks = <&dss1_alwon_fck>;
+ clock-names = "fck";
+ };
+
+ dsi: encoder@4804fc00 {
+ compatible = "ti,omap3-dsi";
+ reg = <0x4804fc00 0x200>,
+ <0x4804fe00 0x40>,
+ <0x4804ff00 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <25>;
+ status = "disabled";
+ ti,hwmods = "dss_dsi1";
+ clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
+ clock-names = "fck", "sys_clk";
+ };
+
+ rfbi: encoder@48050800 {
+ compatible = "ti,omap3-rfbi";
+ reg = <0x48050800 0x100>;
+ status = "disabled";
+ ti,hwmods = "dss_rfbi";
+ clocks = <&dss1_alwon_fck>, <&dss_ick>;
+ clock-names = "fck", "ick";
+ };
+
+ venc: encoder@48050c00 {
+ compatible = "ti,omap3-venc";
+ reg = <0x48050c00 0x100>;
+ status = "disabled";
+ ti,hwmods = "dss_venc";
+ clocks = <&dss_tv_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ ssi: ssi-controller@48058000 {
+ compatible = "ti,omap3-ssi";
+ ti,hwmods = "ssi";
+
+ status = "disabled";
+
+ reg = <0x48058000 0x1000>,
+ <0x48059000 0x1000>;
+ reg-names = "sys",
+ "gdd";
+
+ interrupts = <71>;
+ interrupt-names = "gdd_mpu";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ssi_port1: ssi-port@4805a000 {
+ compatible = "ti,omap3-ssi-port";
+
+ reg = <0x4805a000 0x800>,
+ <0x4805a800 0x800>;
+ reg-names = "tx",
+ "rx";
+
+ interrupt-parent = <&intc>;
+ interrupts = <67>,
+ <68>;
+ };
+
+ ssi_port2: ssi-port@4805b000 {
+ compatible = "ti,omap3-ssi-port";
+
+ reg = <0x4805b000 0x800>,
+ <0x4805b800 0x800>;
+ reg-names = "tx",
+ "rx";
+
+ interrupt-parent = <&intc>;
+ interrupts = <69>,
+ <70>;
+ };
+ };
+ };
};
/include/ "omap3xxx-clocks.dtsi"
* published by the Free Software Foundation.
*/
&cm_clocks {
- security_l4_ick2: security_l4_ick2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- aes1_ick: aes1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- ti,bit-shift = <3>;
- reg = <0x0a14>;
- };
+ aes1_ick: aes1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ reg = <0x0a14>;
+ };
- rng_ick: rng_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <2>;
- };
+ rng_ick: rng_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <2>;
+ };
- sha11_ick: sha11_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <1>;
- };
+ sha11_ick: sha11_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <1>;
+ };
- des1_ick: des1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <0>;
- };
+ des1_ick: des1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <0>;
+ };
- cam_mclk: cam_mclk@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m5x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0f00>;
- ti,set-rate-parent;
- };
+ cam_mclk: cam_mclk@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0f00>;
+ ti,set-rate-parent;
+ };
- cam_ick: cam_ick@f10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x0f10>;
- ti,bit-shift = <0>;
- };
+ cam_ick: cam_ick@f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x0f10>;
+ ti,bit-shift = <0>;
+ };
- csi2_96m_fck: csi2_96m_fck@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0f00>;
- ti,bit-shift = <1>;
- };
+ csi2_96m_fck: csi2_96m_fck@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0f00>;
+ ti,bit-shift = <1>;
+ };
- security_l3_ick: security_l3_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- pka_ick: pka_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l3_ick>;
- reg = <0x0a14>;
- ti,bit-shift = <4>;
- };
+ pka_ick: pka_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x0a14>;
+ ti,bit-shift = <4>;
+ };
- icr_ick: icr_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <29>;
- };
+ icr_ick: icr_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <29>;
+ };
- des2_ick: des2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <26>;
- };
+ des2_ick: des2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <26>;
+ };
- mspro_ick: mspro_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
+ mspro_ick: mspro_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <23>;
+ };
- mailboxes_ick: mailboxes_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <7>;
- };
+ mailboxes_ick: mailboxes_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <7>;
+ };
- ssi_l4_ick: ssi_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- sr1_fck: sr1_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <6>;
- };
+ sr1_fck: sr1_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <6>;
+ };
- sr2_fck: sr2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <7>;
- };
+ sr2_fck: sr2_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <7>;
+ };
- sr_l4_ick: sr_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ sr_l4_ick: sr_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- dpll2_fck: dpll2_fck@40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <19>;
- ti,max-div = <7>;
- reg = <0x0040>;
- ti,index-starts-at-one;
- };
+ dpll2_fck: dpll2_fck@40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x0040>;
+ ti,index-starts-at-one;
+ };
- dpll2_ck: dpll2_ck@4 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&dpll2_fck>;
- reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
- ti,low-power-stop;
- ti,lock;
- ti,low-power-bypass;
- };
+ dpll2_ck: dpll2_ck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+ ti,low-power-stop;
+ ti,lock;
+ ti,low-power-bypass;
+ };
- dpll2_m2_ck: dpll2_m2_ck@44 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll2_ck>;
- ti,max-div = <31>;
- reg = <0x0044>;
- ti,index-starts-at-one;
- };
+ dpll2_m2_ck: dpll2_m2_ck@44 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0044>;
+ ti,index-starts-at-one;
+ };
- iva2_ck: iva2_ck@0 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&dpll2_m2_ck>;
- reg = <0x0000>;
- ti,bit-shift = <0>;
- };
+ iva2_ck: iva2_ck@0 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll2_m2_ck>;
+ reg = <0x0000>;
+ ti,bit-shift = <0>;
+ };
- modem_fck: modem_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- reg = <0x0a00>;
- ti,bit-shift = <31>;
- };
+ modem_fck: modem_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <31>;
+ };
- sad2d_ick: sad2d_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <3>;
- };
+ sad2d_ick: sad2d_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <3>;
+ };
- mad2d_ick: mad2d_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <3>;
- };
+ mad2d_ick: mad2d_ick@a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0a18>;
+ ti,bit-shift = <3>;
+ };
- mspro_fck: mspro_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
- };
+ mspro_fck: mspro_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <23>;
+ };
};
&cm_clockdomains {
- cam_clkdm: cam_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_ick>, <&csi2_96m_fck>;
- };
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_ick>, <&csi2_96m_fck>;
+ };
- iva2_clkdm: iva2_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&iva2_ck>;
- };
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
- dpll2_clkdm: dpll2_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll2_ck>;
- };
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
- };
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+ };
- d2d_clkdm: d2d_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
- };
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+ };
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
- <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
- <&mspro_fck>;
- };
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+ <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+ <&mspro_fck>;
+ };
};
* published by the Free Software Foundation.
*/
&prm_clocks {
- corex2_d3_fck: corex2_d3_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&corex2_fck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- corex2_d5_fck: corex2_d5_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&corex2_fck>;
- clock-mult = <1>;
- clock-div = <5>;
- };
+ corex2_d3_fck: corex2_d3_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ corex2_d5_fck: corex2_d5_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+ };
};
&cm_clocks {
- dpll5_ck: dpll5_ck@d04 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
- ti,low-power-stop;
- ti,lock;
- };
-
- dpll5_m2_ck: dpll5_m2_ck@d50 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll5_ck>;
- ti,max-div = <31>;
- reg = <0x0d50>;
- ti,index-starts-at-one;
- };
-
- sgx_gate_fck: sgx_gate_fck@b00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <1>;
- reg = <0x0b00>;
- };
-
- core_d3_ck: core_d3_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- core_d4_ck: core_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- core_d6_ck: core_d6_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <6>;
- };
-
- omap_192m_alwon_fck: omap_192m_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- core_d2_ck: core_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- sgx_mux_fck: sgx_mux_fck@b40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
- reg = <0x0b40>;
- };
-
- sgx_fck: sgx_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
- };
-
- sgx_ick: sgx_ick@b10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&l3_ick>;
- reg = <0x0b10>;
- ti,bit-shift = <0>;
- };
-
- cpefuse_fck: cpefuse_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0a08>;
- ti,bit-shift = <0>;
- };
-
- ts_fck: ts_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_32k_fck>;
- reg = <0x0a08>;
- ti,bit-shift = <1>;
- };
-
- usbtll_fck: usbtll_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&dpll5_m2_ck>;
- reg = <0x0a08>;
- ti,bit-shift = <2>;
- };
-
- usbtll_ick: usbtll_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <2>;
- };
-
- mmchs3_ick: mmchs3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <30>;
- };
-
- mmchs3_fck: mmchs3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <30>;
- };
-
- dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
- #clock-cells = <0>;
- compatible = "ti,dss-gate-clock";
- clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0e00>;
- ti,set-rate-parent;
- };
-
- dss_ick: dss_ick_3430es2@e10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dss-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x0e10>;
- ti,bit-shift = <0>;
- };
-
- usbhost_120m_fck: usbhost_120m_fck@1400 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll5_m2_ck>;
- reg = <0x1400>;
- ti,bit-shift = <1>;
- };
-
- usbhost_48m_fck: usbhost_48m_fck@1400 {
- #clock-cells = <0>;
- compatible = "ti,dss-gate-clock";
- clocks = <&omap_48m_fck>;
- reg = <0x1400>;
- ti,bit-shift = <0>;
- };
-
- usbhost_ick: usbhost_ick@1410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dss-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x1410>;
- ti,bit-shift = <0>;
- };
+ dpll5_ck: dpll5_ck@d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+ ti,low-power-stop;
+ ti,lock;
+ };
+
+ dpll5_m2_ck: dpll5_m2_ck@d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ ti,max-div = <31>;
+ reg = <0x0d50>;
+ ti,index-starts-at-one;
+ };
+
+ sgx_gate_fck: sgx_gate_fck@b00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0b00>;
+ };
+
+ core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+ };
+
+ omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ sgx_mux_fck: sgx_mux_fck@b40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+ reg = <0x0b40>;
+ };
+
+ sgx_fck: sgx_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+ };
+
+ sgx_ick: sgx_ick@b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0b10>;
+ ti,bit-shift = <0>;
+ };
+
+ cpefuse_fck: cpefuse_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <0>;
+ };
+
+ ts_fck: ts_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_32k_fck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <1>;
+ };
+
+ usbtll_fck: usbtll_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <2>;
+ };
+
+ usbtll_ick: usbtll_ick@a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a18>;
+ ti,bit-shift = <2>;
+ };
+
+ mmchs3_ick: mmchs3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <30>;
+ };
+
+ mmchs3_fck: mmchs3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <30>;
+ };
+
+ dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0e00>;
+ ti,set-rate-parent;
+ };
+
+ dss_ick: dss_ick_3430es2@e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x0e10>;
+ ti,bit-shift = <0>;
+ };
+
+ usbhost_120m_fck: usbhost_120m_fck@1400 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x1400>;
+ ti,bit-shift = <1>;
+ };
+
+ usbhost_48m_fck: usbhost_48m_fck@1400 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&omap_48m_fck>;
+ reg = <0x1400>;
+ ti,bit-shift = <0>;
+ };
+
+ usbhost_ick: usbhost_ick@1410 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x1410>;
+ ti,bit-shift = <0>;
+ };
};
&cm_clockdomains {
- dpll5_clkdm: dpll5_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll5_ck>;
- };
-
- sgx_clkdm: sgx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sgx_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
- <&dss1_alwon_fck>, <&dss_ick>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
- };
-
- usbhost_clkdm: usbhost_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
- <&usbhost_ick>;
- };
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss1_alwon_fck>, <&dss_ick>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+ <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+ <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+ };
+
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+ <&usbhost_ick>;
+ };
};
* published by the Free Software Foundation.
*/
&cm_clocks {
- dpll4_ck: dpll4_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-per-j-type-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
- };
+ dpll4_ck: dpll4_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-j-type-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+ };
- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m5x2_mul_ck>;
- ti,bit-shift = <0x1e>;
- reg = <0x0d00>;
- ti,set-rate-parent;
- ti,set-bit-to-disable;
- };
+ dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x0d00>;
+ ti,set-rate-parent;
+ ti,set-bit-to-disable;
+ };
- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m2x2_mul_ck>;
- ti,bit-shift = <0x1b>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll3_m3x2_mul_ck>;
- ti,bit-shift = <0xc>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m3x2_mul_ck>;
- ti,bit-shift = <0x1c>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m6x2_mul_ck>;
- ti,bit-shift = <0x1f>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- uart4_fck: uart4_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
- reg = <0x1000>;
- ti,bit-shift = <18>;
- };
+ uart4_fck: uart4_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <18>;
+ };
};
&dpll4_m2x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&dpll4_m3x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&dpll4_m4x2_mul_ck {
- ti,clock-mult = <1>;
+ ti,clock-mult = <1>;
};
&dpll4_m5x2_mul_ck {
- ti,clock-mult = <1>;
+ ti,clock-mult = <1>;
};
&dpll4_m6x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&cm_clockdomains {
- dpll4_clkdm: dpll4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll4_ck>;
- };
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
- per_clkdm: per_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>, <&uart4_fck>;
- };
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+ <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+ <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+ <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+ <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+ <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+ <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+ <&mcbsp4_ick>, <&uart4_fck>;
+ };
};
* published by the Free Software Foundation.
*/
&cm_clocks {
- ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
- reg = <0x0a00>;
- };
-
- ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
- reg = <0x0a40>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
- };
-
- ssi_ssr_fck: ssi_ssr_fck_3430es2 {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
- };
-
- ssi_sst_fck: ssi_sst_fck_3430es2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&ssi_ssr_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-hsotgusb-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
- };
-
- ssi_l4_ick: ssi_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- ssi_ick: ssi_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-ssi-interface-clock";
- clocks = <&ssi_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <0>;
- };
-
- usim_gate_fck: usim_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&omap_96m_fck>;
- ti,bit-shift = <9>;
- reg = <0x0c00>;
- };
-
- sys_d2_ck: sys_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_96m_d2_fck: omap_96m_d2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_96m_d4_fck: omap_96m_d4_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- omap_96m_d8_fck: omap_96m_d8_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- omap_96m_d10_fck: omap_96m_d10_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <10>;
- };
-
- dpll5_m2_d4_ck: dpll5_m2_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- dpll5_m2_d8_ck: dpll5_m2_d8_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- dpll5_m2_d16_ck: dpll5_m2_d16_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dpll5_m2_d20_ck: dpll5_m2_d20_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <20>;
- };
-
- usim_mux_fck: usim_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
- ti,bit-shift = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
- };
-
- usim_fck: usim_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&usim_gate_fck>, <&usim_mux_fck>;
- };
-
- usim_ick: usim_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <9>;
- };
+ ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <0>;
+ reg = <0x0a00>;
+ };
+
+ ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <8>;
+ reg = <0x0a40>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ };
+
+ ssi_ssr_fck: ssi_ssr_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+ };
+
+ ssi_sst_fck: ssi_sst_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <4>;
+ };
+
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ ssi_ick: ssi_ick_3430es2@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <0>;
+ };
+
+ usim_gate_fck: usim_gate_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&omap_96m_fck>;
+ ti,bit-shift = <9>;
+ reg = <0x0c00>;
+ };
+
+ sys_d2_ck: sys_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_96m_d2_fck: omap_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_96m_d4_fck: omap_96m_d4_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ omap_96m_d8_fck: omap_96m_d8_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ omap_96m_d10_fck: omap_96m_d10_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <10>;
+ };
+
+ dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <20>;
+ };
+
+ usim_mux_fck: usim_mux_fck@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0c40>;
+ ti,index-starts-at-one;
+ };
+
+ usim_fck: usim_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+ };
+
+ usim_ick: usim_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <9>;
+ };
};
&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>, <&usim_ick>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
- <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&ssi_ick>;
- };
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>, <&usim_ick>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+ <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+ <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+ <&ssi_ick>;
+ };
};
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&uart4 {
+ reg-shift = <2>;
+};
#include "omap3.dtsi"
/ {
- aliases {
- serial3 = &uart4;
- };
+ aliases {
+ serial3 = &uart4;
+ };
- cpus {
- /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
- cpu@0 {
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- >;
- clock-latency = <300000>; /* From legacy driver */
- };
- };
+ cpus {
+ /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+ cpu: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 300000 1012500
+ 600000 1200000
+ 800000 1325000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
- ocp@68000000 {
- uart4: serial@49042000 {
- compatible = "ti,omap3-uart";
- reg = <0x49042000 0x400>;
- interrupts = <80>;
- dmas = <&sdma 81 &sdma 82>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- };
+ ocp@68000000 {
+ uart4: serial@49042000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49042000 0x400>;
+ reg-shift = <2>;
+ interrupts = <80>;
+ dmas = <&sdma 81 &sdma 82>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
- abb_mpu_iva: regulator-abb-mpu {
- compatible = "ti,abb-v1";
- regulator-name = "abb_mpu_iva";
- #address-cells = <0>;
- #size-cells = <0>;
- reg = <0x483072f0 0x8>, <0x48306818 0x4>;
- reg-names = "base-address", "int-address";
- ti,tranxdone-status-mask = <0x4000000>;
- clocks = <&sys_ck>;
- ti,settling-time = <30>;
- ti,clock-cycles = <8>;
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1012500 0 0 0 0 0
- 1200000 0 0 0 0 0
- 1325000 0 0 0 0 0
- 1375000 1 0 0 0 0
- >;
- };
+ abb_mpu_iva: regulator-abb-mpu {
+ compatible = "ti,abb-v1";
+ regulator-name = "abb_mpu_iva";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+ reg-names = "base-address", "int-address";
+ ti,tranxdone-status-mask = <0x4000000>;
+ clocks = <&sys_ck>;
+ ti,settling-time = <30>;
+ ti,clock-cycles = <8>;
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1012500 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1325000 0 0 0 0 0
+ 1375000 1 0 0 0 0
+ >;
+ };
- omap3_pmx_core2: pinmux@480025a0 {
- compatible = "ti,omap3-padconf", "pinctrl-single";
- reg = <0x480025a0 0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
+ omap3_pmx_core2: pinmux@480025a0 {
+ compatible = "ti,omap3-padconf", "pinctrl-single";
+ reg = <0x480025a0 0x5c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
- isp: isp@480bc000 {
- compatible = "ti,omap3-isp";
- reg = <0x480bc000 0x12fc
- 0x480bd800 0x0600>;
- interrupts = <24>;
- iommus = <&mmu_isp>;
- syscon = <&scm_conf 0x2f0>;
- ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
- #clock-cells = <1>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
+ isp: isp@480bc000 {
+ compatible = "ti,omap3-isp";
+ reg = <0x480bc000 0x12fc
+ 0x480bd800 0x0600>;
+ interrupts = <24>;
+ iommus = <&mmu_isp>;
+ syscon = <&scm_conf 0x2f0>;
+ ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+ #clock-cells = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
- bandgap@48002524 {
- reg = <0x48002524 0x4>;
- compatible = "ti,omap36xx-bandgap";
- #thermal-sensor-cells = <0>;
- };
- };
+ bandgap: bandgap@48002524 {
+ reg = <0x48002524 0x4>;
+ compatible = "ti,omap36xx-bandgap";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ #include "omap3-cpu-thermal.dtsi"
+ };
};
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
- clocks = <&dss_tv_fck>, <&dss_96m_fck>;
- clock-names = "fck", "tv_dac_clk";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>;
+ clock-names = "fck", "tv_dac_clk";
};
&ssi {
- status = "ok";
+ status = "ok";
- clocks = <&ssi_ssr_fck>,
- <&ssi_sst_fck>,
- <&ssi_ick>;
- clock-names = "ssi_ssr_fck",
- "ssi_sst_fck",
- "ssi_ick";
+ clocks = <&ssi_ssr_fck>,
+ <&ssi_sst_fck>,
+ <&ssi_ick>;
+ clock-names = "ssi_ssr_fck",
+ "ssi_sst_fck",
+ "ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
* published by the Free Software Foundation.
*/
&prm_clocks {
- virt_16_8m_ck: virt_16_8m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16800000>;
- };
-
- osc_sys_ck: osc_sys_ck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
- reg = <0x0d40>;
- };
-
- sys_ck: sys_ck@1270 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&osc_sys_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x1270>;
- ti,index-starts-at-one;
- };
-
- sys_clkout1: sys_clkout1@d70 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&osc_sys_ck>;
- reg = <0x0d70>;
- ti,bit-shift = <7>;
- };
-
- dpll3_x2_ck: dpll3_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll3_m2x2_ck: dpll3_m2x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_x2_ck: dpll4_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- corex2_fck: corex2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wkup_l4_ick: wkup_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ virt_16_8m_ck: virt_16_8m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ osc_sys_ck: osc_sys_ck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+ reg = <0x0d40>;
+ };
+
+ sys_ck: sys_ck@1270 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&osc_sys_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x1270>;
+ ti,index-starts-at-one;
+ };
+
+ sys_clkout1: sys_clkout1@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&osc_sys_ck>;
+ reg = <0x0d70>;
+ ti,bit-shift = <7>;
+ };
+
+ dpll3_x2_ck: dpll3_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll3_m2x2_ck: dpll3_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_x2_ck: dpll4_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ corex2_fck: corex2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wkup_l4_ick: wkup_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
};
&scm_clocks {
- mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x68>;
- };
-
- mcbsp5_fck: mcbsp5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
- };
-
- mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x04>;
- };
-
- mcbsp1_fck: mcbsp1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
- };
-
- mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
- reg = <0x04>;
- };
-
- mcbsp2_fck: mcbsp2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
- };
-
- mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- reg = <0x68>;
- };
-
- mcbsp3_fck: mcbsp3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
- };
-
- mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x68>;
- };
-
- mcbsp4_fck: mcbsp4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
- };
+ mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <4>;
+ reg = <0x68>;
+ };
+
+ mcbsp5_fck: mcbsp5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+ };
+
+ mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x04>;
+ };
+
+ mcbsp1_fck: mcbsp1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+ };
+
+ mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <6>;
+ reg = <0x04>;
+ };
+
+ mcbsp2_fck: mcbsp2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+ };
+
+ mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ reg = <0x68>;
+ };
+
+ mcbsp3_fck: mcbsp3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+ };
+
+ mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x68>;
+ };
+
+ mcbsp4_fck: mcbsp4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+ };
};
&cm_clocks {
- dummy_apb_pclk: dummy_apb_pclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- omap_32k_fck: omap_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12m_ck: virt_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13m_ck: virt_13m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26000000_ck: virt_26000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- virt_38_4m_ck: virt_38_4m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- };
-
- dpll4_ck: dpll4_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-per-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
- };
-
- dpll4_m2_ck: dpll4_m2_ck@d48 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <63>;
- reg = <0x0d48>;
- ti,index-starts-at-one;
- };
-
- dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m2x2_mul_ck>;
- ti,bit-shift = <0x1b>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- omap_96m_alwon_fck: omap_96m_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll3_ck: dpll3_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-core-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
- };
-
- dpll3_m3_ck: dpll3_m3_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <31>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll3_m3x2_mul_ck>;
- ti,bit-shift = <0xc>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- emu_core_alwon_ck: emu_core_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sys_altclk: sys_altclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- mcbsp_clks: mcbsp_clks {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- dpll3_m2_ck: dpll3_m2_ck@d40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <31>;
- reg = <0x0d40>;
- ti,index-starts-at-one;
- };
-
- core_ck: core_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll1_fck: dpll1_fck@940 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <19>;
- ti,max-div = <7>;
- reg = <0x0940>;
- ti,index-starts-at-one;
- };
-
- dpll1_ck: dpll1_ck@904 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&dpll1_fck>;
- reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
- };
-
- dpll1_x2_ck: dpll1_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll1_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll1_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0944>;
- ti,index-starts-at-one;
- };
-
- cm_96m_fck: cm_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_alwon_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- omap_96m_fck: omap_96m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0d40>;
- };
-
- dpll4_m3_ck: dpll4_m3_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m3x2_mul_ck>;
- ti,bit-shift = <0x1c>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- omap_54m_fck: omap_54m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
- ti,bit-shift = <5>;
- reg = <0x0d40>;
- };
-
- cm_96m_d2_fck: cm_96m_d2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&cm_96m_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_48m_fck: omap_48m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
- ti,bit-shift = <3>;
- reg = <0x0d40>;
- };
-
- omap_12m_fck: omap_12m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- dpll4_m4_ck: dpll4_m4_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&dpll4_m4_ck>;
- ti,clock-mult = <2>;
- ti,clock-div = <1>;
- ti,set-rate-parent;
- };
-
- dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m4x2_mul_ck>;
- ti,bit-shift = <0x1d>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- ti,set-rate-parent;
- };
-
- dpll4_m5_ck: dpll4_m5_ck@f40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <63>;
- reg = <0x0f40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&dpll4_m5_ck>;
- ti,clock-mult = <2>;
- ti,clock-div = <1>;
- ti,set-rate-parent;
- };
-
- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m5x2_mul_ck>;
- ti,bit-shift = <0x1e>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- ti,set-rate-parent;
- };
-
- dpll4_m6_ck: dpll4_m6_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <63>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m6_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m6x2_mul_ck>;
- ti,bit-shift = <0x1f>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- emu_per_alwon_ck: emu_per_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m6x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <7>;
- reg = <0x0d70>;
- };
-
- clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
- reg = <0x0d70>;
- };
-
- clkout2_src_ck: clkout2_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
- };
-
- sys_clkout2: sys_clkout2@d70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_src_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <64>;
- reg = <0x0d70>;
- ti,index-power-of-two;
- };
-
- mpu_ck: mpu_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll1_x2m2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- arm_fck: arm_fck@924 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mpu_ck>;
- reg = <0x0924>;
- ti,max-div = <2>;
- };
-
- emu_mpu_alwon_ck: emu_mpu_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mpu_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- l3_ick: l3_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- l4_ick: l4_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l3_ick>;
- ti,bit-shift = <2>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- rm_ick: rm_ick@c40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l4_ick>;
- ti,bit-shift = <1>;
- ti,max-div = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
- };
-
- gpt10_gate_fck: gpt10_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <11>;
- reg = <0x0a00>;
- };
-
- gpt10_mux_fck: gpt10_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0a40>;
- };
-
- gpt10_fck: gpt10_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
- };
-
- gpt11_gate_fck: gpt11_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <12>;
- reg = <0x0a00>;
- };
-
- gpt11_mux_fck: gpt11_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x0a40>;
- };
-
- gpt11_fck: gpt11_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
- };
-
- core_96m_fck: core_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mmchs2_fck: mmchs2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_fck: mmchs1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <24>;
- };
-
- i2c3_fck: i2c3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <17>;
- };
-
- i2c2_fck: i2c2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <16>;
- };
-
- i2c1_fck: i2c1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <15>;
- };
-
- mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <10>;
- reg = <0x0a00>;
- };
-
- mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <9>;
- reg = <0x0a00>;
- };
-
- core_48m_fck: core_48m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mcspi4_fck: mcspi4_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_fck: mcspi3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_fck: mcspi2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_fck: mcspi1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <18>;
- };
-
- uart2_fck: uart2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <14>;
- };
-
- uart1_fck: uart1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <13>;
- };
-
- core_12m_fck: core_12m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_12m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- hdq_fck: hdq_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_12m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <22>;
- };
-
- core_l3_ick: core_l3_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sdrc_ick: sdrc_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <1>;
- };
-
- gpmc_fck: gpmc_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- core_l4_ick: core_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mmchs2_ick: mmchs2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_ick: mmchs1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <24>;
- };
-
- hdq_ick: hdq_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <22>;
- };
-
- mcspi4_ick: mcspi4_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_ick: mcspi3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_ick: mcspi2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_ick: mcspi1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <18>;
- };
-
- i2c3_ick: i2c3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <17>;
- };
-
- i2c2_ick: i2c2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <16>;
- };
-
- i2c1_ick: i2c1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <15>;
- };
-
- uart2_ick: uart2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <14>;
- };
-
- uart1_ick: uart1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <13>;
- };
-
- gpt11_ick: gpt11_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <12>;
- };
-
- gpt10_ick: gpt10_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <11>;
- };
-
- mcbsp5_ick: mcbsp5_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <10>;
- };
-
- mcbsp1_ick: mcbsp1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <9>;
- };
-
- omapctrl_ick: omapctrl_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <6>;
- };
-
- dss_tv_fck: dss_tv_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_54m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss_96m_fck: dss_96m_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_96m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss2_alwon_fck: dss2_alwon_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0e00>;
- ti,bit-shift = <1>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- gpt1_gate_fck: gpt1_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <0>;
- reg = <0x0c00>;
- };
-
- gpt1_mux_fck: gpt1_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- reg = <0x0c40>;
- };
-
- gpt1_fck: gpt1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
- };
-
- aes2_ick: aes2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- ti,bit-shift = <28>;
- reg = <0x0a10>;
- };
-
- wkup_32k_fck: wkup_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio1_dbck: gpio1_dbck@c00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <3>;
- };
-
- sha12_ick: sha12_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <27>;
- };
-
- wdt2_fck: wdt2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <5>;
- };
-
- wdt2_ick: wdt2_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <5>;
- };
-
- wdt1_ick: wdt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <4>;
- };
-
- gpio1_ick: gpio1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <3>;
- };
-
- omap_32ksync_ick: omap_32ksync_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <2>;
- };
-
- gpt12_ick: gpt12_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <1>;
- };
-
- gpt1_ick: gpt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <0>;
- };
-
- per_96m_fck: per_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_alwon_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- per_48m_fck: per_48m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- uart3_fck: uart3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
- reg = <0x1000>;
- ti,bit-shift = <11>;
- };
-
- gpt2_gate_fck: gpt2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x1000>;
- };
-
- gpt2_mux_fck: gpt2_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- reg = <0x1040>;
- };
-
- gpt2_fck: gpt2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
- };
-
- gpt3_gate_fck: gpt3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1000>;
- };
-
- gpt3_mux_fck: gpt3_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <1>;
- reg = <0x1040>;
- };
-
- gpt3_fck: gpt3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
- };
-
- gpt4_gate_fck: gpt4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1000>;
- };
-
- gpt4_mux_fck: gpt4_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <2>;
- reg = <0x1040>;
- };
-
- gpt4_fck: gpt4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
- };
-
- gpt5_gate_fck: gpt5_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1000>;
- };
-
- gpt5_mux_fck: gpt5_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x1040>;
- };
-
- gpt5_fck: gpt5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
- };
-
- gpt6_gate_fck: gpt6_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1000>;
- };
-
- gpt6_mux_fck: gpt6_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1040>;
- };
-
- gpt6_fck: gpt6_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
- };
-
- gpt7_gate_fck: gpt7_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <8>;
- reg = <0x1000>;
- };
-
- gpt7_mux_fck: gpt7_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1040>;
- };
-
- gpt7_fck: gpt7_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
- };
-
- gpt8_gate_fck: gpt8_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <9>;
- reg = <0x1000>;
- };
-
- gpt8_mux_fck: gpt8_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1040>;
- };
-
- gpt8_fck: gpt8_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
- };
-
- gpt9_gate_fck: gpt9_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <10>;
- reg = <0x1000>;
- };
-
- gpt9_mux_fck: gpt9_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1040>;
- };
-
- gpt9_fck: gpt9_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
- };
-
- per_32k_alwon_fck: per_32k_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio6_dbck: gpio6_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <17>;
- };
-
- gpio5_dbck: gpio5_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <16>;
- };
-
- gpio4_dbck: gpio4_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <15>;
- };
-
- gpio3_dbck: gpio3_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <14>;
- };
-
- gpio2_dbck: gpio2_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <13>;
- };
-
- wdt3_fck: wdt3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <12>;
- };
-
- per_l4_ick: per_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio6_ick: gpio6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <17>;
- };
-
- gpio5_ick: gpio5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <16>;
- };
-
- gpio4_ick: gpio4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <15>;
- };
-
- gpio3_ick: gpio3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <14>;
- };
-
- gpio2_ick: gpio2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <13>;
- };
-
- wdt3_ick: wdt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <12>;
- };
-
- uart3_ick: uart3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <11>;
- };
-
- uart4_ick: uart4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <18>;
- };
-
- gpt9_ick: gpt9_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <10>;
- };
-
- gpt8_ick: gpt8_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <9>;
- };
-
- gpt7_ick: gpt7_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <8>;
- };
-
- gpt6_ick: gpt6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <7>;
- };
-
- gpt5_ick: gpt5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <6>;
- };
-
- gpt4_ick: gpt4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <5>;
- };
-
- gpt3_ick: gpt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <4>;
- };
-
- gpt2_ick: gpt2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <3>;
- };
-
- mcbsp2_ick: mcbsp2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <0>;
- };
-
- mcbsp3_ick: mcbsp3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <1>;
- };
-
- mcbsp4_ick: mcbsp4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <2>;
- };
-
- mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <0>;
- reg = <0x1000>;
- };
-
- mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <1>;
- reg = <0x1000>;
- };
-
- mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x1000>;
- };
-
- emu_src_mux_ck: emu_src_mux_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- reg = <0x1140>;
- };
-
- emu_src_ck: emu_src_ck {
- #clock-cells = <0>;
- compatible = "ti,clkdm-gate-clock";
- clocks = <&emu_src_mux_ck>;
- };
-
- pclk_fck: pclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- pclkx2_fck: pclkx2_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- atclk_fck: atclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- traceclk_src_fck: traceclk_src_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- ti,bit-shift = <2>;
- reg = <0x1140>;
- };
-
- traceclk_fck: traceclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&traceclk_src_fck>;
- ti,bit-shift = <11>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- secure_32k_fck: secure_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- gpt12_fck: gpt12_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&secure_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wdt1_fck: wdt1_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&secure_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ dummy_apb_pclk: dummy_apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ omap_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_38_4m_ck: virt_38_4m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ dpll4_ck: dpll4_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+ };
+
+ dpll4_m2_ck: dpll4_m2_ck@d48 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <63>;
+ reg = <0x0d48>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ omap_96m_alwon_fck: omap_96m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll3_ck: dpll3_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+ };
+
+ dpll3_m3_ck: dpll3_m3_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <31>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ emu_core_alwon_ck: emu_core_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sys_altclk: sys_altclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ dpll3_m2_ck: dpll3_m2_ck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <31>;
+ reg = <0x0d40>;
+ ti,index-starts-at-one;
+ };
+
+ core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll1_fck: dpll1_fck@940 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x0940>;
+ ti,index-starts-at-one;
+ };
+
+ dpll1_ck: dpll1_ck@904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll1_fck>;
+ reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+ };
+
+ dpll1_x2_ck: dpll1_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll1_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0944>;
+ ti,index-starts-at-one;
+ };
+
+ cm_96m_fck: cm_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ omap_96m_fck: omap_96m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0d40>;
+ };
+
+ dpll4_m3_ck: dpll4_m3_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <32>;
+ reg = <0x0e40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ omap_54m_fck: omap_54m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ ti,bit-shift = <5>;
+ reg = <0x0d40>;
+ };
+
+ cm_96m_d2_fck: cm_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cm_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_48m_fck: omap_48m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ ti,bit-shift = <3>;
+ reg = <0x0d40>;
+ };
+
+ omap_12m_fck: omap_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dpll4_m4_ck: dpll4_m4_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <32>;
+ reg = <0x0e40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll4_m4_ck>;
+ ti,clock-mult = <2>;
+ ti,clock-div = <1>;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
+ ti,bit-shift = <0x1d>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m5_ck: dpll4_m5_ck@f40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <63>;
+ reg = <0x0f40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll4_m5_ck>;
+ ti,clock-mult = <2>;
+ ti,clock-div = <1>;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m6_ck: dpll4_m6_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <63>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ emu_per_alwon_ck: emu_per_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0d70>;
+ };
+
+ clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ reg = <0x0d70>;
+ };
+
+ clkout2_src_ck: clkout2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+ };
+
+ sys_clkout2: sys_clkout2@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_src_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ reg = <0x0d70>;
+ ti,index-power-of-two;
+ };
+
+ mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_x2m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ arm_fck: arm_fck@924 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mpu_ck>;
+ reg = <0x0924>;
+ ti,max-div = <2>;
+ };
+
+ emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l3_ick: l3_ick@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,max-div = <3>;
+ reg = <0x0a40>;
+ ti,index-starts-at-one;
+ };
+
+ l4_ick: l4_ick@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <2>;
+ ti,max-div = <3>;
+ reg = <0x0a40>;
+ ti,index-starts-at-one;
+ };
+
+ rm_ick: rm_ick@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <1>;
+ ti,max-div = <3>;
+ reg = <0x0c40>;
+ ti,index-starts-at-one;
+ };
+
+ gpt10_gate_fck: gpt10_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x0a00>;
+ };
+
+ gpt10_mux_fck: gpt10_mux_fck@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0a40>;
+ };
+
+ gpt10_fck: gpt10_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+ };
+
+ gpt11_gate_fck: gpt11_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <12>;
+ reg = <0x0a00>;
+ };
+
+ gpt11_mux_fck: gpt11_mux_fck@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0a40>;
+ };
+
+ gpt11_fck: gpt11_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+ };
+
+ core_96m_fck: core_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mmchs2_fck: mmchs2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_fck: mmchs1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <24>;
+ };
+
+ i2c3_fck: i2c3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_fck: i2c2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_fck: i2c1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <15>;
+ };
+
+ mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <10>;
+ reg = <0x0a00>;
+ };
+
+ mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <9>;
+ reg = <0x0a00>;
+ };
+
+ core_48m_fck: core_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mcspi4_fck: mcspi4_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_fck: mcspi3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_fck: mcspi2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_fck: mcspi1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <18>;
+ };
+
+ uart2_fck: uart2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_fck: uart1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <13>;
+ };
+
+ core_12m_fck: core_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_12m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdq_fck: hdq_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_12m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <22>;
+ };
+
+ core_l3_ick: core_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sdrc_ick: sdrc_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <1>;
+ };
+
+ gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ core_l4_ick: core_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mmchs2_ick: mmchs2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_ick: mmchs1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <24>;
+ };
+
+ hdq_ick: hdq_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <22>;
+ };
+
+ mcspi4_ick: mcspi4_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_ick: mcspi3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_ick: mcspi2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_ick: mcspi1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <18>;
+ };
+
+ i2c3_ick: i2c3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_ick: i2c2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_ick: i2c1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <15>;
+ };
+
+ uart2_ick: uart2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_ick: uart1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <13>;
+ };
+
+ gpt11_ick: gpt11_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <12>;
+ };
+
+ gpt10_ick: gpt10_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <11>;
+ };
+
+ mcbsp5_ick: mcbsp5_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <10>;
+ };
+
+ mcbsp1_ick: mcbsp1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <9>;
+ };
+
+ omapctrl_ick: omapctrl_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <6>;
+ };
+
+ dss_tv_fck: dss_tv_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_54m_fck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <2>;
+ };
+
+ dss_96m_fck: dss_96m_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_96m_fck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <2>;
+ };
+
+ dss2_alwon_fck: dss2_alwon_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <1>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ gpt1_gate_fck: gpt1_gate_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0c00>;
+ };
+
+ gpt1_mux_fck: gpt1_mux_fck@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x0c40>;
+ };
+
+ gpt1_fck: gpt1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+ };
+
+ aes2_ick: aes2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <28>;
+ reg = <0x0a10>;
+ };
+
+ wkup_32k_fck: wkup_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio1_dbck: gpio1_dbck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <3>;
+ };
+
+ sha12_ick: sha12_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <27>;
+ };
+
+ wdt2_fck: wdt2_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <5>;
+ };
+
+ wdt2_ick: wdt2_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <5>;
+ };
+
+ wdt1_ick: wdt1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <4>;
+ };
+
+ gpio1_ick: gpio1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <3>;
+ };
+
+ omap_32ksync_ick: omap_32ksync_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <2>;
+ };
+
+ gpt12_ick: gpt12_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <1>;
+ };
+
+ gpt1_ick: gpt1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <0>;
+ };
+
+ per_96m_fck: per_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ per_48m_fck: per_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ uart3_fck: uart3_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <11>;
+ };
+
+ gpt2_gate_fck: gpt2_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x1000>;
+ };
+
+ gpt2_mux_fck: gpt2_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x1040>;
+ };
+
+ gpt2_fck: gpt2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+ };
+
+ gpt3_gate_fck: gpt3_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x1000>;
+ };
+
+ gpt3_mux_fck: gpt3_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x1040>;
+ };
+
+ gpt3_fck: gpt3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+ };
+
+ gpt4_gate_fck: gpt4_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x1000>;
+ };
+
+ gpt4_mux_fck: gpt4_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x1040>;
+ };
+
+ gpt4_fck: gpt4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+ };
+
+ gpt5_gate_fck: gpt5_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x1000>;
+ };
+
+ gpt5_mux_fck: gpt5_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x1040>;
+ };
+
+ gpt5_fck: gpt5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+ };
+
+ gpt6_gate_fck: gpt6_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x1000>;
+ };
+
+ gpt6_mux_fck: gpt6_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x1040>;
+ };
+
+ gpt6_fck: gpt6_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+ };
+
+ gpt7_gate_fck: gpt7_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1000>;
+ };
+
+ gpt7_mux_fck: gpt7_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x1040>;
+ };
+
+ gpt7_fck: gpt7_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+ };
+
+ gpt8_gate_fck: gpt8_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x1000>;
+ };
+
+ gpt8_mux_fck: gpt8_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x1040>;
+ };
+
+ gpt8_fck: gpt8_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+ };
+
+ gpt9_gate_fck: gpt9_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x1000>;
+ };
+
+ gpt9_mux_fck: gpt9_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x1040>;
+ };
+
+ gpt9_fck: gpt9_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+ };
+
+ per_32k_alwon_fck: per_32k_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio6_dbck: gpio6_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_dbck: gpio5_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_dbck: gpio4_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_dbck: gpio3_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_dbck: gpio2_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_fck: wdt3_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <12>;
+ };
+
+ per_l4_ick: per_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio6_ick: gpio6_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_ick: gpio5_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_ick: gpio4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_ick: gpio3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_ick: gpio2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_ick: wdt3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <12>;
+ };
+
+ uart3_ick: uart3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <11>;
+ };
+
+ uart4_ick: uart4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <18>;
+ };
+
+ gpt9_ick: gpt9_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <10>;
+ };
+
+ gpt8_ick: gpt8_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <9>;
+ };
+
+ gpt7_ick: gpt7_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <8>;
+ };
+
+ gpt6_ick: gpt6_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <7>;
+ };
+
+ gpt5_ick: gpt5_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt4_ick: gpt4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <5>;
+ };
+
+ gpt3_ick: gpt3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <4>;
+ };
+
+ gpt2_ick: gpt2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <3>;
+ };
+
+ mcbsp2_ick: mcbsp2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <0>;
+ };
+
+ mcbsp3_ick: mcbsp3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <1>;
+ };
+
+ mcbsp4_ick: mcbsp4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <2>;
+ };
+
+ mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <0>;
+ reg = <0x1000>;
+ };
+
+ mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <1>;
+ reg = <0x1000>;
+ };
+
+ mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x1000>;
+ };
+
+ emu_src_mux_ck: emu_src_mux_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ reg = <0x1140>;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+ };
+
+ pclk_fck: pclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <7>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ pclkx2_fck: pclkx2_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ atclk_fck: atclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <3>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ traceclk_src_fck: traceclk_src_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x1140>;
+ };
+
+ traceclk_fck: traceclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&traceclk_src_fck>;
+ ti,bit-shift = <11>;
+ ti,max-div = <7>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ secure_32k_fck: secure_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
};
&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>;
- };
-
- dpll3_clkdm: dpll3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll3_ck>;
- };
-
- dpll1_clkdm: dpll1_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll1_ck>;
- };
-
- per_clkdm: per_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>;
- };
-
- emu_clkdm: emu_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&emu_src_ck>;
- };
-
- dpll4_clkdm: dpll4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll4_ck>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
- };
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+ <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+ <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+ <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+ <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+ <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+ <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+ <&mcbsp4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+ };
};
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_6
projects / u-boot / commitdiff